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/external/elfutils/tests/
Drun-show-die-info.sh28 Offset : 11
29 CU offset : 11
38 Offset : 104
39 CU offset : 104
45 Offset : 127
46 CU offset : 127
52 Offset : 146
53 CU offset : 11
62 Offset : 239
63 CU offset : 104
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Drun-show-abbrev.sh25 abbrev[0]: attr[0]: code = 16, form = 6, offset = 0
26 abbrev[0]: attr[1]: code = 18, form = 1, offset = 2
27 abbrev[0]: attr[2]: code = 17, form = 1, offset = 4
28 abbrev[0]: attr[3]: code = 3, form = 8, offset = 6
29 abbrev[0]: attr[4]: code = 27, form = 8, offset = 8
30 abbrev[0]: attr[5]: code = 37, form = 8, offset = 10
31 abbrev[0]: attr[6]: code = 19, form = 11, offset = 12
33 abbrev[19]: attr[0]: code = 1, form = 19, offset = 19
34 abbrev[19]: attr[1]: code = 63, form = 12, offset = 21
35 abbrev[19]: attr[2]: code = 3, form = 8, offset = 23
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/external/mesa3d/src/intel/vulkan/grl/gpu/libs/
Dlsc_intrinsics_fallback.cl10 uint load_uchar_to_uint_L1UC_L3UC(global uchar* it, int offset)
12 return (uint)(it[offset]);
15 uint load_uchar_to_uint_L1UC_L3C(global uchar* it, int offset)
17 return (uint)(it[offset]);
20 uint load_uchar_to_uint_L1C_L3UC(global uchar* it, int offset)
22 return (uint)(it[offset]);
25 uint load_uchar_to_uint_L1C_L3C(global uchar* it, int offset)
27 return (uint)(it[offset]);
30 uint load_uchar_to_uint_L1S_L3UC(global uchar* it, int offset)
32 return (uint)(it[offset]);
[all …]
Dlsc_intrinsics.cl143 uint load_uchar_to_uint_L1UC_L3UC(global uchar* it, int offset)
145 return __builtin_IB_lsc_load_global_uchar_to_uint(it, offset, LSC_LDCC_L1UC_L3UC);
148 uint load_uchar_to_uint_L1UC_L3C(global uchar* it, int offset)
150 return __builtin_IB_lsc_load_global_uchar_to_uint(it, offset, LSC_LDCC_L1UC_L3C);
153 uint load_uchar_to_uint_L1C_L3UC(global uchar* it, int offset)
155 return __builtin_IB_lsc_load_global_uchar_to_uint(it, offset, LSC_LDCC_L1C_L3UC);
158 uint load_uchar_to_uint_L1C_L3C(global uchar* it, int offset)
160 return __builtin_IB_lsc_load_global_uchar_to_uint(it, offset, LSC_LDCC_L1C_L3C);
163 uint load_uchar_to_uint_L1S_L3UC(global uchar* it, int offset)
165 return __builtin_IB_lsc_load_global_uchar_to_uint(it, offset, LSC_LDCC_L1S_L3UC);
[all …]
Dlsc_intrinsics.h9 uint load_uchar_to_uint_L1UC_L3UC(global uchar* it, int offset);
10 uint load_uchar_to_uint_L1UC_L3C(global uchar* it, int offset);
11 uint load_uchar_to_uint_L1C_L3UC(global uchar* it, int offset);
12 uint load_uchar_to_uint_L1C_L3C(global uchar* it, int offset);
13 uint load_uchar_to_uint_L1S_L3UC(global uchar* it, int offset);
14 uint load_uchar_to_uint_L1S_L3C(global uchar* it, int offset);
15 uint load_uchar_to_uint_L1IAR_L3C(global uchar* it, int offset);
17 uint load_ushort_to_uint_L1UC_L3UC(global ushort* it, int offset);
18 uint load_ushort_to_uint_L1UC_L3C(global ushort* it, int offset);
19 uint load_ushort_to_uint_L1C_L3UC(global ushort* it, int offset);
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/external/mesa3d/src/freedreno/registers/dsi/
Ddsi_phy_7nm.xml8 <reg32 offset="0x00000" name="REVISION_ID0"/>
9 <reg32 offset="0x00004" name="REVISION_ID1"/>
10 <reg32 offset="0x00008" name="REVISION_ID2"/>
11 <reg32 offset="0x0000c" name="REVISION_ID3"/>
12 <reg32 offset="0x00010" name="CLK_CFG0"/>
13 <reg32 offset="0x00014" name="CLK_CFG1"/>
14 <reg32 offset="0x00018" name="GLBL_CTRL"/>
15 <reg32 offset="0x0001c" name="RBUF_CTRL"/>
16 <reg32 offset="0x00020" name="VREG_CTRL_0"/>
17 <reg32 offset="0x00024" name="CTRL_0"/>
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Ddsi_phy_10nm.xml8 <reg32 offset="0x00000" name="REVISION_ID0"/>
9 <reg32 offset="0x00004" name="REVISION_ID1"/>
10 <reg32 offset="0x00008" name="REVISION_ID2"/>
11 <reg32 offset="0x0000c" name="REVISION_ID3"/>
12 <reg32 offset="0x00010" name="CLK_CFG0"/>
13 <reg32 offset="0x00014" name="CLK_CFG1"/>
14 <reg32 offset="0x00018" name="GLBL_CTRL"/>
15 <reg32 offset="0x0001c" name="RBUF_CTRL"/>
16 <reg32 offset="0x00020" name="VREG_CTRL"/>
17 <reg32 offset="0x00024" name="CTRL_0"/>
[all …]
Ddsi_phy_28nm.xml8 <array offset="0x00000" name="LN" length="4" stride="0x40">
9 <reg32 offset="0x00" name="CFG_0"/>
10 <reg32 offset="0x04" name="CFG_1"/>
11 <reg32 offset="0x08" name="CFG_2"/>
12 <reg32 offset="0x0c" name="CFG_3"/>
13 <reg32 offset="0x10" name="CFG_4"/>
14 <reg32 offset="0x14" name="TEST_DATAPATH"/>
15 <reg32 offset="0x18" name="DEBUG_SEL"/>
16 <reg32 offset="0x1c" name="TEST_STR_0"/>
17 <reg32 offset="0x20" name="TEST_STR_1"/>
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Ddsi_phy_14nm.xml8 <reg32 offset="0x00000" name="REVISION_ID0"/>
9 <reg32 offset="0x00004" name="REVISION_ID1"/>
10 <reg32 offset="0x00008" name="REVISION_ID2"/>
11 <reg32 offset="0x0000c" name="REVISION_ID3"/>
12 <reg32 offset="0x00010" name="CLK_CFG0">
16 <reg32 offset="0x00014" name="CLK_CFG1">
19 <reg32 offset="0x00018" name="GLBL_TEST_CTRL">
22 <reg32 offset="0x0001C" name="CTRL_0"/>
23 <reg32 offset="0x00020" name="CTRL_1">
25 <reg32 offset="0x00024" name="HW_TRIGGER"/>
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Ddsi_phy_28nm_8960.xml9 <array offset="0x00000" name="LN" length="4" stride="0x40">
10 <reg32 offset="0x00" name="CFG_0"/>
11 <reg32 offset="0x04" name="CFG_1"/>
12 <reg32 offset="0x08" name="CFG_2"/>
13 <reg32 offset="0x0c" name="TEST_DATAPATH"/>
14 <reg32 offset="0x14" name="TEST_STR_0"/>
15 <reg32 offset="0x18" name="TEST_STR_1"/>
18 <reg32 offset="0x00100" name="LNCK_CFG_0"/>
19 <reg32 offset="0x00104" name="LNCK_CFG_1"/>
20 <reg32 offset="0x00108" name="LNCK_CFG_2"/>
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Ddsi_phy_v2.xml10 <reg32 offset="0x00200" name="PHY_PLL_CTRL_0">
13 <reg32 offset="0x00204" name="PHY_PLL_CTRL_1"/>
14 <reg32 offset="0x00208" name="PHY_PLL_CTRL_2"/>
15 <reg32 offset="0x0020c" name="PHY_PLL_CTRL_3"/>
16 <reg32 offset="0x00210" name="PHY_PLL_CTRL_4"/>
17 <reg32 offset="0x00214" name="PHY_PLL_CTRL_5"/>
18 <reg32 offset="0x00218" name="PHY_PLL_CTRL_6"/>
19 <reg32 offset="0x0021c" name="PHY_PLL_CTRL_7"/>
20 <reg32 offset="0x00220" name="PHY_PLL_CTRL_8"/>
21 <reg32 offset="0x00224" name="PHY_PLL_CTRL_9"/>
[all …]
/external/mesa3d/src/freedreno/fdl/
Dfd6_layout_test.c44 {.offset = 0, .pitch = 256},
45 {.offset = 8192, .pitch = 256},
46 {.offset = 12288, .pitch = 256},
47 {.offset = 14336, .pitch = 256},
48 {.offset = 15360, .pitch = 256},
49 {.offset = 15872, .pitch = 256},
67 {.offset = 0, .pitch = 4096},
68 {.offset = 65536, .pitch = 2048},
69 {.offset = 98304, .pitch = 1024},
70 {.offset = 114688, .pitch = 512},
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/external/mesa3d/src/freedreno/registers/hdmi/
Dhdmi.xml42 <reg32 offset="0x00000" name="CTRL">
47 <reg32 offset="0x00020" name="AUDIO_PKT_CTRL1">
50 <reg32 offset="0x00024" name="ACR_PKT_CTRL">
67 <reg32 offset="0x0028" name="VBI_PKT_CTRL">
87 <reg32 offset="0x0002c" name="INFOFRAME_CTRL0">
104 <reg32 offset="0x00030" name="INFOFRAME_CTRL1">
110 <reg32 offset="0x00034" name="GEN_PKT_CTRL">
140 <reg32 offset="0x00040" name="GC">
143 <reg32 offset="0x00044" name="AUDIO_PKT_CTRL2">
152 <reg32 offset="0x0006c" name="AVI_INFO" stride="4" length="4"/>
[all …]
/external/mesa3d/src/freedreno/registers/adreno/
Da6xx_gmu.xml43 <reg32 offset="0x80" name="GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL"/>
44 <reg32 offset="0x81" name="GMU_GX_SPTPRAC_POWER_CONTROL"/>
45 <reg32 offset="0xc00" name="GMU_CM3_ITCM_START"/>
46 <reg32 offset="0x1c00" name="GMU_CM3_DTCM_START"/>
47 <reg32 offset="0x23f0" name="GMU_NMI_CONTROL_STATUS"/>
48 <reg32 offset="0x23f8" name="GMU_BOOT_SLUMBER_OPTION"/>
49 <reg32 offset="0x23f9" name="GMU_GX_VOTE_IDX"/>
50 <reg32 offset="0x23fa" name="GMU_MX_VOTE_IDX"/>
51 <reg32 offset="0x23fc" name="GMU_DCVS_ACK_OPTION"/>
52 <reg32 offset="0x23fd" name="GMU_DCVS_PERF_SETTING"/>
[all …]
Da5xx.xml862 <reg32 offset="0x0800" name="CP_RB_BASE"/>
863 <reg32 offset="0x0801" name="CP_RB_BASE_HI"/>
864 <reg32 offset="0x0802" name="CP_RB_CNTL"/>
865 <reg32 offset="0x0804" name="CP_RB_RPTR_ADDR"/>
866 <reg32 offset="0x0805" name="CP_RB_RPTR_ADDR_HI"/>
867 <reg32 offset="0x0806" name="CP_RB_RPTR"/>
868 <reg32 offset="0x0807" name="CP_RB_WPTR"/>
869 <reg32 offset="0x0808" name="CP_PFP_STAT_ADDR"/>
870 <reg32 offset="0x0809" name="CP_PFP_STAT_DATA"/>
871 <reg32 offset="0x080b" name="CP_DRAW_STATE_ADDR"/>
[all …]
Dadreno_control_regs.xml19 <reg32 name="PREEMPT_INSTR" offset="0x04"/>
22 <reg32 name="SP" offset="0x05"/>
25 <reg32 name="STACK0" offset="0x08" type="hex"/>
26 <reg32 name="STACK1" offset="0x09" type="hex"/>
27 <reg32 name="STACK2" offset="0x0a" type="hex"/>
28 <reg32 name="STACK3" offset="0x0b" type="hex"/>
29 <reg32 name="STACK4" offset="0x0c" type="hex"/>
30 <reg32 name="STACK5" offset="0x0d" type="hex"/>
31 <reg32 name="STACK6" offset="0x0e" type="hex"/>
32 <reg32 name="STACK7" offset="0x0f" type="hex"/>
[all …]
/external/tpm2-tss/include/tss2/
Dtss2_mu.h28 size_t *offset);
34 size_t *offset,
42 size_t *offset);
48 size_t *offset,
56 size_t *offset);
62 size_t *offset,
70 size_t *offset);
76 size_t *offset,
84 size_t *offset);
90 size_t *offset,
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/external/flatbuffers/ts/
Dbyte-buffer.ts3 import { Offset, Table, IGeneratedObject } from "./types.js";
54 readInt8(offset: number): number {
55 return this.readUint8(offset) << 24 >> 24;
58 readUint8(offset: number): number {
59 return this.bytes_[offset];
62 readInt16(offset: number): number {
63 return this.readUint16(offset) << 16 >> 16;
66 readUint16(offset: number): number {
67 return this.bytes_[offset] | this.bytes_[offset + 1] << 8;
70 readInt32(offset: number): number {
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/external/libnetfilter_conntrack/src/expect/
Dsnprintf_xml.c57 unsigned int size = 0, offset = 0; in snprintf_expect_meta_xml() local
60 BUFFER_SIZE(ret, size, len, offset); in snprintf_expect_meta_xml()
63 ret = snprintf(buf+offset, len, in snprintf_expect_meta_xml()
66 BUFFER_SIZE(ret, size, len, offset); in snprintf_expect_meta_xml()
69 ret = snprintf(buf+offset, len, "<timeout>%u</timeout>", in snprintf_expect_meta_xml()
71 BUFFER_SIZE(ret, size, len, offset); in snprintf_expect_meta_xml()
74 ret = snprintf(buf+offset, len, "<class>%u</class>", in snprintf_expect_meta_xml()
76 BUFFER_SIZE(ret, size, len, offset); in snprintf_expect_meta_xml()
79 ret = snprintf(buf+offset, len, "<zone>%u</zone>", exp->zone); in snprintf_expect_meta_xml()
80 BUFFER_SIZE(ret, size, len, offset); in snprintf_expect_meta_xml()
[all …]
/external/llvm/unittests/Support/
DDataExtractorTest.cpp28 uint32_t offset = 0; in TEST() local
30 EXPECT_EQ(0x80U, DE.getU8(&offset)); in TEST()
31 EXPECT_EQ(1U, offset); in TEST()
32 offset = 0; in TEST()
33 EXPECT_EQ(0x8090U, DE.getU16(&offset)); in TEST()
34 EXPECT_EQ(2U, offset); in TEST()
35 offset = 0; in TEST()
36 EXPECT_EQ(0x8090FFFFU, DE.getU32(&offset)); in TEST()
37 EXPECT_EQ(4U, offset); in TEST()
38 offset = 0; in TEST()
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/external/flatbuffers/tests/optional_scalars/
Dscalar-stuff.js25 const offset = this.bb.__offset(this.bb_pos, 4);
26 return offset ? this.bb.readInt8(this.bb_pos + offset) : 0;
29 const offset = this.bb.__offset(this.bb_pos, 6);
30 return offset ? this.bb.readInt8(this.bb_pos + offset) : null;
33 const offset = this.bb.__offset(this.bb_pos, 8);
34 return offset ? this.bb.readInt8(this.bb_pos + offset) : 42;
37 const offset = this.bb.__offset(this.bb_pos, 10);
38 return offset ? this.bb.readUint8(this.bb_pos + offset) : 0;
41 const offset = this.bb.__offset(this.bb_pos, 12);
42 return offset ? this.bb.readUint8(this.bb_pos + offset) : null;
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/external/flatbuffers/tests/ts/ts-flat-files/
Dmonster_test_generated.ts159 static createUnused(builder:flatbuffers.Builder, a: number):flatbuffers.Offset {
162 return builder.offset();
186 const offset = this.bb!.__offset(this.bb_pos, 4); constant
187 …return offset ? (obj || new TableA()).__init(this.bb!.__indirect(this.bb_pos + offset), this.bb!) …
194 static addA(builder:flatbuffers.Builder, aOffset:flatbuffers.Offset) {
198 static endTableB(builder:flatbuffers.Builder):flatbuffers.Offset {
199 const offset = builder.endObject(); constant
200 return offset;
203 static createTableB(builder:flatbuffers.Builder, aOffset:flatbuffers.Offset):flatbuffers.Offset {
237 const offset = this.bb!.__offset(this.bb_pos, 4); constant
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/external/mesa3d/src/amd/common/
Dac_msgpack.c56 msgpack->offset = 0; in ac_msgpack_init()
67 if ((msgpack->offset + data_size) > msgpack->mem_size) { in ac_msgpack_resize_if_required()
87 msgpack->mem[msgpack->offset] = MSGPACK_FIXMAP_OP | n; in ac_msgpack_add_fixmap_op()
88 msgpack->offset = msgpack->offset + 1; in ac_msgpack_add_fixmap_op()
92 msgpack->mem[msgpack->offset] = MSGPACK_MAP16_OP; in ac_msgpack_add_fixmap_op()
93 *((uint16_t*)&msgpack->mem[msgpack->offset + 1]) = util_bswap16(n); in ac_msgpack_add_fixmap_op()
94 msgpack->offset = msgpack->offset + 3; in ac_msgpack_add_fixmap_op()
98 msgpack->mem[msgpack->offset] = MSGPACK_MAP32_OP; in ac_msgpack_add_fixmap_op()
99 *((unsigned int*)&msgpack->mem[msgpack->offset + 1]) = util_bswap32(n); in ac_msgpack_add_fixmap_op()
100 msgpack->offset = msgpack->offset + 5; in ac_msgpack_add_fixmap_op()
[all …]
/external/vixl/test/aarch32/
Dtest-assembler-cond-rd-memop-immediate-8192-a32.cc73 int32_t offset; member
100 const TestData kTests[] = {{{pl, r13, r0, plus, 0, Offset},
103 "pl r13 r0 plus 0 Offset",
105 {{ge, r5, r3, plus, 0, Offset},
108 "ge r5 r3 plus 0 Offset",
110 {{cc, r0, r4, plus, 0, Offset},
113 "cc r0 r4 plus 0 Offset",
115 {{ge, r0, r0, plus, 0, Offset},
118 "ge r0 r0 plus 0 Offset",
120 {{eq, r12, r3, plus, 0, Offset},
[all …]
Dtest-assembler-cond-rd-memop-immediate-512-a32.cc73 int32_t offset; member
100 const TestData kTests[] = {{{pl, r13, r0, plus, 0, Offset},
103 "pl r13 r0 plus 0 Offset",
105 {{ge, r5, r3, plus, 0, Offset},
108 "ge r5 r3 plus 0 Offset",
110 {{cc, r0, r4, plus, 0, Offset},
113 "cc r0 r4 plus 0 Offset",
115 {{ge, r0, r0, plus, 0, Offset},
118 "ge r0 r0 plus 0 Offset",
120 {{eq, r12, r3, plus, 0, Offset},
[all …]

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