1 /*
2 * Copyright © 2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /**
25 * @file brw_inst.h
26 *
27 * A representation of i965 EU assembly instructions, with helper methods to
28 * get and set various fields. This is the actual hardware format.
29 */
30
31 #ifndef BRW_INST_H
32 #define BRW_INST_H
33
34 #include <assert.h>
35 #include <stdint.h>
36
37 #include "brw_eu_defines.h"
38 #include "brw_isa_info.h"
39 #include "brw_reg_type.h"
40 #include "dev/intel_device_info.h"
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* brw_context.h has a forward declaration of brw_inst, so name the struct. */
47 typedef struct brw_inst {
48 uint64_t data[2];
49 } brw_inst;
50
51 static inline uint64_t brw_inst_bits(const brw_inst *inst,
52 unsigned high, unsigned low);
53 static inline void brw_inst_set_bits(brw_inst *inst,
54 unsigned high, unsigned low,
55 uint64_t value);
56
57 #define FC(name, hi9, lo9, hi12, lo12, assertions) \
58 static inline void \
59 brw_inst_set_##name(const struct intel_device_info *devinfo, \
60 brw_inst *inst, uint64_t v) \
61 { \
62 assert(assertions); \
63 if (devinfo->ver >= 12) \
64 brw_inst_set_bits(inst, hi12, lo12, v); \
65 else \
66 brw_inst_set_bits(inst, hi9, lo9, v); \
67 } \
68 static inline uint64_t \
69 brw_inst_##name(const struct intel_device_info *devinfo, \
70 const brw_inst *inst) \
71 { \
72 assert(assertions); \
73 if (devinfo->ver >= 12) \
74 return brw_inst_bits(inst, hi12, lo12); \
75 else \
76 return brw_inst_bits(inst, hi9, lo9); \
77 }
78
79 /* A simple macro for fields which stay in the same place on all generations,
80 * except for Gfx12!
81 */
82 #define F(name, hi9, lo9, hi12, lo12) FC(name, hi9, lo9, hi12, lo12, true)
83
84 /* A simple macro for fields which stay in the same place on all generations,
85 * except for Gfx12 and Gfx20.
86 */
87 #define F20(name, hi9, lo9, hi12, lo12, hi20, lo20) \
88 static inline void \
89 brw_inst_set_##name(const struct intel_device_info *devinfo, \
90 brw_inst *inst, uint64_t v) \
91 { \
92 if (devinfo->ver >= 20) \
93 brw_inst_set_bits(inst, hi20, lo20, v); \
94 else if (devinfo->ver >= 12) \
95 brw_inst_set_bits(inst, hi12, lo12, v); \
96 else \
97 brw_inst_set_bits(inst, hi9, lo9, v); \
98 } \
99 static inline uint64_t \
100 brw_inst_##name(const struct intel_device_info *devinfo, \
101 const brw_inst *inst) \
102 { \
103 if (devinfo->ver >= 20) \
104 return brw_inst_bits(inst, hi20, lo20); \
105 else if (devinfo->ver >= 12) \
106 return brw_inst_bits(inst, hi12, lo12); \
107 else \
108 return brw_inst_bits(inst, hi9, lo9); \
109 }
110
111 #define FV20(name, hi9, lo9, hi12, lo12, hi20, lo20) \
112 static inline void \
113 brw_inst_set_##name(const struct intel_device_info *devinfo, \
114 brw_inst *inst, uint64_t v) \
115 { \
116 if (devinfo->ver >= 20) \
117 brw_inst_set_bits(inst, hi20, lo20, v & 0x7); \
118 else if (devinfo->ver >= 12) \
119 brw_inst_set_bits(inst, hi12, lo12, v); \
120 else \
121 brw_inst_set_bits(inst, hi9, lo9, v); \
122 } \
123 static inline uint64_t \
124 brw_inst_##name(const struct intel_device_info *devinfo, \
125 const brw_inst *inst) \
126 { \
127 if (devinfo->ver >= 20) \
128 return brw_inst_bits(inst, hi20, lo20) == 0x7 ? 0xF : \
129 brw_inst_bits(inst, hi20, lo20); \
130 else if (devinfo->ver >= 12) \
131 return brw_inst_bits(inst, hi12, lo12); \
132 else \
133 return brw_inst_bits(inst, hi9, lo9); \
134 }
135
136 #define FD20(name, hi9, lo9, hi12, lo12, hi20, lo20, zero20) \
137 static inline void \
138 brw_inst_set_##name(const struct intel_device_info *devinfo, \
139 brw_inst *inst, uint64_t v) \
140 { \
141 if (devinfo->ver >= 20) { \
142 brw_inst_set_bits(inst, hi20, lo20, v >> 1); \
143 if (zero20 == -1) \
144 assert((v & 1) == 0); \
145 else \
146 brw_inst_set_bits(inst, zero20, zero20, v & 1); \
147 } else if (devinfo->ver >= 12) \
148 brw_inst_set_bits(inst, hi12, lo12, v); \
149 else \
150 brw_inst_set_bits(inst, hi9, lo9, v); \
151 } \
152 static inline uint64_t \
153 brw_inst_##name(const struct intel_device_info *devinfo, \
154 const brw_inst *inst) \
155 { \
156 if (devinfo->ver >= 20) \
157 return (brw_inst_bits(inst, hi20, lo20) << 1) | \
158 (zero20 == -1 ? 0 : \
159 brw_inst_bits(inst, zero20, zero20)); \
160 else if (devinfo->ver >= 12) \
161 return brw_inst_bits(inst, hi12, lo12); \
162 else \
163 return brw_inst_bits(inst, hi9, lo9); \
164 }
165
166 /* Macro for fields that gained extra discontiguous MSBs in Gfx12 (specified
167 * by hi12ex-lo12ex).
168 */
169 #define FFDC(name, hi9, lo9, hi12ex, lo12ex, hi12, lo12, assertions) \
170 static inline void \
171 brw_inst_set_##name(const struct intel_device_info *devinfo, \
172 brw_inst *inst, uint64_t value) \
173 { \
174 assert(assertions); \
175 if (devinfo->ver >= 12) { \
176 const unsigned k = hi12 - lo12 + 1; \
177 if (hi12ex != -1 && lo12ex != -1) \
178 brw_inst_set_bits(inst, hi12ex, lo12ex, value >> k); \
179 brw_inst_set_bits(inst, hi12, lo12, value & ((1ull << k) - 1)); \
180 } else { \
181 brw_inst_set_bits(inst, hi9, lo9, value); \
182 } \
183 } \
184 static inline uint64_t \
185 brw_inst_##name(const struct intel_device_info *devinfo, const brw_inst *inst)\
186 { \
187 assert(assertions); \
188 if (devinfo->ver >= 12) { \
189 const unsigned k = hi12 - lo12 + 1; \
190 return (hi12ex == -1 || lo12ex == -1 ? 0 : \
191 brw_inst_bits(inst, hi12ex, lo12ex) << k) | \
192 brw_inst_bits(inst, hi12, lo12); \
193 } else { \
194 return brw_inst_bits(inst, hi9, lo9); \
195 } \
196 }
197
198 #define FD(name, hi9, lo9, hi12ex, lo12ex, hi12, lo12) \
199 FFDC(name, hi9, lo9, hi12ex, lo12ex, hi12, lo12, true)
200
201 /* Macro for fields that didn't move across generations until Gfx12, and then
202 * gained extra discontiguous bits.
203 */
204 #define FDC(name, hi9, lo9, hi12ex, lo12ex, hi12, lo12, assertions) \
205 FFDC(name, hi9, lo9, hi12ex, lo12ex, hi12, lo12, assertions)
206
207
208 /* Macro for the 2-bit register file field, which on Gfx12+ is stored as the
209 * variable length combination of an IsImm (hi12) bit and an additional file
210 * (lo12) bit.
211 */
212 #define FI(name, hi9, lo9, hi12, lo12) \
213 static inline void \
214 brw_inst_set_##name(const struct intel_device_info *devinfo, \
215 brw_inst *inst, uint64_t value) \
216 { \
217 if (devinfo->ver >= 12) { \
218 brw_inst_set_bits(inst, hi12, hi12, value >> 1); \
219 if ((value >> 1) == 0) \
220 brw_inst_set_bits(inst, lo12, lo12, value & 1); \
221 } else { \
222 brw_inst_set_bits(inst, hi9, lo9, value); \
223 } \
224 } \
225 static inline uint64_t \
226 brw_inst_##name(const struct intel_device_info *devinfo, const brw_inst *inst)\
227 { \
228 if (devinfo->ver >= 12) { \
229 return (brw_inst_bits(inst, hi12, hi12) << 1) | \
230 (brw_inst_bits(inst, hi12, hi12) == 0 ? \
231 brw_inst_bits(inst, lo12, lo12) : 1); \
232 } else { \
233 return brw_inst_bits(inst, hi9, lo9); \
234 } \
235 }
236
237 /* Macro for fields that become a constant in Gfx12+ not actually represented
238 * in the instruction.
239 */
240 #define FK(name, hi9, lo9, const12) \
241 static inline void \
242 brw_inst_set_##name(const struct intel_device_info *devinfo, \
243 brw_inst *inst, uint64_t v) \
244 { \
245 if (devinfo->ver >= 12) \
246 assert(v == (const12)); \
247 else \
248 brw_inst_set_bits(inst, hi9, lo9, v); \
249 } \
250 static inline uint64_t \
251 brw_inst_##name(const struct intel_device_info *devinfo, \
252 const brw_inst *inst) \
253 { \
254 if (devinfo->ver >= 12) \
255 return (const12); \
256 else \
257 return brw_inst_bits(inst, hi9, lo9); \
258 }
259
260 FV20(src1_vstride, /* 9+ */ 120, 117, /* 12+ */ 119, 116, /* 20+ */ 118, 116)
261 F(src1_width, /* 9+ */ 116, 114, /* 12+ */ 115, 113)
262 F(src1_da16_swiz_w, /* 9+ */ 115, 114, /* 12+ */ -1, -1)
263 F(src1_da16_swiz_z, /* 9+ */ 113, 112, /* 12+ */ -1, -1)
264 F(src1_hstride, /* 9+ */ 113, 112, /* 12+ */ 97, 96)
265 F(src1_address_mode, /* 9+ */ 111, 111, /* 12+ */ 112, 112)
266 /** Src1.SrcMod @{ */
267 F(src1_negate, /* 9+ */ 110, 110, /* 12+ */ 121, 121)
268 F(src1_abs, /* 9+ */ 109, 109, /* 12+ */ 120, 120)
269 /** @} */
270 F(src1_ia_subreg_nr, /* 9+ */ 108, 105, /* 12+ */ 111, 108)
271 F(src1_da_reg_nr, /* 9+ */ 108, 101, /* 12+ */ 111, 104)
272 F(src1_da16_subreg_nr, /* 9+ */ 100, 100, /* 12+ */ -1, -1)
273 FD20(src1_da1_subreg_nr, /* 9+ */ 100, 96, /* 12+ */ 103, 99, /* 20+ */ 103, 99, -1)
274 F(src1_da16_swiz_y, /* 9+ */ 99, 98, /* 12+ */ -1, -1)
275 F(src1_da16_swiz_x, /* 9+ */ 97, 96, /* 12+ */ -1, -1)
276 F(src1_reg_hw_type, /* 9+ */ 94, 91, /* 12+ */ 91, 88)
277 FI(src1_reg_file, /* 9+ */ 90, 89, /* 12+ */ 47, 98)
278 F(src1_is_imm, /* 9+ */ -1, -1, /* 12+ */ 47, 47)
279 FV20(src0_vstride, /* 9+ */ 88, 85, /* 12+ */ 87, 84, /* 20+ */ 86, 84)
280 F(src0_width, /* 9+ */ 84, 82, /* 12+ */ 83, 81)
281 F(src0_da16_swiz_w, /* 9+ */ 83, 82, /* 12+ */ -1, -1)
282 F(src0_da16_swiz_z, /* 9+ */ 81, 80, /* 12+ */ -1, -1)
283 F(src0_hstride, /* 9+ */ 81, 80, /* 12+ */ 65, 64)
284 F(src0_address_mode, /* 9+ */ 79, 79, /* 12+ */ 80, 80)
285 /** Src0.SrcMod @{ */
286 F(src0_negate, /* 9+ */ 78, 78, /* 12+ */ 45, 45)
287 F(src0_abs, /* 9+ */ 77, 77, /* 12+ */ 44, 44)
288 /** @} */
289 F(src0_ia_subreg_nr, /* 9+ */ 76, 73, /* 12+ */ 79, 76)
290 F(src0_da_reg_nr, /* 9+ */ 76, 69, /* 12+ */ 79, 72)
291 F(src0_da16_subreg_nr, /* 9+ */ 68, 68, /* 12+ */ -1, -1)
292 FD20(src0_da1_subreg_nr, /* 9+ */ 68, 64, /* 12+ */ 71, 67, /* 20+ */ 71, 67, 87)
293 F(src0_da16_swiz_y, /* 9+ */ 67, 66, /* 12+ */ -1, -1)
294 F(src0_da16_swiz_x, /* 9+ */ 65, 64, /* 12+ */ -1, -1)
295 F(dst_address_mode, /* 9+ */ 63, 63, /* 12+ */ 35, 35)
296 F(dst_hstride, /* 9+ */ 62, 61, /* 12+ */ 49, 48)
297 F(dst_ia_subreg_nr, /* 9+ */ 60, 57, /* 12+ */ 63, 60)
298 F(dst_da_reg_nr, /* 9+ */ 60, 53, /* 12+ */ 63, 56)
299 F(dst_da16_subreg_nr, /* 9+ */ 52, 52, /* 12+ */ -1, -1)
300 FD20(dst_da1_subreg_nr, /* 9+ */ 52, 48, /* 12+ */ 55, 51, /* 20+ */ 55, 51, 33)
301 F(da16_writemask, /* 9+ */ 51, 48, /* 12+ */ -1, -1) /* Dst.ChanEn */
302 F(src0_reg_hw_type, /* 9+ */ 46, 43, /* 12+ */ 43, 40)
303 FI(src0_reg_file, /* 9+ */ 42, 41, /* 12+ */ 46, 66)
304 F(src0_is_imm, /* 9+ */ -1, -1, /* 12+ */ 46, 46)
305 F(dst_reg_hw_type, /* 9+ */ 40, 37, /* 12+ */ 39, 36)
306 F(dst_reg_file, /* 9+ */ 36, 35, /* 12+ */ 50, 50)
307 F(mask_control, /* 9+ */ 34, 34, /* 12+ */ 31, 31)
308 F20(flag_reg_nr, /* 9+ */ 33, 33, /* 12+ */ 23, 23, /* 20+ */ 23, 22)
309 F20(flag_subreg_nr, /* 9+ */ 32, 32, /* 12+ */ 22, 22, /* 20+ */ 21, 21)
310 F(saturate, /* 9+ */ 31, 31, /* 12+ */ 34, 34)
311 F(debug_control, /* 9+ */ 30, 30, /* 12+ */ 30, 30)
312 F(cmpt_control, /* 9+ */ 29, 29, /* 12+ */ 29, 29)
313 F(branch_control, /* 9+ */ 28, 28, /* 12+ */ 33, 33)
314 FC(acc_wr_control, /* 9+ */ 28, 28, /* 12+ */ 33, 33, devinfo->ver < 20)
315 F(cond_modifier, /* 9+ */ 27, 24, /* 12+ */ 95, 92)
316 F(math_function, /* 9+ */ 27, 24, /* 12+ */ 95, 92)
317 F20(exec_size, /* 9+ */ 23, 21, /* 12+ */ 18, 16, /* 20+ */ 20, 18)
318 F(pred_inv, /* 9+ */ 20, 20, /* 12+ */ 28, 28)
319 F20(pred_control, /* 9+ */ 19, 16, /* 12+ */ 27, 24, /* 20+ */ 27, 26)
320 F(thread_control, /* 9+ */ 15, 14, /* 12+ */ -1, -1)
321 F(atomic_control, /* 9+ */ -1, -1, /* 12+ */ 32, 32)
322 F20(qtr_control, /* 9+ */ 13, 12, /* 12+ */ 21, 20, /* 20+ */ 25, 24)
323 F20(nib_control, /* 9+ */ 11, 11, /* 12+ */ 19, 19, /* 20+ */ -1, -1)
324 F(no_dd_check, /* 9+ */ 10, 10, /* 12+ */ -1, -1)
325 F(no_dd_clear, /* 9+ */ 9, 9, /* 12+ */ -1, -1)
326 F20(swsb, /* 9+ */ -1, -1, /* 12+ */ 15, 8, /* 20+ */ 17, 8)
327 FK(access_mode, /* 9+ */ 8, 8, /* 12+ */ BRW_ALIGN_1)
328 /* Bit 7 is Reserved (for future Opcode expansion) */
329 F(hw_opcode, /* 9+ */ 6, 0, /* 12+ */ 6, 0)
330
331 /**
332 * Three-source instructions:
333 * @{
334 */
335 F(3src_src2_reg_nr, /* 9+ */ 125, 118, /* 12+ */ 127, 120) /* same in align1 */
336 F(3src_a16_src2_subreg_nr, /* 9+ */ 117, 115, /* 12+ */ -1, -1) /* Extra discontiguous bit on CHV? */
337 F(3src_a16_src2_swizzle, /* 9+ */ 114, 107, /* 12+ */ -1, -1)
338 F(3src_a16_src2_rep_ctrl, /* 9+ */ 106, 106, /* 12+ */ -1, -1)
339 F(3src_src1_reg_nr, /* 9+ */ 104, 97, /* 12+ */ 111, 104) /* same in align1 */
340 F(3src_a16_src1_subreg_nr, /* 9+ */ 96, 94, /* 12+ */ -1, -1) /* Extra discontiguous bit on CHV? */
341 F(3src_a16_src1_swizzle, /* 9+ */ 93, 86, /* 12+ */ -1, -1)
342 F(3src_a16_src1_rep_ctrl, /* 9+ */ 85, 85, /* 12+ */ -1, -1)
343 F(3src_src0_reg_nr, /* 9+ */ 83, 76, /* 12+ */ 79, 72) /* same in align1 */
344 F(3src_a16_src0_subreg_nr, /* 9+ */ 75, 73, /* 12+ */ -1, -1) /* Extra discontiguous bit on CHV? */
345 F(3src_a16_src0_swizzle, /* 9+ */ 72, 65, /* 12+ */ -1, -1)
346 F(3src_a16_src0_rep_ctrl, /* 9+ */ 64, 64, /* 12+ */ -1, -1)
347 F(3src_dst_reg_nr, /* 9+ */ 63, 56, /* 12+ */ 63, 56) /* same in align1 */
348 F(3src_a16_dst_subreg_nr, /* 9+ */ 55, 53, /* 12+ */ -1, -1)
349 F(3src_a16_dst_writemask, /* 9+ */ 52, 49, /* 12+ */ -1, -1)
350 F(3src_a16_nib_ctrl, /* 9+ */ 11, 11, /* 12+ */ -1, -1) /* only exists on IVB+ */
351 F(3src_a16_dst_hw_type, /* 9+ */ 48, 46, /* 12+ */ -1, -1) /* only exists on IVB+ */
352 F(3src_a16_src_hw_type, /* 9+ */ 45, 43, /* 12+ */ -1, -1)
353 F(3src_src2_negate, /* 9+ */ 42, 42, /* 12+ */ 85, 85)
354 F(3src_src2_abs, /* 9+ */ 41, 41, /* 12+ */ 84, 84)
355 F(3src_src1_negate, /* 9+ */ 40, 40, /* 12+ */ 87, 87)
356 F(3src_src1_abs, /* 9+ */ 39, 39, /* 12+ */ 86, 86)
357 F(3src_src0_negate, /* 9+ */ 38, 38, /* 12+ */ 45, 45)
358 F(3src_src0_abs, /* 9+ */ 37, 37, /* 12+ */ 44, 44)
359 F(3src_a16_src1_type, /* 9+ */ 36, 36, /* 12+ */ -1, -1)
360 F(3src_a16_src2_type, /* 9+ */ 35, 35, /* 12+ */ -1, -1)
361 F(3src_a16_flag_reg_nr, /* 9+ */ 33, 33, /* 12+ */ -1, -1)
362 F(3src_a16_flag_subreg_nr, /* 9+ */ 32, 32, /* 12+ */ -1, -1)
363 F(3src_saturate, /* 9+ */ 31, 31, /* 12+ */ 34, 34)
364 F(3src_debug_control, /* 9+ */ 30, 30, /* 12+ */ 30, 30)
365 F(3src_cmpt_control, /* 9+ */ 29, 29, /* 12+ */ 29, 29)
366 FC(3src_acc_wr_control, /* 9+ */ 28, 28, /* 12+ */ 33, 33, devinfo->ver < 20)
367 F(3src_cond_modifier, /* 9+ */ 27, 24, /* 12+ */ 95, 92)
368 F(3src_exec_size, /* 9+ */ 23, 21, /* 12+ */ 18, 16)
369 F(3src_pred_inv, /* 9+ */ 20, 20, /* 12+ */ 28, 28)
370 F20(3src_pred_control, /* 9+ */ 19, 16, /* 12+ */ 27, 24, /* 20+ */ 27, 26)
371 F(3src_thread_control, /* 9+ */ 15, 14, /* 12+ */ -1, -1)
372 F(3src_atomic_control, /* 9+ */ -1, -1, /* 12+ */ 32, 32)
373 F20(3src_qtr_control, /* 9+ */ 13, 12, /* 12+ */ 21, 20, /* 20+ */ 25, 24)
374 F(3src_no_dd_check, /* 9+ */ 10, 10, /* 12+ */ -1, -1)
375 F(3src_no_dd_clear, /* 9+ */ 9, 9, /* 12+ */ -1, -1)
376 F(3src_mask_control, /* 9+ */ 34, 34, /* 12+ */ 31, 31)
377 FK(3src_access_mode, /* 9+ */ 8, 8, /* 12+ */ BRW_ALIGN_1)
378 F(3src_swsb, /* 9+ */ -1, -1, /* 12+ */ 15, 8)
379 /* Bit 7 is Reserved (for future Opcode expansion) */
380 F(3src_hw_opcode, /* 9+ */ 6, 0, /* 12+ */ 6, 0)
381 /** @} */
382
383 #define REG_TYPE(reg) \
384 static inline void \
385 brw_inst_set_3src_a16_##reg##_type(const struct intel_device_info *devinfo, \
386 brw_inst *inst, enum brw_reg_type type) \
387 { \
388 unsigned hw_type = brw_reg_type_to_a16_hw_3src_type(devinfo, type); \
389 brw_inst_set_3src_a16_##reg##_hw_type(devinfo, inst, hw_type); \
390 } \
391 \
392 static inline enum brw_reg_type \
393 brw_inst_3src_a16_##reg##_type(const struct intel_device_info *devinfo, \
394 const brw_inst *inst) \
395 { \
396 unsigned hw_type = brw_inst_3src_a16_##reg##_hw_type(devinfo, inst); \
397 return brw_a16_hw_3src_type_to_reg_type(devinfo, hw_type); \
398 }
399
REG_TYPE(dst)400 REG_TYPE(dst)
401 REG_TYPE(src)
402 #undef REG_TYPE
403
404 /**
405 * Three-source align1 instructions:
406 * @{
407 */
408 /* Reserved 127:126 */
409 /* src2_reg_nr same in align16 */
410 FD20(3src_a1_src2_subreg_nr,/* 9+ */ 117, 113, /* 12+ */ 119, 115, /* 20+ */ 119, 115, -1)
411 FC(3src_a1_src2_hstride, /* 9+ */ 112, 111, /* 12+ */ 113, 112, devinfo->ver >= 10)
412 /* Reserved 110:109. src2 vstride is an implied parameter */
413 FC(3src_a1_src2_hw_type, /* 9+ */ 108, 106, /* 12+ */ 82, 80, devinfo->ver >= 10)
414 /* Reserved 105 */
415 /* src1_reg_nr same in align16 */
416 FD20(3src_a1_src1_subreg_nr, /* 9+ */ 96, 92, /* 12+ */ 103, 99, /* 20+ */ 103, 99, -1)
417 FC(3src_a1_src1_hstride, /* 9+ */ 91, 90, /* 12+ */ 97, 96, devinfo->ver >= 10)
418 FDC(3src_a1_src1_vstride, /* 9+ */ 89, 88, /* 12+ */ 91, 91, 83, 83, devinfo->ver >= 10)
419 FC(3src_a1_src1_hw_type, /* 9+ */ 87, 85, /* 12+ */ 90, 88, devinfo->ver >= 10)
420 /* Reserved 84 */
421 /* src0_reg_nr same in align16 */
422 FD20(3src_a1_src0_subreg_nr, /* 9+ */ 75, 71, /* 12+ */ 71, 67, /* 20+ */ 71, 67, -1)
423 FC(3src_a1_src0_hstride, /* 9+ */ 70, 69, /* 12+ */ 65, 64, devinfo->ver >= 10)
424 FDC(3src_a1_src0_vstride, /* 9+ */ 68, 67, /* 12+ */ 43, 43, 35, 35, devinfo->ver >= 10)
425 FC(3src_a1_src0_hw_type, /* 9+ */ 66, 64, /* 12+ */ 42, 40, devinfo->ver >= 10)
426 /* dst_reg_nr same in align16 */
427 FC(3src_a1_dst_subreg_nr, /* 9+ */ 55, 54, /* 12+ */ 55, 54, devinfo->ver >= 10)
428 FC(3src_a1_special_acc, /* 9+ */ 55, 52, /* 12+ */ 54, 51, devinfo->ver >= 10) /* aliases dst_subreg_nr */
429 /* Reserved 51:50 */
430 FC(3src_a1_dst_hstride, /* 9+ */ 49, 49, /* 12+ */ 48, 48, devinfo->ver >= 10)
431 FC(3src_a1_dst_hw_type, /* 9+ */ 48, 46, /* 12+ */ 38, 36, devinfo->ver >= 10)
432 FI(3src_a1_src2_reg_file, /* 9+ */ 45, 45, /* 12+ */ 47, 114)
433 FC(3src_a1_src1_reg_file, /* 9+ */ 44, 44, /* 12+ */ 98, 98, devinfo->ver >= 10)
434 FI(3src_a1_src0_reg_file, /* 9+ */ 43, 43, /* 12+ */ 46, 66)
435
436 F(3src_a1_src2_is_imm, /* 9+ */ -1, -1, /* 12+ */ 47, 47)
437 F(3src_a1_src0_is_imm, /* 9+ */ -1, -1, /* 12+ */ 46, 46)
438
439 /* Source Modifier fields same in align16 */
440 FC(3src_a1_dst_reg_file, /* 9+ */ 36, 36, /* 12+ */ 50, 50, devinfo->ver >= 10)
441 FC(3src_a1_exec_type, /* 9+ */ 35, 35, /* 12+ */ 39, 39, devinfo->ver >= 10)
442 /* Fields below this same in align16 */
443 /** @} */
444
445 #define REG_TYPE(reg) \
446 static inline void \
447 brw_inst_set_3src_a1_##reg##_type(const struct intel_device_info *devinfo, \
448 brw_inst *inst, enum brw_reg_type type) \
449 { \
450 UNUSED enum gfx10_align1_3src_exec_type exec_type = \
451 (enum gfx10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo, \
452 inst); \
453 if (brw_reg_type_is_floating_point(type)) { \
454 assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT); \
455 } else { \
456 assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_INT); \
457 } \
458 unsigned hw_type = brw_reg_type_to_a1_hw_3src_type(devinfo, type); \
459 brw_inst_set_3src_a1_##reg##_hw_type(devinfo, inst, hw_type); \
460 } \
461 \
462 static inline enum brw_reg_type \
463 brw_inst_3src_a1_##reg##_type(const struct intel_device_info *devinfo, \
464 const brw_inst *inst) \
465 { \
466 enum gfx10_align1_3src_exec_type exec_type = \
467 (enum gfx10_align1_3src_exec_type) brw_inst_3src_a1_exec_type(devinfo, \
468 inst); \
469 unsigned hw_type = brw_inst_3src_a1_##reg##_hw_type(devinfo, inst); \
470 return brw_a1_hw_3src_type_to_reg_type(devinfo, hw_type, exec_type); \
471 }
472
473 REG_TYPE(dst)
474 REG_TYPE(src0)
475 REG_TYPE(src1)
476 REG_TYPE(src2)
477 #undef REG_TYPE
478
479 /**
480 * Three-source align1 instruction immediates:
481 * @{
482 */
483 static inline uint16_t
484 brw_inst_3src_a1_src0_imm(ASSERTED const struct intel_device_info *devinfo,
485 const brw_inst *insn)
486 {
487 assert(devinfo->ver >= 10);
488 if (devinfo->ver >= 12)
489 return brw_inst_bits(insn, 79, 64);
490 else
491 return brw_inst_bits(insn, 82, 67);
492 }
493
494 static inline uint16_t
brw_inst_3src_a1_src2_imm(ASSERTED const struct intel_device_info * devinfo,const brw_inst * insn)495 brw_inst_3src_a1_src2_imm(ASSERTED const struct intel_device_info *devinfo,
496 const brw_inst *insn)
497 {
498 assert(devinfo->ver >= 10);
499 if (devinfo->ver >= 12)
500 return brw_inst_bits(insn, 127, 112);
501 else
502 return brw_inst_bits(insn, 124, 109);
503 }
504
505 static inline void
brw_inst_set_3src_a1_src0_imm(ASSERTED const struct intel_device_info * devinfo,brw_inst * insn,uint16_t value)506 brw_inst_set_3src_a1_src0_imm(ASSERTED const struct intel_device_info *devinfo,
507 brw_inst *insn, uint16_t value)
508 {
509 assert(devinfo->ver >= 10);
510 if (devinfo->ver >= 12)
511 brw_inst_set_bits(insn, 79, 64, value);
512 else
513 brw_inst_set_bits(insn, 82, 67, value);
514 }
515
516 static inline void
brw_inst_set_3src_a1_src2_imm(ASSERTED const struct intel_device_info * devinfo,brw_inst * insn,uint16_t value)517 brw_inst_set_3src_a1_src2_imm(ASSERTED const struct intel_device_info *devinfo,
518 brw_inst *insn, uint16_t value)
519 {
520 assert(devinfo->ver >= 10);
521 if (devinfo->ver >= 12)
522 brw_inst_set_bits(insn, 127, 112, value);
523 else
524 brw_inst_set_bits(insn, 124, 109, value);
525 }
526 /** @} */
527
528 /**
529 * Three-source systolic instructions:
530 * @{
531 */
532 F(dpas_3src_src2_reg_nr, /* 9+ */ -1, -1, /* 12+ */ 127, 120)
533 F(dpas_3src_src2_subreg_nr, /* 9+ */ -1, -1, /* 12+ */ 119, 115)
534 F(dpas_3src_src2_reg_file, /* 9+ */ -1, -1, /* 12+ */ 114, 114)
535 F(dpas_3src_src1_reg_nr, /* 9+ */ -1, -1, /* 12+ */ 111, 104)
536 F(dpas_3src_src1_subreg_nr, /* 9+ */ -1, -1, /* 12+ */ 103, 99)
537 F(dpas_3src_src1_reg_file, /* 9+ */ -1, -1, /* 12+ */ 98, 98)
538 F(dpas_3src_src1_hw_type, /* 9+ */ -1, -1, /* 12+ */ 90, 88)
539 F(dpas_3src_src1_subbyte, /* 9+ */ -1, -1, /* 12+ */ 87, 86)
540 F(dpas_3src_src2_subbyte, /* 9+ */ -1, -1, /* 12+ */ 85, 84)
541 F(dpas_3src_src2_hw_type, /* 9+ */ -1, -1, /* 12+ */ 82, 80)
542 F(dpas_3src_src0_reg_nr, /* 9+ */ -1, -1, /* 12+ */ 79, 72)
543 F(dpas_3src_src0_subreg_nr, /* 9+ */ -1, -1, /* 12+ */ 71, 67)
544 F(dpas_3src_src0_reg_file, /* 9+ */ -1, -1, /* 12+ */ 66, 66)
545 F(dpas_3src_dst_reg_nr, /* 9+ */ -1, -1, /* 12+ */ 63, 56)
546 F(dpas_3src_dst_subreg_nr, /* 9+ */ -1, -1, /* 12+ */ 55, 51)
547 F(dpas_3src_dst_reg_file, /* 9+ */ -1, -1, /* 12+ */ 50, 50)
548 F(dpas_3src_sdepth, /* 9+ */ -1, -1, /* 12+ */ 49, 48)
549 F(dpas_3src_rcount, /* 9+ */ -1, -1, /* 12+ */ 45, 43)
550 F(dpas_3src_src0_hw_type, /* 9+ */ -1, -1, /* 12+ */ 42, 40)
551 F(dpas_3src_exec_type, /* 9+ */ -1, -1, /* 12+ */ 39, 39)
552 F(dpas_3src_dst_hw_type, /* 9+ */ -1, -1, /* 12+ */ 38, 36)
553 /** @} */
554
555 #define REG_TYPE(reg) \
556 static inline void \
557 brw_inst_set_dpas_3src_##reg##_type(const struct intel_device_info *devinfo, \
558 brw_inst *inst, enum brw_reg_type type) \
559 { \
560 UNUSED enum gfx10_align1_3src_exec_type exec_type = \
561 (enum gfx10_align1_3src_exec_type) brw_inst_dpas_3src_exec_type(devinfo,\
562 inst); \
563 if (brw_reg_type_is_floating_point(type)) { \
564 assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_FLOAT); \
565 } else { \
566 assert(exec_type == BRW_ALIGN1_3SRC_EXEC_TYPE_INT); \
567 } \
568 unsigned hw_type = brw_reg_type_to_a1_hw_3src_type(devinfo, type); \
569 brw_inst_set_dpas_3src_##reg##_hw_type(devinfo, inst, hw_type); \
570 } \
571 \
572 static inline enum brw_reg_type \
573 brw_inst_dpas_3src_##reg##_type(const struct intel_device_info *devinfo, \
574 const brw_inst *inst) \
575 { \
576 enum gfx10_align1_3src_exec_type exec_type = \
577 (enum gfx10_align1_3src_exec_type) brw_inst_dpas_3src_exec_type(devinfo,\
578 inst); \
579 unsigned hw_type = brw_inst_dpas_3src_##reg##_hw_type(devinfo, inst); \
580 return brw_a1_hw_3src_type_to_reg_type(devinfo, hw_type, exec_type); \
581 }
582
REG_TYPE(dst)583 REG_TYPE(dst)
584 REG_TYPE(src0)
585 REG_TYPE(src1)
586 REG_TYPE(src2)
587 #undef REG_TYPE
588
589 /**
590 * Flow control instruction bits:
591 * @{
592 */
593 static inline void
594 brw_inst_set_uip(const struct intel_device_info *devinfo,
595 brw_inst *inst, int32_t value)
596 {
597 if (devinfo->ver >= 12)
598 brw_inst_set_src1_is_imm(devinfo, inst, 1);
599
600 brw_inst_set_bits(inst, 95, 64, (uint32_t)value);
601 }
602
603 static inline int32_t
brw_inst_uip(const struct intel_device_info * devinfo,const brw_inst * inst)604 brw_inst_uip(const struct intel_device_info *devinfo, const brw_inst *inst)
605 {
606 return brw_inst_bits(inst, 95, 64);
607 }
608
609 static inline void
brw_inst_set_jip(const struct intel_device_info * devinfo,brw_inst * inst,int32_t value)610 brw_inst_set_jip(const struct intel_device_info *devinfo,
611 brw_inst *inst, int32_t value)
612 {
613 if (devinfo->ver >= 12)
614 brw_inst_set_src0_is_imm(devinfo, inst, 1);
615
616 brw_inst_set_bits(inst, 127, 96, (uint32_t)value);
617 }
618
619 static inline int32_t
brw_inst_jip(const struct intel_device_info * devinfo,const brw_inst * inst)620 brw_inst_jip(const struct intel_device_info *devinfo, const brw_inst *inst)
621 {
622 return brw_inst_bits(inst, 127, 96);
623 }
624 /** @} */
625
626 /**
627 * SEND instructions:
628 * @{
629 */
630 F(send_ex_desc_ia_subreg_nr, /* 9+ */ 82, 80, /* 12+ */ 42, 40)
631 F(send_src0_address_mode, /* 9+ */ 79, 79, /* 12+ */ -1, -1)
632 F(send_sel_reg32_desc, /* 9+ */ 77, 77, /* 12+ */ 48, 48)
633 F(send_sel_reg32_ex_desc, /* 9+ */ 61, 61, /* 12+ */ 49, 49)
634 F(send_src0_reg_file, /* 9+ */ 42, 41, /* 12+ */ 66, 66)
635 F(send_src1_reg_nr, /* 9+ */ 51, 44, /* 12+ */ 111, 104)
636 FC(send_src1_len, /* 9+ */ -1, -1, /* 12+ */ 103, 99, devinfo->verx10 >= 125)
637 F(send_src1_reg_file, /* 9+ */ 36, 36, /* 12+ */ 98, 98)
638 F(send_dst_reg_file, /* 9+ */ 35, 35, /* 12+ */ 50, 50)
639 FC(send_ex_bso, /* 9+ */ -1, -1, /* 12+ */ 39, 39, devinfo->verx10 >= 125)
640 /** @} */
641
642 /* Message descriptor bits */
643 #define MD(x) ((x) + 96)
644 #define MD12(x) ((x) >= 30 ? (x) - 30 + 122 : \
645 (x) >= 25 ? (x) - 25 + 67 : \
646 (x) >= 20 ? (x) - 20 + 51 : \
647 (x) >= 11 ? (x) - 11 + 113 : \
648 (x) - 0 + 81)
649
650 /**
651 * Set the SEND(C) message descriptor immediate.
652 *
653 * This doesn't include the SFID nor the EOT field that were considered to be
654 * part of the message descriptor by ancient versions of the BSpec, because
655 * they are present in the instruction even if the message descriptor is
656 * provided indirectly in the address register, so we want to specify them
657 * separately.
658 */
659 static inline void
brw_inst_set_send_desc(const struct intel_device_info * devinfo,brw_inst * inst,uint32_t value)660 brw_inst_set_send_desc(const struct intel_device_info *devinfo,
661 brw_inst *inst, uint32_t value)
662 {
663 if (devinfo->ver >= 12) {
664 brw_inst_set_bits(inst, 123, 122, GET_BITS(value, 31, 30));
665 brw_inst_set_bits(inst, 71, 67, GET_BITS(value, 29, 25));
666 brw_inst_set_bits(inst, 55, 51, GET_BITS(value, 24, 20));
667 brw_inst_set_bits(inst, 121, 113, GET_BITS(value, 19, 11));
668 brw_inst_set_bits(inst, 91, 81, GET_BITS(value, 10, 0));
669 } else {
670 brw_inst_set_bits(inst, 126, 96, value);
671 assert(value >> 31 == 0);
672 }
673 }
674
675 /**
676 * Get the SEND(C) message descriptor immediate.
677 *
678 * \sa brw_inst_set_send_desc().
679 */
680 static inline uint32_t
brw_inst_send_desc(const struct intel_device_info * devinfo,const brw_inst * inst)681 brw_inst_send_desc(const struct intel_device_info *devinfo,
682 const brw_inst *inst)
683 {
684 if (devinfo->ver >= 12) {
685 return (brw_inst_bits(inst, 123, 122) << 30 |
686 brw_inst_bits(inst, 71, 67) << 25 |
687 brw_inst_bits(inst, 55, 51) << 20 |
688 brw_inst_bits(inst, 121, 113) << 11 |
689 brw_inst_bits(inst, 91, 81));
690 } else {
691 return brw_inst_bits(inst, 126, 96);
692 }
693 }
694
695 /**
696 * Set the SEND(C) message extended descriptor immediate.
697 *
698 * This doesn't include the SFID nor the EOT field that were considered to be
699 * part of the extended message descriptor by some versions of the BSpec,
700 * because they are present in the instruction even if the extended message
701 * descriptor is provided indirectly in a register, so we want to specify them
702 * separately.
703 */
704 static inline void
brw_inst_set_send_ex_desc(const struct intel_device_info * devinfo,brw_inst * inst,uint32_t value)705 brw_inst_set_send_ex_desc(const struct intel_device_info *devinfo,
706 brw_inst *inst, uint32_t value)
707 {
708 if (devinfo->ver >= 12) {
709 brw_inst_set_bits(inst, 127, 124, GET_BITS(value, 31, 28));
710 brw_inst_set_bits(inst, 97, 96, GET_BITS(value, 27, 26));
711 brw_inst_set_bits(inst, 65, 64, GET_BITS(value, 25, 24));
712 brw_inst_set_bits(inst, 47, 35, GET_BITS(value, 23, 11));
713 brw_inst_set_bits(inst, 103, 99, GET_BITS(value, 10, 6));
714 assert(GET_BITS(value, 5, 0) == 0);
715 } else {
716 assert(devinfo->ver >= 9);
717 brw_inst_set_bits(inst, 94, 91, GET_BITS(value, 31, 28));
718 brw_inst_set_bits(inst, 88, 85, GET_BITS(value, 27, 24));
719 brw_inst_set_bits(inst, 83, 80, GET_BITS(value, 23, 20));
720 brw_inst_set_bits(inst, 67, 64, GET_BITS(value, 19, 16));
721 assert(GET_BITS(value, 15, 0) == 0);
722 }
723 }
724
725 /**
726 * Set the SENDS(C) message extended descriptor immediate.
727 *
728 * This doesn't include the SFID nor the EOT field that were considered to be
729 * part of the extended message descriptor by some versions of the BSpec,
730 * because they are present in the instruction even if the extended message
731 * descriptor is provided indirectly in a register, so we want to specify them
732 * separately.
733 */
734 static inline void
brw_inst_set_sends_ex_desc(const struct intel_device_info * devinfo,brw_inst * inst,uint32_t value)735 brw_inst_set_sends_ex_desc(const struct intel_device_info *devinfo,
736 brw_inst *inst, uint32_t value)
737 {
738 if (devinfo->ver >= 12) {
739 brw_inst_set_send_ex_desc(devinfo, inst, value);
740 } else {
741 brw_inst_set_bits(inst, 95, 80, GET_BITS(value, 31, 16));
742 assert(GET_BITS(value, 15, 10) == 0);
743 brw_inst_set_bits(inst, 67, 64, GET_BITS(value, 9, 6));
744 assert(GET_BITS(value, 5, 0) == 0);
745 }
746 }
747
748 /**
749 * Get the SEND(C) message extended descriptor immediate.
750 *
751 * \sa brw_inst_set_send_ex_desc().
752 */
753 static inline uint32_t
brw_inst_send_ex_desc(const struct intel_device_info * devinfo,const brw_inst * inst)754 brw_inst_send_ex_desc(const struct intel_device_info *devinfo,
755 const brw_inst *inst)
756 {
757 if (devinfo->ver >= 12) {
758 return (brw_inst_bits(inst, 127, 124) << 28 |
759 brw_inst_bits(inst, 97, 96) << 26 |
760 brw_inst_bits(inst, 65, 64) << 24 |
761 brw_inst_bits(inst, 47, 35) << 11 |
762 brw_inst_bits(inst, 103, 99) << 6);
763 } else {
764 assert(devinfo->ver >= 9);
765 return (brw_inst_bits(inst, 94, 91) << 28 |
766 brw_inst_bits(inst, 88, 85) << 24 |
767 brw_inst_bits(inst, 83, 80) << 20 |
768 brw_inst_bits(inst, 67, 64) << 16);
769 }
770 }
771
772 /**
773 * Get the SENDS(C) message extended descriptor immediate.
774 *
775 * \sa brw_inst_set_send_ex_desc().
776 */
777 static inline uint32_t
brw_inst_sends_ex_desc(const struct intel_device_info * devinfo,const brw_inst * inst)778 brw_inst_sends_ex_desc(const struct intel_device_info *devinfo,
779 const brw_inst *inst)
780 {
781 if (devinfo->ver >= 12) {
782 return brw_inst_send_ex_desc(devinfo, inst);
783 } else {
784 return (brw_inst_bits(inst, 95, 80) << 16 |
785 brw_inst_bits(inst, 67, 64) << 6);
786 }
787 }
788
789 /**
790 * Fields for SEND messages:
791 * @{
792 */
793 F(eot, /* 9+ */ 127, 127, /* 12+ */ 34, 34)
794 F(mlen, /* 9+ */ 124, 121, /* 12+ */ MD12(28), MD12(25))
795 F(rlen, /* 9+ */ 120, 116, /* 12+ */ MD12(24), MD12(20))
796 F(header_present, /* 9+ */ 115, 115, /* 12+ */ MD12(19), MD12(19))
797 F(gateway_notify, /* 9+ */ MD(16), MD(15), /* 12+ */ -1, -1)
798 FD(function_control, /* 9+ */ 114, 96, /* 12+ */ MD12(18), MD12(11), MD12(10), MD12(0))
799 F(gateway_subfuncid, /* 9+ */ MD(2), MD(0), /* 12+ */ MD12(2), MD12(0))
800 F(sfid, /* 9+ */ 27, 24, /* 12+ */ 95, 92)
801 F(null_rt, /* 9+ */ 80, 80, /* 12+ */ 44, 44) /* actually only Gfx11+ */
802 F(send_rta_index, /* 9+ */ -1, -1, /* 12+ */ 38, 36)
803 /** @} */
804
805 /**
806 * URB message function control bits:
807 * @{
808 */
809 F(urb_per_slot_offset, /* 9+ */ MD(17), MD(17), /* 12+ */ MD12(17), MD12(17))
810 F(urb_channel_mask_present, /* 9+ */ MD(15), MD(15), /* 12+ */ MD12(15), MD12(15))
811 F(urb_swizzle_control, /* 9+ */ MD(15), MD(15), /* 12+ */ -1, -1)
812 FD(urb_global_offset, /* 9+ */ MD(14), MD(4), /* 12+ */ MD12(14), MD12(11), MD12(10), MD12(4))
813 F(urb_opcode, /* 9+ */ MD( 3), MD(0), /* 12+ */ MD12(3), MD12(0))
814 /** @} */
815
816 /**
817 * Sampler message function control bits:
818 * @{
819 */
820 F(sampler_simd_mode, /* 9+ */ MD(18), MD(17), /* 12+ */ MD12(18), MD12(17))
821 F(sampler_msg_type, /* 9+ */ MD(16), MD(12), /* 12+ */ MD12(16), MD12(12))
822 FD(sampler, /* 9+ */ MD(11), MD(8), /* 12+ */ MD12(11), MD12(11), MD12(10), MD12(8))
823 F(binding_table_index, /* 9+ */ MD(7), MD(0), /* 12+ */ MD12(7), MD12(0)) /* also used by other messages */
824 /** @} */
825
826 /**
827 * Data port message function control bits:
828 * @{
829 */
830 F(dp_category, /* 9+ */ MD(18), MD(18), /* 12+ */ MD12(18), MD12(18))
831
832 F(dp_read_msg_type, /* 9+ */ MD(17), MD(14), /* 12+ */ MD12(17), MD12(14))
833 F(dp_write_msg_type, /* 9+ */ MD(17), MD(14), /* 12+ */ MD12(17), MD12(14))
834 FD(dp_read_msg_control, /* 9+ */ MD(13), MD( 8), /* 12+ */ MD12(13), MD12(11), MD12(10), MD12(8))
835 FD(dp_write_msg_control, /* 9+ */ MD(13), MD( 8), /* 12+ */ MD12(13), MD12(11), MD12(10), MD12(8))
836
837 F(dp_msg_type, /* 9+ */ MD(18), MD(14), /* 12+ */ MD12(18), MD12(14))
838 FD(dp_msg_control, /* 9+ */ MD(13), MD( 8), /* 12+ */ MD12(13), MD12(11), MD12(10), MD12(8))
839 /** @} */
840
841 /**
842 * Scratch message bits:
843 * @{
844 */
845 F(scratch_read_write, /* 9+ */ MD(17), MD(17), /* 12+ */ MD12(17), MD12(17)) /* 0 = read, 1 = write */
846 F(scratch_type, /* 9+ */ MD(16), MD(16), /* 12+ */ -1, -1) /* 0 = OWord, 1 = DWord */
847 F(scratch_invalidate_after_read, /* 9+ */ MD(15), MD(15), /* 12+ */ MD12(15), MD12(15))
848 F(scratch_block_size, /* 9+ */ MD(13), MD(12), /* 12+ */ MD12(13), MD12(12))
849 FD(scratch_addr_offset,
850 /* 9: */ MD(11), MD(0),
851 /* 12: */ MD12(11), MD12(11), MD12(10), MD12(0))
852 /** @} */
853
854 /**
855 * Render Target message function control bits:
856 * @{
857 */
858 F(rt_last, /* 9+ */ MD(12), MD(12), /* 12+ */ MD12(12), MD12(12))
859 F(rt_slot_group, /* 9+ */ MD(11), MD(11), /* 12+ */ MD12(11), MD12(11))
860 F(rt_message_type, /* 9+ */ MD(10), MD( 8), /* 12+ */ MD12(10), MD12(8))
861 /** @} */
862
863 /**
864 * Thread Spawn message function control bits:
865 * @{
866 */
867 FC(ts_resource_select, /* 9+ */ MD( 4), MD( 4), /* 12+ */ -1, -1, devinfo->ver < 11)
868 FC(ts_request_type, /* 9+ */ MD( 1), MD( 1), /* 12+ */ -1, -1, devinfo->ver < 11)
869 F(ts_opcode, /* 9+ */ MD( 0), MD( 0), /* 12+ */ MD12(0), MD12(0))
870 /** @} */
871
872 /**
873 * Pixel Interpolator message function control bits:
874 * @{
875 */
876 F(pi_simd_mode, /* 9+ */ MD(16), MD(16), /* 12+ */ MD12(16), MD12(16))
877 F(pi_nopersp, /* 9+ */ MD(14), MD(14), /* 12+ */ MD12(14), MD12(14))
878 F(pi_message_type, /* 9+ */ MD(13), MD(12), /* 12+ */ MD12(13), MD12(12))
879 F(pi_slot_group, /* 9+ */ MD(11), MD(11), /* 12+ */ MD12(11), MD12(11))
880 F(pi_message_data, /* 9+ */ MD(7), MD(0), /* 12+ */ MD12(7), MD12(0))
881 /** @} */
882
883 /**
884 * Immediates:
885 * @{
886 */
887 static inline int
brw_inst_imm_d(const struct intel_device_info * devinfo,const brw_inst * insn)888 brw_inst_imm_d(const struct intel_device_info *devinfo, const brw_inst *insn)
889 {
890 (void) devinfo;
891 return brw_inst_bits(insn, 127, 96);
892 }
893
894 static inline unsigned
brw_inst_imm_ud(const struct intel_device_info * devinfo,const brw_inst * insn)895 brw_inst_imm_ud(const struct intel_device_info *devinfo, const brw_inst *insn)
896 {
897 (void) devinfo;
898 return brw_inst_bits(insn, 127, 96);
899 }
900
901 static inline uint64_t
brw_inst_imm_uq(const struct intel_device_info * devinfo,const brw_inst * insn)902 brw_inst_imm_uq(const struct intel_device_info *devinfo,
903 const brw_inst *insn)
904 {
905 if (devinfo->ver >= 12) {
906 return brw_inst_bits(insn, 95, 64) << 32 |
907 brw_inst_bits(insn, 127, 96);
908 } else {
909 return brw_inst_bits(insn, 127, 64);
910 }
911 }
912
913 static inline float
brw_inst_imm_f(const struct intel_device_info * devinfo,const brw_inst * insn)914 brw_inst_imm_f(const struct intel_device_info *devinfo, const brw_inst *insn)
915 {
916 union {
917 float f;
918 uint32_t u;
919 } ft;
920 (void) devinfo;
921 ft.u = brw_inst_bits(insn, 127, 96);
922 return ft.f;
923 }
924
925 static inline double
brw_inst_imm_df(const struct intel_device_info * devinfo,const brw_inst * insn)926 brw_inst_imm_df(const struct intel_device_info *devinfo, const brw_inst *insn)
927 {
928 union {
929 double d;
930 uint64_t u;
931 } dt;
932 dt.u = brw_inst_imm_uq(devinfo, insn);
933 return dt.d;
934 }
935
936 static inline void
brw_inst_set_imm_d(const struct intel_device_info * devinfo,brw_inst * insn,int value)937 brw_inst_set_imm_d(const struct intel_device_info *devinfo,
938 brw_inst *insn, int value)
939 {
940 (void) devinfo;
941 return brw_inst_set_bits(insn, 127, 96, value);
942 }
943
944 static inline void
brw_inst_set_imm_ud(const struct intel_device_info * devinfo,brw_inst * insn,unsigned value)945 brw_inst_set_imm_ud(const struct intel_device_info *devinfo,
946 brw_inst *insn, unsigned value)
947 {
948 (void) devinfo;
949 return brw_inst_set_bits(insn, 127, 96, value);
950 }
951
952 static inline void
brw_inst_set_imm_f(const struct intel_device_info * devinfo,brw_inst * insn,float value)953 brw_inst_set_imm_f(const struct intel_device_info *devinfo,
954 brw_inst *insn, float value)
955 {
956 union {
957 float f;
958 uint32_t u;
959 } ft;
960 (void) devinfo;
961 ft.f = value;
962 brw_inst_set_bits(insn, 127, 96, ft.u);
963 }
964
965 static inline void
brw_inst_set_imm_df(const struct intel_device_info * devinfo,brw_inst * insn,double value)966 brw_inst_set_imm_df(const struct intel_device_info *devinfo,
967 brw_inst *insn, double value)
968 {
969 union {
970 double d;
971 uint64_t u;
972 } dt;
973 (void) devinfo;
974 dt.d = value;
975
976 if (devinfo->ver >= 12) {
977 brw_inst_set_bits(insn, 95, 64, dt.u >> 32);
978 brw_inst_set_bits(insn, 127, 96, dt.u & 0xFFFFFFFF);
979 } else {
980 brw_inst_set_bits(insn, 127, 64, dt.u);
981 }
982 }
983
984 static inline void
brw_inst_set_imm_uq(const struct intel_device_info * devinfo,brw_inst * insn,uint64_t value)985 brw_inst_set_imm_uq(const struct intel_device_info *devinfo,
986 brw_inst *insn, uint64_t value)
987 {
988 (void) devinfo;
989 if (devinfo->ver >= 12) {
990 brw_inst_set_bits(insn, 95, 64, value >> 32);
991 brw_inst_set_bits(insn, 127, 96, value & 0xFFFFFFFF);
992 } else {
993 brw_inst_set_bits(insn, 127, 64, value);
994 }
995 }
996
997 /** @} */
998
999 #define REG_TYPE(reg) \
1000 static inline void \
1001 brw_inst_set_##reg##_file_type(const struct intel_device_info *devinfo, \
1002 brw_inst *inst, enum brw_reg_file file, \
1003 enum brw_reg_type type) \
1004 { \
1005 assert(file <= BRW_IMMEDIATE_VALUE); \
1006 unsigned hw_type = brw_reg_type_to_hw_type(devinfo, file, type); \
1007 brw_inst_set_##reg##_reg_file(devinfo, inst, file); \
1008 brw_inst_set_##reg##_reg_hw_type(devinfo, inst, hw_type); \
1009 } \
1010 \
1011 static inline enum brw_reg_type \
1012 brw_inst_##reg##_type(const struct intel_device_info *devinfo, \
1013 const brw_inst *inst) \
1014 { \
1015 unsigned file = __builtin_strcmp("dst", #reg) == 0 ? \
1016 (unsigned) BRW_GENERAL_REGISTER_FILE : \
1017 brw_inst_##reg##_reg_file(devinfo, inst); \
1018 unsigned hw_type = brw_inst_##reg##_reg_hw_type(devinfo, inst); \
1019 return brw_hw_type_to_reg_type(devinfo, (enum brw_reg_file)file, hw_type); \
1020 }
1021
1022 REG_TYPE(dst)
REG_TYPE(src0)1023 REG_TYPE(src0)
1024 REG_TYPE(src1)
1025 #undef REG_TYPE
1026
1027
1028 /* The AddrImm fields are split into two discontiguous sections on Gfx9+ */
1029 #define BRW_IA1_ADDR_IMM(reg, g9_nine, g9_high, g9_low, \
1030 g12_high, g12_low, g20_high, g20_low, g20_zero) \
1031 static inline void \
1032 brw_inst_set_##reg##_ia1_addr_imm(const struct \
1033 intel_device_info *devinfo, \
1034 brw_inst *inst, \
1035 unsigned value) \
1036 { \
1037 if (devinfo->ver >= 20) { \
1038 assert((value & ~0x7ff) == 0); \
1039 brw_inst_set_bits(inst, g20_high, g20_low, value >> 1); \
1040 if (g20_zero == -1) \
1041 assert((value & 1) == 0); \
1042 else \
1043 brw_inst_set_bits(inst, g20_zero, g20_zero, value & 1); \
1044 } else if (devinfo->ver >= 12) { \
1045 assert((value & ~0x3ff) == 0); \
1046 brw_inst_set_bits(inst, g12_high, g12_low, value); \
1047 } else { \
1048 assert((value & ~0x3ff) == 0); \
1049 brw_inst_set_bits(inst, g9_high, g9_low, value & 0x1ff); \
1050 brw_inst_set_bits(inst, g9_nine, g9_nine, value >> 9); \
1051 } \
1052 } \
1053 static inline unsigned \
1054 brw_inst_##reg##_ia1_addr_imm(const struct intel_device_info *devinfo, \
1055 const brw_inst *inst) \
1056 { \
1057 if (devinfo->ver >= 20) { \
1058 return brw_inst_bits(inst, g20_high, g20_low) << 1 | \
1059 (g20_zero == -1 ? 0 : \
1060 brw_inst_bits(inst, g20_zero, g20_zero)); \
1061 } else if (devinfo->ver >= 12) { \
1062 return brw_inst_bits(inst, g12_high, g12_low); \
1063 } else { \
1064 return brw_inst_bits(inst, g9_high, g9_low) | \
1065 (brw_inst_bits(inst, g9_nine, g9_nine) << 9); \
1066 } \
1067 }
1068
1069 /* AddrImm for Align1 Indirect Addressing */
1070 /* ----Gfx9---- -Gfx12- ---Gfx20--- */
1071 BRW_IA1_ADDR_IMM(src1, 121, 104, 96, 107, 98, 107, 98, -1)
1072 BRW_IA1_ADDR_IMM(src0, 95, 72, 64, 75, 66, 75, 66, 87)
1073 BRW_IA1_ADDR_IMM(dst, 47, 56, 48, 59, 50, 59, 50, 33)
1074
1075 #define BRW_IA16_ADDR_IMM(reg, g9_nine, g9_high, g9_low) \
1076 static inline void \
1077 brw_inst_set_##reg##_ia16_addr_imm(const struct \
1078 intel_device_info *devinfo, \
1079 brw_inst *inst, unsigned value) \
1080 { \
1081 assert(devinfo->ver < 12); \
1082 assert((value & ~0x3ff) == 0); \
1083 assert(GET_BITS(value, 3, 0) == 0); \
1084 brw_inst_set_bits(inst, g9_high, g9_low, GET_BITS(value, 8, 4)); \
1085 brw_inst_set_bits(inst, g9_nine, g9_nine, GET_BITS(value, 9, 9)); \
1086 } \
1087 static inline unsigned \
1088 brw_inst_##reg##_ia16_addr_imm(const struct intel_device_info *devinfo, \
1089 const brw_inst *inst) \
1090 { \
1091 assert(devinfo->ver < 12); \
1092 return (brw_inst_bits(inst, g9_high, g9_low) << 4) | \
1093 (brw_inst_bits(inst, g9_nine, g9_nine) << 9); \
1094 }
1095
1096 /* AddrImm[9:0] for Align16 Indirect Addressing:
1097 * Compared to Align1, these are missing the low 4 bits.
1098 * ----Gfx9----
1099 */
1100 BRW_IA16_ADDR_IMM(src1, 121, 104, 100)
1101 BRW_IA16_ADDR_IMM(src0, 95, 72, 68)
1102 BRW_IA16_ADDR_IMM(dst, 47, 56, 52)
1103 BRW_IA16_ADDR_IMM(send_src0, 78, 72, 68)
1104 BRW_IA16_ADDR_IMM(send_dst, 62, 56, 52)
1105
1106 /**
1107 * Fetch a set of contiguous bits from the instruction.
1108 *
1109 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
1110 */
1111 static inline uint64_t
1112 brw_inst_bits(const brw_inst *inst, unsigned high, unsigned low)
1113 {
1114 assume(high < 128);
1115 assume(high >= low);
1116 /* We assume the field doesn't cross 64-bit boundaries. */
1117 const unsigned word = high / 64;
1118 assert(word == low / 64);
1119
1120 high %= 64;
1121 low %= 64;
1122
1123 const uint64_t mask = (~0ull >> (64 - (high - low + 1)));
1124
1125 return (inst->data[word] >> low) & mask;
1126 }
1127
1128 /**
1129 * Set bits in the instruction, with proper shifting and masking.
1130 *
1131 * Bits indices range from 0..127; fields may not cross 64-bit boundaries.
1132 */
1133 static inline void
brw_inst_set_bits(brw_inst * inst,unsigned high,unsigned low,uint64_t value)1134 brw_inst_set_bits(brw_inst *inst, unsigned high, unsigned low, uint64_t value)
1135 {
1136 assume(high < 128);
1137 assume(high >= low);
1138 const unsigned word = high / 64;
1139 assert(word == low / 64);
1140
1141 high %= 64;
1142 low %= 64;
1143
1144 const uint64_t mask = (~0ull >> (64 - (high - low + 1))) << low;
1145
1146 /* Make sure the supplied value actually fits in the given bitfield. */
1147 assert((value & (mask >> low)) == value);
1148
1149 inst->data[word] = (inst->data[word] & ~mask) | (value << low);
1150 }
1151
1152 #undef BRW_IA16_ADDR_IMM
1153 #undef BRW_IA1_ADDR_IMM
1154 #undef MD
1155 #undef F
1156 #undef FC
1157 #undef F20
1158 #undef FD20
1159
1160 typedef struct {
1161 uint64_t data;
1162 } brw_compact_inst;
1163
1164 /**
1165 * Fetch a set of contiguous bits from the compacted instruction.
1166 *
1167 * Bits indices range from 0..63.
1168 */
1169 static inline unsigned
brw_compact_inst_bits(const brw_compact_inst * inst,unsigned high,unsigned low)1170 brw_compact_inst_bits(const brw_compact_inst *inst, unsigned high, unsigned low)
1171 {
1172 assume(high < 64);
1173 assume(high >= low);
1174 const uint64_t mask = (1ull << (high - low + 1)) - 1;
1175
1176 return (inst->data >> low) & mask;
1177 }
1178
1179 /**
1180 * Set bits in the compacted instruction.
1181 *
1182 * Bits indices range from 0..63.
1183 */
1184 static inline void
brw_compact_inst_set_bits(brw_compact_inst * inst,unsigned high,unsigned low,uint64_t value)1185 brw_compact_inst_set_bits(brw_compact_inst *inst, unsigned high, unsigned low,
1186 uint64_t value)
1187 {
1188 assume(high < 64);
1189 assume(high >= low);
1190 const uint64_t mask = ((1ull << (high - low + 1)) - 1) << low;
1191
1192 /* Make sure the supplied value actually fits in the given bitfield. */
1193 assert((value & (mask >> low)) == value);
1194
1195 inst->data = (inst->data & ~mask) | (value << low);
1196 }
1197
1198 #define FC(name, hi9, lo9, hi12, lo12, assertions) \
1199 static inline void \
1200 brw_compact_inst_set_##name(const struct \
1201 intel_device_info *devinfo, \
1202 brw_compact_inst *inst, unsigned v) \
1203 { \
1204 assert(assertions); \
1205 if (devinfo->ver >= 12) \
1206 brw_compact_inst_set_bits(inst, hi12, lo12, v); \
1207 else \
1208 brw_compact_inst_set_bits(inst, hi9, lo9, v); \
1209 } \
1210 static inline unsigned \
1211 brw_compact_inst_##name(const struct intel_device_info *devinfo, \
1212 const brw_compact_inst *inst) \
1213 { \
1214 assert(assertions); \
1215 if (devinfo->ver >= 12) \
1216 return brw_compact_inst_bits(inst, hi12, lo12); \
1217 else \
1218 return brw_compact_inst_bits(inst, hi9, lo9); \
1219 }
1220
1221 /* A simple macro for fields which stay in the same place on all generations
1222 * except for Gfx12.
1223 */
1224 #define F(name, hi9, lo9, hi12, lo12) FC(name, hi9, lo9, hi12, lo12, true)
1225
1226 /* A macro for fields which moved to several different locations
1227 * across generations.
1228 */
1229 #define F20(name, hi9, lo9, hi12, lo12, hi20, lo20) \
1230 static inline void \
1231 brw_compact_inst_set_##name(const struct \
1232 intel_device_info *devinfo, \
1233 brw_compact_inst *inst, unsigned v) \
1234 { \
1235 if (devinfo->ver >= 20) \
1236 brw_compact_inst_set_bits(inst, hi20, lo20, v); \
1237 else if (devinfo->ver >= 12) \
1238 brw_compact_inst_set_bits(inst, hi12, lo12, v); \
1239 else \
1240 brw_compact_inst_set_bits(inst, hi9, lo9, v); \
1241 } \
1242 static inline unsigned \
1243 brw_compact_inst_##name(const struct intel_device_info *devinfo, \
1244 const brw_compact_inst *inst) \
1245 { \
1246 if (devinfo->ver >= 20) \
1247 return brw_compact_inst_bits(inst, hi20, lo20); \
1248 else if (devinfo->ver >= 12) \
1249 return brw_compact_inst_bits(inst, hi12, lo12); \
1250 else \
1251 return brw_compact_inst_bits(inst, hi9, lo9); \
1252 }
1253
1254 /* A macro for fields which gained extra discontiguous bits in Gfx20
1255 * (specified by hi20ex-lo20ex).
1256 */
1257 #define FD20(name, hi9, lo9, hi12, lo12, \
1258 hi20, lo20, hi20ex, lo20ex) \
1259 static inline void \
1260 brw_compact_inst_set_##name(const struct \
1261 intel_device_info *devinfo, \
1262 brw_compact_inst *inst, unsigned v) \
1263 { \
1264 if (devinfo->ver >= 20) { \
1265 const unsigned k = hi20 - lo20 + 1; \
1266 brw_compact_inst_set_bits(inst, hi20ex, lo20ex, v >> k); \
1267 brw_compact_inst_set_bits(inst, hi20, lo20, v & ((1u << k) - 1)); \
1268 } else if (devinfo->ver >= 12) { \
1269 brw_compact_inst_set_bits(inst, hi12, lo12, v); \
1270 } else { \
1271 brw_compact_inst_set_bits(inst, hi9, lo9, v); \
1272 } \
1273 } \
1274 static inline unsigned \
1275 brw_compact_inst_##name(const struct intel_device_info *devinfo, \
1276 const brw_compact_inst *inst) \
1277 { \
1278 if (devinfo->ver >= 20) { \
1279 const unsigned k = hi20 - lo20 + 1; \
1280 return (brw_compact_inst_bits(inst, hi20ex, lo20ex) << k | \
1281 brw_compact_inst_bits(inst, hi20, lo20)); \
1282 } else if (devinfo->ver >= 12) { \
1283 return brw_compact_inst_bits(inst, hi12, lo12); \
1284 } else { \
1285 return brw_compact_inst_bits(inst, hi9, lo9); \
1286 } \
1287 }
1288
1289 F(src1_reg_nr, /* 9+ */ 63, 56, /* 12+ */ 63, 56)
1290 F(src0_reg_nr, /* 9+ */ 55, 48, /* 12+ */ 47, 40)
1291 F20(dst_reg_nr, /* 9+ */ 47, 40, /* 12+ */ 23, 16, /* 20+ */ 39, 32)
1292 F(src1_index, /* 9+ */ 39, 35, /* 12+ */ 55, 52)
1293 F20(src0_index, /* 9+ */ 34, 30, /* 12+ */ 51, 48, /* 20+ */ 25, 23)
1294 F(cmpt_control, /* 9+ */ 29, 29, /* 12+ */ 29, 29) /* Same location as brw_inst */
1295 F(cond_modifier, /* 9+ */ 27, 24, /* 12+ */ -1, -1) /* Same location as brw_inst */
1296 F(acc_wr_control, /* 9+ */ 23, 23, /* 12+ */ -1, -1)
1297 F20(subreg_index, /* 9+ */ 22, 18, /* 12+ */ 39, 35, /* 20+ */ 51, 48)
1298 FD20(datatype_index, /* 9+ */ 17, 13, /* 12+ */ 34, 30, /* 20+ */ 28, 26, 31, 30)
1299 F20(control_index, /* 9+ */ 12, 8, /* 12+ */ 28, 24, /* 20+ */ 22, 18)
1300 F20(swsb, /* 9+ */ -1, -1, /* 12+ */ 15, 8, /* 20+ */ 17, 8)
1301 F(debug_control, /* 9+ */ 7, 7, /* 12+ */ 7, 7)
1302 F(hw_opcode, /* 9+ */ 6, 0, /* 12+ */ 6, 0) /* Same location as brw_inst */
1303
1304 static inline unsigned
brw_compact_inst_imm(const struct intel_device_info * devinfo,const brw_compact_inst * inst)1305 brw_compact_inst_imm(const struct intel_device_info *devinfo,
1306 const brw_compact_inst *inst)
1307 {
1308 if (devinfo->ver >= 12) {
1309 return brw_compact_inst_bits(inst, 63, 52);
1310 } else {
1311 return (brw_compact_inst_bits(inst, 39, 35) << 8) |
1312 (brw_compact_inst_bits(inst, 63, 56));
1313 }
1314 }
1315
1316 /**
1317 * Compacted three-source instructions:
1318 * @{
1319 */
1320 F(3src_src2_reg_nr, /* 9+ */ 63, 57, /* 12+ */ 55, 48)
1321 F(3src_src1_reg_nr, /* 9+ */ 56, 50, /* 12+ */ 63, 56)
1322 F(3src_src0_reg_nr, /* 9+ */ 49, 43, /* 12+ */ 47, 40)
1323 F(3src_src2_subreg_nr, /* 9+ */ 42, 40, /* 12+ */ -1, -1)
1324 F(3src_src1_subreg_nr, /* 9+ */ 39, 37, /* 12+ */ -1, -1)
1325 F(3src_src0_subreg_nr, /* 9+ */ 36, 34, /* 12+ */ -1, -1)
1326 F(3src_src2_rep_ctrl, /* 9+ */ 33, 33, /* 12+ */ -1, -1)
1327 F(3src_src1_rep_ctrl, /* 9+ */ 32, 32, /* 12+ */ -1, -1)
1328 F(3src_saturate, /* 9+ */ 31, 31, /* 12+ */ -1, -1)
1329 F(3src_debug_control, /* 9+ */ 30, 30, /* 12+ */ 7, 7)
1330 F(3src_cmpt_control, /* 9+ */ 29, 29, /* 12+ */ 29, 29)
1331 F(3src_src0_rep_ctrl, /* 9+ */ 28, 28, /* 12+ */ -1, -1)
1332 /* Reserved */
1333 F20(3src_dst_reg_nr, /* 9+ */ 18, 12, /* 12+ */ 23, 16, /* 20+ */ 39, 32)
1334 F20(3src_source_index, /* 9+ */ 11, 10, /* 12+ */ 34, 30, /* 20+ */ 25, 22)
1335 FD20(3src_subreg_index, /* 9+ */ -1, -1, /* 12+ */ 39, 35, /* 20+ */ 28, 26, 31, 30)
1336 F20(3src_control_index, /* 9+ */ 9, 8, /* 12+ */ 28, 24, /* 20+ */ 21, 18)
1337 F20(3src_swsb, /* 9+ */ -1, -1, /* 12+ */ 15, 8, /* 20+ */ 17, 8)
1338 /* Bit 7 is Reserved (for future Opcode expansion) */
1339 F(3src_hw_opcode, /* 9+ */ 6, 0, /* 12+ */ 6, 0)
1340 /** @} */
1341
1342 #undef F
1343
1344 static inline void
brw_inst_set_opcode(const struct brw_isa_info * isa,struct brw_inst * inst,enum opcode opcode)1345 brw_inst_set_opcode(const struct brw_isa_info *isa,
1346 struct brw_inst *inst, enum opcode opcode)
1347 {
1348 brw_inst_set_hw_opcode(isa->devinfo, inst, brw_opcode_encode(isa, opcode));
1349 }
1350
1351 static inline enum opcode
brw_inst_opcode(const struct brw_isa_info * isa,const struct brw_inst * inst)1352 brw_inst_opcode(const struct brw_isa_info *isa,
1353 const struct brw_inst *inst)
1354 {
1355 return brw_opcode_decode(isa, brw_inst_hw_opcode(isa->devinfo, inst));
1356 }
1357
1358 #ifdef __cplusplus
1359 }
1360 #endif
1361
1362 #endif
1363