1 /* 2 * Copyright © 2017 Advanced Micro Devices, Inc. 3 * 4 * SPDX-License-Identifier: MIT 5 */ 6 7 #ifndef AC_SURFACE_H 8 #define AC_SURFACE_H 9 10 #include "amd_family.h" 11 #include "util/format/u_format.h" 12 13 /* NIR is optional. Some components don't want to include NIR with ac_surface.h. */ 14 #ifdef AC_SURFACE_INCLUDE_NIR 15 #include "compiler/nir/nir_builder.h" 16 #endif 17 18 #include <stdbool.h> 19 #include <stdint.h> 20 #include <stdio.h> 21 22 #ifdef __cplusplus 23 extern "C" { 24 #endif 25 26 /* Forward declarations. */ 27 struct ac_addrlib; 28 29 struct amdgpu_gpu_info; 30 struct radeon_info; 31 32 #define RADEON_SURF_MAX_LEVELS 15 33 34 enum radeon_surf_mode 35 { 36 RADEON_SURF_MODE_LINEAR_ALIGNED = 1, 37 RADEON_SURF_MODE_1D = 2, 38 RADEON_SURF_MODE_2D = 3, 39 }; 40 41 /* This describes D/S/Z/R swizzle modes. 42 * Defined in the GB_TILE_MODEn.MICRO_TILE_MODE_NEW order. 43 */ 44 enum radeon_micro_mode 45 { 46 RADEON_MICRO_MODE_DISPLAY = 0, 47 RADEON_MICRO_MODE_STANDARD = 1, 48 RADEON_MICRO_MODE_DEPTH = 2, 49 RADEON_MICRO_MODE_RENDER = 3, /* gfx9 and older: rotated */ 50 }; 51 52 /* the first 16 bits are reserved for libdrm_radeon, don't use them */ 53 #define RADEON_SURF_SCANOUT (1 << 16) 54 #define RADEON_SURF_ZBUFFER (1 << 17) 55 #define RADEON_SURF_SBUFFER (1 << 18) 56 #define RADEON_SURF_Z_OR_SBUFFER (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER) 57 /* bits 19 and 20 are reserved for libdrm_radeon, don't use them */ 58 #define RADEON_SURF_FMASK (1 << 21) 59 #define RADEON_SURF_DISABLE_DCC (1ull << 22) 60 #define RADEON_SURF_TC_COMPATIBLE_HTILE (1ull << 23) 61 #define RADEON_SURF_IMPORTED (1ull << 24) 62 #define RADEON_SURF_CONTIGUOUS_DCC_LAYERS (1ull << 25) 63 #define RADEON_SURF_SHAREABLE (1ull << 26) 64 #define RADEON_SURF_NO_RENDER_TARGET (1ull << 27) 65 /* Force a swizzle mode (gfx9+) or tile mode (gfx6-8). 66 * If this is not set, optimize for space. */ 67 #define RADEON_SURF_FORCE_SWIZZLE_MODE (1ull << 28) 68 #define RADEON_SURF_NO_FMASK (1ull << 29) 69 #define RADEON_SURF_NO_HTILE (1ull << 30) 70 #define RADEON_SURF_FORCE_MICRO_TILE_MODE (1ull << 31) 71 #define RADEON_SURF_PRT (1ull << 32) 72 #define RADEON_SURF_VRS_RATE (1ull << 33) 73 /* Block compressed + linear format is not supported in addrlib. These surface can be 74 * used as transfer resource. This flag indicates not to set flags.texture flag for 75 * color surface in gfx9_compute_surface(). */ 76 #define RADEON_SURF_NO_TEXTURE (1ull << 34) 77 #define RADEON_SURF_NO_STENCIL_ADJUST (1ull << 35) 78 79 struct legacy_surf_level { 80 uint32_t offset_256B; /* divided by 256, the hw can only do 40-bit addresses */ 81 uint32_t slice_size_dw; /* in dwords; max = 4GB / 4. */ 82 unsigned nblk_x : 15; 83 unsigned nblk_y : 15; 84 enum radeon_surf_mode mode : 2; 85 }; 86 87 struct legacy_surf_dcc_level { 88 uint32_t dcc_offset; /* relative offset within DCC mip tree */ 89 uint32_t dcc_fast_clear_size; 90 uint32_t dcc_slice_fast_clear_size; 91 }; 92 93 struct legacy_surf_fmask { 94 unsigned slice_tile_max; /* max 4M */ 95 uint8_t tiling_index; /* max 31 */ 96 uint8_t bankh; /* max 8 */ 97 uint16_t pitch_in_pixels; 98 }; 99 100 struct legacy_surf_layout { 101 unsigned bankw : 4; /* max 8 */ 102 unsigned bankh : 4; /* max 8 */ 103 unsigned mtilea : 4; /* max 8 */ 104 unsigned tile_split : 13; /* max 4K */ 105 unsigned stencil_tile_split : 13; /* max 4K */ 106 unsigned pipe_config : 5; /* max 17 */ 107 unsigned num_banks : 5; /* max 16 */ 108 unsigned macro_tile_index : 4; /* max 15 */ 109 110 /* Whether the depth miptree or stencil miptree as used by the DB are 111 * adjusted from their TC compatible form to ensure depth/stencil 112 * compatibility. If either is true, the corresponding plane cannot be 113 * sampled from. 114 */ 115 unsigned depth_adjusted : 1; 116 unsigned stencil_adjusted : 1; 117 118 struct legacy_surf_level level[RADEON_SURF_MAX_LEVELS]; 119 uint8_t tiling_index[RADEON_SURF_MAX_LEVELS]; 120 121 union { 122 /* Color layout */ 123 struct { 124 struct legacy_surf_dcc_level dcc_level[RADEON_SURF_MAX_LEVELS]; 125 struct legacy_surf_fmask fmask; 126 unsigned cmask_slice_tile_max; 127 } color; 128 129 /* Z/S layout */ 130 struct { 131 struct legacy_surf_level stencil_level[RADEON_SURF_MAX_LEVELS]; 132 uint8_t stencil_tiling_index[RADEON_SURF_MAX_LEVELS]; 133 } zs; 134 }; 135 }; 136 137 /* Same as addrlib - AddrResourceType. */ 138 enum gfx9_resource_type 139 { 140 RADEON_RESOURCE_1D = 0, 141 RADEON_RESOURCE_2D, 142 RADEON_RESOURCE_3D, 143 }; 144 145 struct gfx9_surf_meta_flags { 146 uint8_t rb_aligned : 1; /* optimal for RBs */ 147 uint8_t pipe_aligned : 1; /* optimal for TC */ 148 uint8_t independent_64B_blocks : 1; 149 uint8_t independent_128B_blocks : 1; 150 uint8_t max_compressed_block_size : 2; 151 uint8_t display_equation_valid : 1; 152 }; 153 154 struct gfx9_surf_meta_level { 155 unsigned offset; 156 unsigned size; /* the size of one level in one layer (the image is an array of layers 157 * where each layer has an array of levels) */ 158 }; 159 160 /** 161 * Meta address equation. 162 * 163 * DCC/HTILE address equation for doing DCC/HTILE address computations in shaders. 164 * 165 * ac_surface_meta_address_test.c contains the reference implementation. 166 * ac_nir_{dcc,htile}_addr_from_coord is the NIR implementation. 167 * 168 * For DCC: 169 * The gfx9 equation doesn't support mipmapping. 170 * The gfx10 equation doesn't support mipmapping and MSAA. 171 * (those are also limitations of Addr2ComputeDccAddrFromCoord) 172 * 173 * For HTILE: 174 * The gfx9 equation isn't implemented. 175 * The gfx10 equation doesn't support mipmapping. 176 */ 177 struct gfx9_meta_equation { 178 uint16_t meta_block_width; 179 uint16_t meta_block_height; 180 uint16_t meta_block_depth; 181 182 union { 183 /* The gfx9 DCC equation is chip-specific, and it varies with: 184 * - resource type 185 * - swizzle_mode 186 * - bpp 187 * - number of samples 188 * - number of fragments 189 * - pipe_aligned 190 * - rb_aligned 191 */ 192 struct { 193 uint8_t num_bits; 194 uint8_t num_pipe_bits; 195 196 struct { 197 struct { 198 uint8_t dim:3; /* 0..4 */ 199 uint8_t ord:5; /* 0..31 */ 200 } coord[5]; /* 0..num_coords-1 */ 201 } bit[20]; /* 0..num_bits-1 */ 202 } gfx9; 203 204 /* The gfx10 DCC equation is chip-specific, it requires 64KB_R_X, and it varies with: 205 * - bpp 206 * - number of samples 207 * - number of fragments 208 * - pipe_aligned 209 * 210 * The gfx10 HTILE equation is chip-specific, it requires 64KB_Z_X, and it varies with: 211 * - number of samples 212 */ 213 uint16_t gfx10_bits[64]; 214 } u; 215 }; 216 217 struct gfx9_surf_layout { 218 uint16_t epitch; /* gfx9 only, not on gfx10 */ 219 uint8_t swizzle_mode; /* color or depth */ 220 bool uses_custom_pitch; /* only used by gfx10.3+ */ 221 222 enum gfx9_resource_type resource_type:8; /* 1D, 2D or 3D */ 223 uint16_t surf_pitch; /* in blocks */ 224 uint16_t surf_height; 225 226 uint64_t surf_offset; /* 0 unless imported with an offset */ 227 /* The size of the 2D plane containing all mipmap levels. */ 228 uint64_t surf_slice_size; 229 /* Mipmap level offset within the slice in bytes. Only valid for LINEAR. */ 230 uint64_t offset[RADEON_SURF_MAX_LEVELS]; /* up to 16K * 16K * 16 * ~1.33 */ 231 /* Mipmap level pitch in elements. Only valid for LINEAR. */ 232 uint16_t pitch[RADEON_SURF_MAX_LEVELS]; 233 234 uint16_t base_mip_width; 235 uint16_t base_mip_height; 236 237 /* Pitch of level in blocks, only valid for prt images. */ 238 uint16_t prt_level_pitch[RADEON_SURF_MAX_LEVELS]; 239 /* Offset within slice in bytes, only valid for prt images. */ 240 uint64_t prt_level_offset[RADEON_SURF_MAX_LEVELS]; /* up to 64K * 64K * 16 * ~1.33 */ 241 242 /* DCC or HTILE level info */ 243 struct gfx9_surf_meta_level meta_levels[RADEON_SURF_MAX_LEVELS]; 244 245 union { 246 /* Color */ 247 struct { 248 struct gfx9_surf_meta_flags dcc; /* metadata of color */ 249 uint8_t fmask_swizzle_mode; 250 uint16_t fmask_epitch; /* gfx9 only, not on gfx10 */ 251 252 uint16_t dcc_pitch_max; 253 uint16_t dcc_height; 254 255 uint8_t dcc_block_width; 256 uint8_t dcc_block_height; 257 uint8_t dcc_block_depth; 258 259 /* Displayable DCC. This is always rb_aligned=0 and pipe_aligned=0. 260 * The 3D engine doesn't support that layout except for chips with 1 RB. 261 * All other chips must set rb_aligned=1. 262 * A compute shader needs to convert from aligned DCC to unaligned. 263 */ 264 uint8_t display_dcc_alignment_log2; 265 uint32_t display_dcc_size; 266 uint16_t display_dcc_pitch_max; /* (mip chain pitch - 1) */ 267 uint16_t display_dcc_height; 268 bool dcc_retile_use_uint16; /* if all values fit into uint16_t */ 269 uint32_t dcc_retile_num_elements; 270 void *dcc_retile_map; 271 272 /* CMASK level info (only level 0) */ 273 struct gfx9_surf_meta_level cmask_level0; 274 275 /* For DCC retiling. */ 276 struct gfx9_meta_equation dcc_equation; /* 2D only */ 277 struct gfx9_meta_equation display_dcc_equation; 278 279 /* For FCE compute. */ 280 struct gfx9_meta_equation cmask_equation; /* 2D only */ 281 } color; 282 283 /* Z/S */ 284 struct { 285 uint64_t stencil_offset; /* separate stencil */ 286 uint16_t stencil_epitch; /* gfx9 only, not on gfx10 */ 287 uint8_t stencil_swizzle_mode; 288 289 /* For HTILE VRS. */ 290 struct gfx9_meta_equation htile_equation; 291 } zs; 292 }; 293 }; 294 295 struct radeon_surf { 296 /* Format properties. */ 297 uint8_t blk_w : 4; 298 uint8_t blk_h : 4; 299 uint8_t bpe : 5; 300 /* Display, standard(thin), depth, render(rotated). AKA D,S,Z,R swizzle modes. */ 301 uint8_t micro_tile_mode : 3; 302 /* Number of mipmap levels where DCC or HTILE is enabled starting from level 0. 303 * Non-zero levels may be disabled due to alignment constraints, but not 304 * the first level. 305 */ 306 uint8_t num_meta_levels : 4; 307 uint8_t is_linear : 1; 308 uint8_t has_stencil : 1; 309 /* This might be true even if micro_tile_mode isn't displayable or rotated. */ 310 uint8_t is_displayable : 1; 311 uint8_t first_mip_tail_level : 4; 312 313 /* These are return values. Some of them can be set by the caller, but 314 * they will be treated as hints (e.g. bankw, bankh) and might be 315 * changed by the calculator. 316 */ 317 318 /* Not supported yet for depth + stencil. */ 319 uint16_t prt_tile_width; /* up to 256 roughly (for 64KB tiles) */ 320 uint16_t prt_tile_height; /* up to 256 roughly (for 64KB tiles) */ 321 uint16_t prt_tile_depth; /* up to 32 roughly (for 64KB thick tiles) */ 322 323 /* Tile swizzle can be OR'd with low bits of the BASE_256B address. 324 * The value is the same for all mipmap levels. Supported tile modes: 325 * - GFX6: Only macro tiling. 326 * - GFX9: Only *_X and *_T swizzle modes. Level 0 must not be in the mip 327 * tail. 328 * 329 * Only these surfaces are allowed to set it: 330 * - color (if it doesn't have to be displayable) 331 * - DCC (same tile swizzle as color) 332 * - FMASK 333 * - CMASK if it's TC-compatible or if the gen is GFX9 334 * - depth/stencil if HTILE is not TC-compatible and if the gen is not GFX9 335 */ 336 uint16_t tile_swizzle; /* it has 16 bits because gfx11 shifts it by 2 bits */ 337 uint8_t fmask_tile_swizzle; 338 339 /* Use (1 << log2) to compute the alignment. */ 340 uint8_t surf_alignment_log2; 341 uint8_t fmask_alignment_log2; 342 uint8_t meta_alignment_log2; /* DCC or HTILE */ 343 uint8_t cmask_alignment_log2; 344 uint8_t alignment_log2; 345 346 /* DRM format modifier. Set to DRM_FORMAT_MOD_INVALID to have addrlib 347 * select tiling parameters instead. 348 */ 349 uint64_t modifier; 350 uint64_t flags; 351 352 uint64_t surf_size; 353 uint64_t fmask_size; 354 uint32_t fmask_slice_size; /* max 2^31 (16K * 16K * 8) */ 355 356 /* DCC and HTILE (they are very small) */ 357 uint32_t meta_size; 358 uint32_t meta_slice_size; 359 uint32_t meta_pitch; 360 361 uint32_t cmask_size; 362 uint32_t cmask_slice_size; 363 uint16_t cmask_pitch; /* GFX9+ */ 364 uint16_t cmask_height; /* GFX9+ */ 365 366 /* All buffers combined. */ 367 uint64_t meta_offset; /* DCC or HTILE */ 368 uint64_t fmask_offset; 369 uint64_t cmask_offset; 370 uint64_t display_dcc_offset; 371 uint64_t total_size; 372 373 union { 374 /* Return values for GFX8 and older. 375 * 376 * Some of them can be set by the caller if certain parameters are 377 * desirable. The allocator will try to obey them. 378 */ 379 struct legacy_surf_layout legacy; 380 381 /* GFX9+ return values. */ 382 struct gfx9_surf_layout gfx9; 383 } u; 384 }; 385 386 struct ac_surf_info { 387 uint32_t width; 388 uint32_t height; 389 uint32_t depth; 390 uint8_t samples; /* For Z/S: samples; For color: FMASK coverage samples */ 391 uint8_t storage_samples; /* For color: allocated samples */ 392 uint8_t levels; 393 uint8_t num_channels; /* heuristic for displayability */ 394 uint16_t array_size; 395 uint32_t *surf_index; /* Set a monotonic counter for tile swizzling. */ 396 uint32_t *fmask_surf_index; 397 }; 398 399 struct ac_surf_config { 400 struct ac_surf_info info; 401 unsigned is_1d : 1; 402 unsigned is_3d : 1; 403 unsigned is_cube : 1; 404 unsigned is_array : 1; 405 }; 406 407 /* Output parameters for ac_surface_compute_nbc_view */ 408 struct ac_surf_nbc_view { 409 bool valid; 410 uint32_t width; 411 uint32_t height; 412 uint32_t level; 413 uint32_t num_levels; /* Used for max_mip in the resource descriptor */ 414 uint8_t tile_swizzle; 415 uint64_t base_address_offset; 416 }; 417 418 struct ac_addrlib *ac_addrlib_create(const struct radeon_info *info, uint64_t *max_alignment); 419 void ac_addrlib_destroy(struct ac_addrlib *addrlib); 420 void *ac_addrlib_get_handle(struct ac_addrlib *addrlib); 421 422 int ac_compute_surface(struct ac_addrlib *addrlib, const struct radeon_info *info, 423 const struct ac_surf_config *config, enum radeon_surf_mode mode, 424 struct radeon_surf *surf); 425 void ac_surface_zero_dcc_fields(struct radeon_surf *surf); 426 unsigned ac_pipe_config_to_num_pipes(unsigned pipe_config); 427 428 void ac_surface_apply_bo_metadata(const struct radeon_info *info, struct radeon_surf *surf, 429 uint64_t tiling_flags, enum radeon_surf_mode *mode); 430 void ac_surface_compute_bo_metadata(const struct radeon_info *info, struct radeon_surf *surf, 431 uint64_t *tiling_flags); 432 433 bool ac_surface_apply_umd_metadata(const struct radeon_info *info, struct radeon_surf *surf, 434 unsigned num_storage_samples, unsigned num_mipmap_levels, 435 unsigned size_metadata, const uint32_t metadata[64]); 436 void ac_surface_compute_umd_metadata(const struct radeon_info *info, struct radeon_surf *surf, 437 unsigned num_mipmap_levels, uint32_t desc[8], 438 unsigned *size_metadata, uint32_t metadata[64], 439 bool include_tool_md); 440 441 bool ac_surface_override_offset_stride(const struct radeon_info *info, struct radeon_surf *surf, 442 unsigned num_layers, unsigned num_mipmap_levels, 443 uint64_t offset, unsigned pitch); 444 445 struct ac_modifier_options { 446 bool dcc; /* Whether to allow DCC. */ 447 bool dcc_retile; /* Whether to allow use of a DCC retile map. */ 448 }; 449 450 bool ac_is_modifier_supported(const struct radeon_info *info, 451 const struct ac_modifier_options *options, 452 enum pipe_format format, 453 uint64_t modifier); 454 bool ac_get_supported_modifiers(const struct radeon_info *info, 455 const struct ac_modifier_options *options, 456 enum pipe_format format, 457 unsigned *mod_count, 458 uint64_t *mods); 459 bool ac_modifier_has_dcc(uint64_t modifier); 460 bool ac_modifier_has_dcc_retile(uint64_t modifier); 461 bool ac_modifier_supports_dcc_image_stores(enum amd_gfx_level gfx_level, uint64_t modifier); 462 void ac_modifier_max_extent(const struct radeon_info *info, 463 uint64_t modifier, uint32_t *width, uint32_t *height); 464 465 unsigned ac_surface_get_nplanes(const struct radeon_surf *surf); 466 uint64_t ac_surface_get_plane_offset(enum amd_gfx_level gfx_level, 467 const struct radeon_surf *surf, 468 unsigned plane, unsigned layer); 469 uint64_t ac_surface_get_plane_stride(enum amd_gfx_level gfx_level, 470 const struct radeon_surf *surf, 471 unsigned plane, unsigned level); 472 /* Of the whole miplevel, not an individual layer */ 473 uint64_t ac_surface_get_plane_size(const struct radeon_surf *surf, 474 unsigned plane); 475 476 uint64_t ac_surface_addr_from_coord(struct ac_addrlib *addrlib, const struct radeon_info *info, 477 const struct radeon_surf *surf, 478 const struct ac_surf_info *surf_info, unsigned level, 479 unsigned x, unsigned y, unsigned layer, bool is_3d); 480 void ac_surface_compute_nbc_view(struct ac_addrlib *addrlib, const struct radeon_info *info, 481 const struct radeon_surf *surf, 482 const struct ac_surf_info *surf_info, unsigned level, 483 unsigned layer, struct ac_surf_nbc_view *out); 484 485 void ac_surface_print_info(FILE *out, const struct radeon_info *info, 486 const struct radeon_surf *surf); 487 488 bool ac_surface_supports_dcc_image_stores(enum amd_gfx_level gfx_level, 489 const struct radeon_surf *surf); 490 unsigned ac_get_cb_number_type(enum pipe_format format); 491 unsigned ac_get_cb_format(enum amd_gfx_level gfx_level, enum pipe_format format); 492 493 #ifdef AC_SURFACE_INCLUDE_NIR 494 nir_def *ac_nir_dcc_addr_from_coord(nir_builder *b, const struct radeon_info *info, 495 unsigned bpe, struct gfx9_meta_equation *equation, 496 nir_def *dcc_pitch, nir_def *dcc_height, 497 nir_def *dcc_slice_size, 498 nir_def *x, nir_def *y, nir_def *z, 499 nir_def *sample, nir_def *pipe_xor); 500 501 nir_def *ac_nir_cmask_addr_from_coord(nir_builder *b, const struct radeon_info *info, 502 struct gfx9_meta_equation *equation, 503 nir_def *cmask_pitch, nir_def *cmask_height, 504 nir_def *cmask_slice_size, 505 nir_def *x, nir_def *y, nir_def *z, 506 nir_def *pipe_xor, 507 nir_def **bit_position); 508 509 nir_def *ac_nir_htile_addr_from_coord(nir_builder *b, const struct radeon_info *info, 510 struct gfx9_meta_equation *equation, 511 nir_def *htile_pitch, 512 nir_def *htile_slice_size, 513 nir_def *x, nir_def *y, nir_def *z, 514 nir_def *pipe_xor); 515 #endif 516 517 #ifdef __cplusplus 518 } 519 #endif 520 521 #endif /* AC_SURFACE_H */ 522