1 /* 2 ************************************************************************************************************************ 3 * 4 * Copyright (C) 2017-2022 Advanced Micro Devices, Inc. All rights reserved. 5 * SPDX-License-Identifier: MIT 6 * 7 ***********************************************************************************************************************/ 8 9 #ifndef _AMDGPU_ASIC_ADDR_H 10 #define _AMDGPU_ASIC_ADDR_H 11 12 #define ATI_VENDOR_ID 0x1002 13 #define AMD_VENDOR_ID 0x1022 14 15 // AMDGPU_VENDOR_IS_AMD(vendorId) 16 #define AMDGPU_VENDOR_IS_AMD(v) ((v == ATI_VENDOR_ID) || (v == AMD_VENDOR_ID)) 17 18 #define FAMILY_UNKNOWN 0x00 19 #define FAMILY_TN 0x69 //# 105 / Trinity APUs 20 #define FAMILY_SI 0x6E //# 110 / Southern Islands: Tahiti, Pitcairn, CapeVerde, Oland, Hainan 21 #define FAMILY_CI 0x78 //# 120 / Sea Islands: Bonaire, Hawaii 22 #define FAMILY_KV 0x7D //# 125 / Kaveri APUs: Spectre, Spooky, Kalindi, Godavari 23 #define FAMILY_VI 0x82 //# 130 / Volcanic Islands: Iceland, Tonga, Fiji 24 #define FAMILY_POLARIS 0x82 //# 130 / Polaris: 10, 11, 12 25 #define FAMILY_CZ 0x87 //# 135 / Carrizo APUs: Carrizo, Stoney 26 #define FAMILY_AI 0x8D //# 141 / Vega: 10, 20 27 #define FAMILY_RV 0x8E //# 142 / Raven 28 #define FAMILY_NV 0x8F //# 143 / Navi: 10 29 #define FAMILY_VGH 0x90 //# 144 / Van Gogh 30 #define FAMILY_NV3 0x91 //# 145 / Navi: 3x 31 #define FAMILY_GFX1103 0x94 32 #define FAMILY_GFX1150 0x96 33 #define FAMILY_RMB 0x92 //# 146 / Rembrandt 34 #define FAMILY_RPL 0x95 //# 149 / Raphael 35 #define FAMILY_MDN 0x97 //# 151 / Mendocino 36 37 // AMDGPU_FAMILY_IS(familyId, familyName) 38 #define FAMILY_IS(f, fn) (f == FAMILY_##fn) 39 #define FAMILY_IS_TN(f) FAMILY_IS(f, TN) 40 #define FAMILY_IS_SI(f) FAMILY_IS(f, SI) 41 #define FAMILY_IS_CI(f) FAMILY_IS(f, CI) 42 #define FAMILY_IS_KV(f) FAMILY_IS(f, KV) 43 #define FAMILY_IS_VI(f) FAMILY_IS(f, VI) 44 #define FAMILY_IS_POLARIS(f) FAMILY_IS(f, POLARIS) 45 #define FAMILY_IS_CZ(f) FAMILY_IS(f, CZ) 46 #define FAMILY_IS_AI(f) FAMILY_IS(f, AI) 47 #define FAMILY_IS_RV(f) FAMILY_IS(f, RV) 48 #define FAMILY_IS_NV(f) FAMILY_IS(f, NV) 49 #define FAMILY_IS_NV3(f) FAMILY_IS(f, NV3) 50 #define FAMILY_IS_RMB(f) FAMILY_IS(f, RMB) 51 52 #define AMDGPU_UNKNOWN 0xFF 53 54 #define AMDGPU_TAHITI_RANGE 0x05, 0x14 //# 5 <= x < 20 55 #define AMDGPU_PITCAIRN_RANGE 0x15, 0x28 //# 21 <= x < 40 56 #define AMDGPU_CAPEVERDE_RANGE 0x29, 0x3C //# 41 <= x < 60 57 #define AMDGPU_OLAND_RANGE 0x3C, 0x46 //# 60 <= x < 70 58 #define AMDGPU_HAINAN_RANGE 0x46, 0xFF //# 70 <= x < max 59 60 #define AMDGPU_BONAIRE_RANGE 0x14, 0x28 //# 20 <= x < 40 61 #define AMDGPU_HAWAII_RANGE 0x28, 0x3C //# 40 <= x < 60 62 63 #define AMDGPU_SPECTRE_RANGE 0x01, 0x41 //# 1 <= x < 65 64 #define AMDGPU_SPOOKY_RANGE 0x41, 0x81 //# 65 <= x < 129 65 #define AMDGPU_KALINDI_RANGE 0x81, 0xA1 //# 129 <= x < 161 66 #define AMDGPU_GODAVARI_RANGE 0xA1, 0xFF //# 161 <= x < max 67 68 #define AMDGPU_ICELAND_RANGE 0x01, 0x14 //# 1 <= x < 20 69 #define AMDGPU_TONGA_RANGE 0x14, 0x28 //# 20 <= x < 40 70 #define AMDGPU_FIJI_RANGE 0x3C, 0x50 //# 60 <= x < 80 71 72 #define AMDGPU_POLARIS10_RANGE 0x50, 0x5A //# 80 <= x < 90 73 #define AMDGPU_POLARIS11_RANGE 0x5A, 0x64 //# 90 <= x < 100 74 #define AMDGPU_POLARIS12_RANGE 0x64, 0x6E //# 100 <= x < 110 75 #define AMDGPU_VEGAM_RANGE 0x6E, 0xFF //# 110 <= x < max 76 77 #define AMDGPU_CARRIZO_RANGE 0x01, 0x21 //# 1 <= x < 33 78 #define AMDGPU_BRISTOL_RANGE 0x10, 0x21 //# 16 <= x < 33 79 #define AMDGPU_STONEY_RANGE 0x61, 0xFF //# 97 <= x < max 80 81 #define AMDGPU_VEGA10_RANGE 0x01, 0x14 //# 1 <= x < 20 82 #define AMDGPU_VEGA12_RANGE 0x14, 0x28 //# 20 <= x < 40 83 #define AMDGPU_VEGA20_RANGE 0x28, 0xFF //# 40 <= x < max 84 85 #define AMDGPU_RAVEN_RANGE 0x01, 0x81 //# 1 <= x < 129 86 #define AMDGPU_RAVEN2_RANGE 0x81, 0x90 //# 129 <= x < 144 87 #define AMDGPU_RENOIR_RANGE 0x91, 0xFF //# 145 <= x < max 88 89 #define AMDGPU_NAVI10_RANGE 0x01, 0x0A //# 1 <= x < 10 90 #define AMDGPU_NAVI12_RANGE 0x0A, 0x14 //# 10 <= x < 20 91 #define AMDGPU_NAVI14_RANGE 0x14, 0x28 //# 20 <= x < 40 92 #define AMDGPU_NAVI21_RANGE 0x28, 0x32 //# 40 <= x < 50 93 #define AMDGPU_NAVI22_RANGE 0x32, 0x3C //# 50 <= x < 60 94 #define AMDGPU_NAVI23_RANGE 0x3C, 0x46 //# 60 <= x < 70 95 #define AMDGPU_NAVI24_RANGE 0x46, 0x50 //# 70 <= x < 80 96 97 #define AMDGPU_VANGOGH_RANGE 0x01, 0xFF //# 1 <= x < max 98 99 #define AMDGPU_NAVI31_RANGE 0x01, 0x10 //# 01 <= x < 16 100 #define AMDGPU_NAVI32_RANGE 0x20, 0xFF //# 32 <= x < 255 101 #define AMDGPU_NAVI33_RANGE 0x10, 0x20 //# 16 <= x < 32 102 #define AMDGPU_GFX1103_R1_RANGE 0x01, 0x80 //# 1 <= x < 128 103 #define AMDGPU_GFX1103_R2_RANGE 0x80, 0xFF //# 128 <= x < max 104 105 #define AMDGPU_GFX1150_RANGE 0x01, 0xFF //# 1 <= x < max 106 107 #define AMDGPU_REMBRANDT_RANGE 0x01, 0xFF //# 01 <= x < 255 108 109 #define AMDGPU_RAPHAEL_RANGE 0x01, 0xFF //# 1 <= x < max 110 111 #define AMDGPU_MENDOCINO_RANGE 0x01, 0xFF //# 1 <= x < max 112 113 #define AMDGPU_EXPAND_FIX(x) x 114 #define AMDGPU_RANGE_HELPER(val, min, max) ((val >= min) && (val < max)) 115 #define AMDGPU_IN_RANGE(val, ...) AMDGPU_EXPAND_FIX(AMDGPU_RANGE_HELPER(val, __VA_ARGS__)) 116 117 118 // ASICREV_IS(eRevisionId, revisionName) 119 #define ASICREV_IS(r, rn) AMDGPU_IN_RANGE(r, AMDGPU_##rn##_RANGE) 120 #define ASICREV_IS_TAHITI_P(r) ASICREV_IS(r, TAHITI) 121 #define ASICREV_IS_PITCAIRN_PM(r) ASICREV_IS(r, PITCAIRN) 122 #define ASICREV_IS_CAPEVERDE_M(r) ASICREV_IS(r, CAPEVERDE) 123 #define ASICREV_IS_OLAND_M(r) ASICREV_IS(r, OLAND) 124 #define ASICREV_IS_HAINAN_V(r) ASICREV_IS(r, HAINAN) 125 126 #define ASICREV_IS_BONAIRE_M(r) ASICREV_IS(r, BONAIRE) 127 #define ASICREV_IS_HAWAII_P(r) ASICREV_IS(r, HAWAII) 128 129 #define ASICREV_IS_SPECTRE(r) ASICREV_IS(r, SPECTRE) 130 #define ASICREV_IS_SPOOKY(r) ASICREV_IS(r, SPOOKY) 131 #define ASICREV_IS_KALINDI(r) ASICREV_IS(r, KALINDI) 132 #define ASICREV_IS_KALINDI_GODAVARI(r) ASICREV_IS(r, GODAVARI) 133 134 #define ASICREV_IS_ICELAND_M(r) ASICREV_IS(r, ICELAND) 135 #define ASICREV_IS_TONGA_P(r) ASICREV_IS(r, TONGA) 136 #define ASICREV_IS_FIJI_P(r) ASICREV_IS(r, FIJI) 137 138 #define ASICREV_IS_POLARIS10_P(r) ASICREV_IS(r, POLARIS10) 139 #define ASICREV_IS_POLARIS11_M(r) ASICREV_IS(r, POLARIS11) 140 #define ASICREV_IS_POLARIS12_V(r) ASICREV_IS(r, POLARIS12) 141 #define ASICREV_IS_VEGAM_P(r) ASICREV_IS(r, VEGAM) 142 143 #define ASICREV_IS_CARRIZO(r) ASICREV_IS(r, CARRIZO) 144 #define ASICREV_IS_CARRIZO_BRISTOL(r) ASICREV_IS(r, BRISTOL) 145 #define ASICREV_IS_STONEY(r) ASICREV_IS(r, STONEY) 146 147 #define ASICREV_IS_VEGA10_M(r) ASICREV_IS(r, VEGA10) 148 #define ASICREV_IS_VEGA10_P(r) ASICREV_IS(r, VEGA10) 149 #define ASICREV_IS_VEGA12_P(r) ASICREV_IS(r, VEGA12) 150 #define ASICREV_IS_VEGA12_p(r) ASICREV_IS(r, VEGA12) 151 #define ASICREV_IS_VEGA20_P(r) ASICREV_IS(r, VEGA20) 152 153 #define ASICREV_IS_RAVEN(r) ASICREV_IS(r, RAVEN) 154 #define ASICREV_IS_RAVEN2(r) ASICREV_IS(r, RAVEN2) 155 #define ASICREV_IS_RENOIR(r) ASICREV_IS(r, RENOIR) 156 157 #define ASICREV_IS_NAVI10_P(r) ASICREV_IS(r, NAVI10) 158 159 #define ASICREV_IS_NAVI12_P(r) ASICREV_IS(r, NAVI12) 160 161 #define ASICREV_IS_NAVI14_M(r) ASICREV_IS(r, NAVI14) 162 163 #define ASICREV_IS_NAVI21_M(r) ASICREV_IS(r, NAVI21) 164 165 #define ASICREV_IS_NAVI22_P(r) ASICREV_IS(r, NAVI22) 166 167 #define ASICREV_IS_NAVI23_P(r) ASICREV_IS(r, NAVI23) 168 169 #define ASICREV_IS_NAVI24_P(r) ASICREV_IS(r, NAVI24) 170 171 #define ASICREV_IS_VANGOGH(r) ASICREV_IS(r, VANGOGH) 172 173 #define ASICREV_IS_NAVI31_P(r) ASICREV_IS(r, NAVI31) 174 #define ASICREV_IS_NAVI32_P(r) ASICREV_IS(r, NAVI32) 175 #define ASICREV_IS_NAVI33_P(r) ASICREV_IS(r, NAVI33) 176 #define ASICREV_IS_GFX1103_R1(r) ASICREV_IS(r, GFX1103_R1) 177 #define ASICREV_IS_GFX1103_R2(r) ASICREV_IS(r, GFX1103_R2) 178 #define ASICREV_IS_GFX1150(r) ASICREV_IS(r, GFX1150) 179 180 #define ASICREV_IS_REMBRANDT(r) ASICREV_IS(r, REMBRANDT) 181 182 #define ASICREV_IS_RAPHAEL(r) ASICREV_IS(r, RAPHAEL) 183 184 #define ASICREV_IS_MENDOCINO(r) ASICREV_IS(r, MENDOCINO) 185 186 #endif // _AMDGPU_ASIC_ADDR_H 187