1 /* 2 ************************************************************************************************************************ 3 * 4 * Copyright (C) 2007-2022 Advanced Micro Devices, Inc. All rights reserved. 5 * SPDX-License-Identifier: MIT 6 * 7 ***********************************************************************************************************************/ 8 9 /** 10 **************************************************************************************************** 11 * @file addrinterface.h 12 * @brief Contains the addrlib interfaces declaration and parameter defines 13 **************************************************************************************************** 14 */ 15 #ifndef __ADDR_INTERFACE_H__ 16 #define __ADDR_INTERFACE_H__ 17 18 // Includes should be before extern "C" 19 #include "addrtypes.h" 20 21 #if defined(__cplusplus) 22 extern "C" 23 { 24 #endif 25 26 #define ADDRLIB_VERSION_MAJOR 8 27 #define ADDRLIB_VERSION_MINOR 9 28 #define ADDRLIB_VERSION ((ADDRLIB_VERSION_MAJOR << 16) | ADDRLIB_VERSION_MINOR) 29 30 /// Virtually all interface functions need ADDR_HANDLE as first parameter 31 typedef VOID* ADDR_HANDLE; 32 33 /// Client handle used in callbacks 34 typedef VOID* ADDR_CLIENT_HANDLE; 35 36 /** 37 * ///////////////////////////////////////////////////////////////////////////////////////////////// 38 * // Callback functions 39 * ///////////////////////////////////////////////////////////////////////////////////////////////// 40 * typedef VOID* (ADDR_API* ADDR_ALLOCSYSMEM)( 41 * const ADDR_ALLOCSYSMEM_INPUT* pInput); 42 * typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_FREESYSMEM)( 43 * VOID* pVirtAddr); 44 * typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_DEBUGPRINT)( 45 * const ADDR_DEBUGPRINT_INPUT* pInput); 46 * 47 * ///////////////////////////////////////////////////////////////////////////////////////////////// 48 * // Create/Destroy/Config functions 49 * ///////////////////////////////////////////////////////////////////////////////////////////////// 50 * AddrCreate() 51 * AddrDestroy() 52 * 53 * ///////////////////////////////////////////////////////////////////////////////////////////////// 54 * // Surface functions 55 * ///////////////////////////////////////////////////////////////////////////////////////////////// 56 * AddrComputeSurfaceInfo() 57 * AddrComputeSurfaceAddrFromCoord() 58 * AddrComputeSurfaceCoordFromAddr() 59 * 60 * ///////////////////////////////////////////////////////////////////////////////////////////////// 61 * // HTile functions 62 * ///////////////////////////////////////////////////////////////////////////////////////////////// 63 * AddrComputeHtileInfo() 64 * AddrComputeHtileAddrFromCoord() 65 * AddrComputeHtileCoordFromAddr() 66 * 67 * ///////////////////////////////////////////////////////////////////////////////////////////////// 68 * // C-mask functions 69 * ///////////////////////////////////////////////////////////////////////////////////////////////// 70 * AddrComputeCmaskInfo() 71 * AddrComputeCmaskAddrFromCoord() 72 * AddrComputeCmaskCoordFromAddr() 73 * 74 * ///////////////////////////////////////////////////////////////////////////////////////////////// 75 * // F-mask functions 76 * ///////////////////////////////////////////////////////////////////////////////////////////////// 77 * AddrComputeFmaskInfo() 78 * AddrComputeFmaskAddrFromCoord() 79 * AddrComputeFmaskCoordFromAddr() 80 * 81 * ///////////////////////////////////////////////////////////////////////////////////////////////// 82 * // Element/Utility functions 83 * ///////////////////////////////////////////////////////////////////////////////////////////////// 84 * ElemFlt32ToDepthPixel() 85 * ElemFlt32ToColorPixel() 86 * AddrExtractBankPipeSwizzle() 87 * AddrCombineBankPipeSwizzle() 88 * AddrComputeSliceSwizzle() 89 * AddrConvertTileInfoToHW() 90 * AddrConvertTileIndex() 91 * AddrConvertTileIndex1() 92 * AddrGetTileIndex() 93 * AddrComputeBaseSwizzle() 94 * AddrUseTileIndex() 95 * AddrUseCombinedSwizzle() 96 * 97 **/ 98 99 //////////////////////////////////////////////////////////////////////////////////////////////////// 100 // Callback functions 101 //////////////////////////////////////////////////////////////////////////////////////////////////// 102 103 /** 104 **************************************************************************************************** 105 * @brief channel setting structure 106 **************************************************************************************************** 107 */ 108 typedef union _ADDR_CHANNEL_SETTING 109 { 110 struct 111 { 112 UINT_8 valid : 1; ///< Indicate whehter this channel setting is valid 113 UINT_8 channel : 2; ///< 0 for x channel, 1 for y channel, 2 for z channel, 3 for MSAA sample index 114 UINT_8 index : 5; ///< Channel index 115 }; 116 UINT_8 value; ///< Value 117 } ADDR_CHANNEL_SETTING; 118 119 /** 120 **************************************************************************************************** 121 * @brief address equation key structure 122 **************************************************************************************************** 123 */ 124 typedef union _ADDR_EQUATION_KEY 125 { 126 struct 127 { 128 UINT_32 log2ElementBytes : 3; ///< Log2 of Bytes per pixel 129 UINT_32 tileMode : 5; ///< Tile mode 130 UINT_32 microTileType : 3; ///< Micro tile type 131 UINT_32 pipeConfig : 5; ///< pipe config 132 UINT_32 numBanksLog2 : 3; ///< Number of banks log2 133 UINT_32 bankWidth : 4; ///< Bank width 134 UINT_32 bankHeight : 4; ///< Bank height 135 UINT_32 macroAspectRatio : 3; ///< Macro tile aspect ratio 136 UINT_32 prt : 1; ///< SI only, indicate whether this equation is for prt 137 UINT_32 reserved : 1; ///< Reserved bit 138 } fields; 139 UINT_32 value; 140 } ADDR_EQUATION_KEY; 141 142 /** 143 **************************************************************************************************** 144 * @brief address equation structure 145 **************************************************************************************************** 146 */ 147 #define ADDR_MAX_LEGACY_EQUATION_COMP 3u 148 #define ADDR_MAX_EQUATION_COMP 5u 149 #define ADDR_MAX_EQUATION_BIT 20u 150 151 // Invalid equation index 152 #define ADDR_INVALID_EQUATION_INDEX 0xFFFFFFFF 153 154 typedef struct _ADDR_EQUATION 155 { 156 union 157 { 158 struct { 159 ADDR_CHANNEL_SETTING addr[ADDR_MAX_EQUATION_BIT]; ///< addr setting 160 ADDR_CHANNEL_SETTING xor1[ADDR_MAX_EQUATION_BIT]; ///< xor setting 161 ADDR_CHANNEL_SETTING xor2[ADDR_MAX_EQUATION_BIT]; ///< xor2 setting 162 ADDR_CHANNEL_SETTING xor3[ADDR_MAX_EQUATION_BIT]; ///< xor3 setting 163 ADDR_CHANNEL_SETTING xor4[ADDR_MAX_EQUATION_BIT]; ///< xor4 setting 164 }; 165 ///< Components showing the sources of each bit; each bit is result of addr ^ xor ^ xor2... 166 ADDR_CHANNEL_SETTING comps[ADDR_MAX_EQUATION_COMP][ADDR_MAX_EQUATION_BIT]; 167 }; 168 UINT_32 numBits; ///< The number of bits in equation 169 UINT_32 numBitComponents; ///< The max number of channels contributing to a bit 170 BOOL_32 stackedDepthSlices; ///< TRUE if depth slices are treated as being 171 ///< stacked vertically prior to swizzling 172 } ADDR_EQUATION; 173 174 175 /** 176 **************************************************************************************************** 177 * @brief Alloc system memory flags. 178 * @note These flags are reserved for future use and if flags are added will minimize the impact 179 * of the client. 180 **************************************************************************************************** 181 */ 182 typedef union _ADDR_ALLOCSYSMEM_FLAGS 183 { 184 struct 185 { 186 UINT_32 reserved : 32; ///< Reserved for future use. 187 } fields; 188 UINT_32 value; 189 190 } ADDR_ALLOCSYSMEM_FLAGS; 191 192 /** 193 **************************************************************************************************** 194 * @brief Alloc system memory input structure 195 **************************************************************************************************** 196 */ 197 typedef struct _ADDR_ALLOCSYSMEM_INPUT 198 { 199 UINT_32 size; ///< Size of this structure in bytes 200 201 ADDR_ALLOCSYSMEM_FLAGS flags; ///< System memory flags. 202 UINT_32 sizeInBytes; ///< System memory allocation size in bytes. 203 ADDR_CLIENT_HANDLE hClient; ///< Client handle 204 } ADDR_ALLOCSYSMEM_INPUT; 205 206 /** 207 **************************************************************************************************** 208 * ADDR_ALLOCSYSMEM 209 * @brief 210 * Allocate system memory callback function. Returns valid pointer on success. 211 **************************************************************************************************** 212 */ 213 typedef VOID* (ADDR_API* ADDR_ALLOCSYSMEM)( 214 const ADDR_ALLOCSYSMEM_INPUT* pInput); 215 216 /** 217 **************************************************************************************************** 218 * @brief Free system memory input structure 219 **************************************************************************************************** 220 */ 221 typedef struct _ADDR_FREESYSMEM_INPUT 222 { 223 UINT_32 size; ///< Size of this structure in bytes 224 225 VOID* pVirtAddr; ///< Virtual address 226 ADDR_CLIENT_HANDLE hClient; ///< Client handle 227 } ADDR_FREESYSMEM_INPUT; 228 229 /** 230 **************************************************************************************************** 231 * ADDR_FREESYSMEM 232 * @brief 233 * Free system memory callback function. 234 * Returns ADDR_OK on success. 235 **************************************************************************************************** 236 */ 237 typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_FREESYSMEM)( 238 const ADDR_FREESYSMEM_INPUT* pInput); 239 240 /** 241 **************************************************************************************************** 242 * @brief Print debug message input structure 243 **************************************************************************************************** 244 */ 245 typedef struct _ADDR_DEBUGPRINT_INPUT 246 { 247 UINT_32 size; ///< Size of this structure in bytes 248 249 CHAR* pDebugString; ///< Debug print string 250 va_list ap; ///< Variable argument list 251 ADDR_CLIENT_HANDLE hClient; ///< Client handle 252 } ADDR_DEBUGPRINT_INPUT; 253 254 /** 255 **************************************************************************************************** 256 * ADDR_DEBUGPRINT 257 * @brief 258 * Print debug message callback function. 259 * Returns ADDR_OK on success. 260 **************************************************************************************************** 261 */ 262 typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_DEBUGPRINT)( 263 const ADDR_DEBUGPRINT_INPUT* pInput); 264 265 /** 266 **************************************************************************************************** 267 * ADDR_CALLBACKS 268 * 269 * @brief 270 * Address Library needs client to provide system memory alloc/free routines. 271 **************************************************************************************************** 272 */ 273 typedef struct _ADDR_CALLBACKS 274 { 275 ADDR_ALLOCSYSMEM allocSysMem; ///< Routine to allocate system memory 276 ADDR_FREESYSMEM freeSysMem; ///< Routine to free system memory 277 ADDR_DEBUGPRINT debugPrint; ///< Routine to print debug message 278 } ADDR_CALLBACKS; 279 280 //////////////////////////////////////////////////////////////////////////////////////////////////// 281 // Create/Destroy functions 282 //////////////////////////////////////////////////////////////////////////////////////////////////// 283 284 /** 285 **************************************************************************************************** 286 * ADDR_CREATE_FLAGS 287 * 288 * @brief 289 * This structure is used to pass some setup in creation of AddrLib 290 * @note 291 **************************************************************************************************** 292 */ 293 typedef union _ADDR_CREATE_FLAGS 294 { 295 struct 296 { 297 UINT_32 noCubeMipSlicesPad : 1; ///< Turn cubemap faces padding off 298 UINT_32 fillSizeFields : 1; ///< If clients fill size fields in all input and 299 /// output structure 300 UINT_32 useTileIndex : 1; ///< Make tileIndex field in input valid 301 UINT_32 useCombinedSwizzle : 1; ///< Use combined tile swizzle 302 UINT_32 checkLast2DLevel : 1; ///< Check the last 2D mip sub level 303 UINT_32 useHtileSliceAlign : 1; ///< Do htile single slice alignment 304 UINT_32 allowLargeThickTile : 1; ///< Allow 64*thickness*bytesPerPixel > rowSize 305 UINT_32 forceDccAndTcCompat : 1; ///< Force enable DCC and TC compatibility 306 UINT_32 nonPower2MemConfig : 1; ///< Video memory bit width is not power of 2 307 UINT_32 enableAltTiling : 1; ///< Enable alt tile mode 308 UINT_32 reserved : 22; ///< Reserved bits for future use 309 }; 310 311 UINT_32 value; 312 } ADDR_CREATE_FLAGS; 313 314 /** 315 **************************************************************************************************** 316 * ADDR_REGISTER_VALUE 317 * 318 * @brief 319 * Data from registers to setup AddrLib global data, used in AddrCreate 320 **************************************************************************************************** 321 */ 322 typedef struct _ADDR_REGISTER_VALUE 323 { 324 UINT_32 gbAddrConfig; ///< For R8xx, use GB_ADDR_CONFIG register value. 325 /// For R6xx/R7xx, use GB_TILING_CONFIG. 326 /// But they can be treated as the same. 327 /// if this value is 0, use chip to set default value 328 UINT_32 backendDisables; ///< 1 bit per backend, starting with LSB. 1=disabled,0=enabled. 329 /// Register value of CC_RB_BACKEND_DISABLE.BACKEND_DISABLE 330 331 /// R800 registers----------------------------------------------- 332 UINT_32 noOfBanks; ///< Number of h/w ram banks - For r800: MC_ARB_RAMCFG.NOOFBANK 333 /// No enums for this value in h/w header files 334 /// 0: 4 335 /// 1: 8 336 /// 2: 16 337 UINT_32 noOfRanks; /// MC_ARB_RAMCFG.NOOFRANK 338 /// 0: 1 339 /// 1: 2 340 /// SI (R1000) registers----------------------------------------- 341 const UINT_32* pTileConfig; ///< Global tile setting tables 342 UINT_32 noOfEntries; ///< Number of entries in pTileConfig 343 344 ///< CI registers------------------------------------------------- 345 const UINT_32* pMacroTileConfig; ///< Global macro tile mode table 346 UINT_32 noOfMacroEntries; ///< Number of entries in pMacroTileConfig 347 } ADDR_REGISTER_VALUE; 348 349 /** 350 **************************************************************************************************** 351 * ADDR_CREATE_INPUT 352 * 353 * @brief 354 * Parameters use to create an AddrLib Object. Caller must provide all fields. 355 * 356 **************************************************************************************************** 357 */ 358 typedef struct _ADDR_CREATE_INPUT 359 { 360 UINT_32 size; ///< Size of this structure in bytes 361 362 UINT_32 chipEngine; ///< Chip Engine 363 UINT_32 chipFamily; ///< Chip Family 364 UINT_32 chipRevision; ///< Chip Revision 365 ADDR_CALLBACKS callbacks; ///< Callbacks for sysmem alloc/free/print 366 ADDR_CREATE_FLAGS createFlags; ///< Flags to setup AddrLib 367 ADDR_REGISTER_VALUE regValue; ///< Data from registers to setup AddrLib global data 368 ADDR_CLIENT_HANDLE hClient; ///< Client handle 369 UINT_32 minPitchAlignPixels; ///< Minimum pitch alignment in pixels 370 } ADDR_CREATE_INPUT; 371 372 /** 373 **************************************************************************************************** 374 * ADDR_CREATEINFO_OUTPUT 375 * 376 * @brief 377 * Return AddrLib handle to client driver 378 * 379 **************************************************************************************************** 380 */ 381 typedef struct _ADDR_CREATE_OUTPUT 382 { 383 UINT_32 size; ///< Size of this structure in bytes 384 385 ADDR_HANDLE hLib; ///< Address lib handle 386 387 UINT_32 numEquations; ///< Number of equations in the table 388 const ADDR_EQUATION* pEquationTable; ///< Pointer to the equation table 389 } ADDR_CREATE_OUTPUT; 390 391 /** 392 **************************************************************************************************** 393 * AddrCreate 394 * 395 * @brief 396 * Create AddrLib object, must be called before any interface calls 397 * 398 * @return 399 * ADDR_OK if successful 400 **************************************************************************************************** 401 */ 402 ADDR_E_RETURNCODE ADDR_API AddrCreate( 403 const ADDR_CREATE_INPUT* pAddrCreateIn, 404 ADDR_CREATE_OUTPUT* pAddrCreateOut); 405 406 407 408 /** 409 **************************************************************************************************** 410 * AddrDestroy 411 * 412 * @brief 413 * Destroy AddrLib object, must be called to free internally allocated resources. 414 * 415 * @return 416 * ADDR_OK if successful 417 **************************************************************************************************** 418 */ 419 ADDR_E_RETURNCODE ADDR_API AddrDestroy( 420 ADDR_HANDLE hLib); 421 422 423 424 //////////////////////////////////////////////////////////////////////////////////////////////////// 425 // Surface functions 426 //////////////////////////////////////////////////////////////////////////////////////////////////// 427 428 /** 429 **************************************************************************************************** 430 * @brief 431 * Bank/tiling parameters. On function input, these can be set as desired or 432 * left 0 for AddrLib to calculate/default. On function output, these are the actual 433 * parameters used. 434 * @note 435 * Valid bankWidth/bankHeight value: 436 * 1,2,4,8. They are factors instead of pixels or bytes. 437 * 438 * The bank number remains constant across each row of the 439 * macro tile as each pipe is selected, so the number of 440 * tiles in the x direction with the same bank number will 441 * be bank_width * num_pipes. 442 **************************************************************************************************** 443 */ 444 typedef struct _ADDR_TILEINFO 445 { 446 /// Any of these parameters can be set to 0 to use the HW default. 447 UINT_32 banks; ///< Number of banks, numerical value 448 UINT_32 bankWidth; ///< Number of tiles in the X direction in the same bank 449 UINT_32 bankHeight; ///< Number of tiles in the Y direction in the same bank 450 UINT_32 macroAspectRatio; ///< Macro tile aspect ratio. 1-1:1, 2-4:1, 4-16:1, 8-64:1 451 UINT_32 tileSplitBytes; ///< Tile split size, in bytes 452 AddrPipeCfg pipeConfig; ///< Pipe Config = HW enum + 1 453 } ADDR_TILEINFO; 454 455 // Create a define to avoid client change. The removal of R800 is because we plan to implement SI 456 // within 800 HWL - An AddrPipeCfg is added in above data structure 457 typedef ADDR_TILEINFO ADDR_R800_TILEINFO; 458 459 /** 460 **************************************************************************************************** 461 * @brief 462 * Information needed by quad buffer stereo support 463 **************************************************************************************************** 464 */ 465 typedef struct _ADDR_QBSTEREOINFO 466 { 467 UINT_32 eyeHeight; ///< Height (in pixel rows) to right eye 468 UINT_32 rightOffset; ///< Offset (in bytes) to right eye 469 UINT_32 rightSwizzle; ///< TileSwizzle for right eyes 470 } ADDR_QBSTEREOINFO; 471 472 /** 473 **************************************************************************************************** 474 * ADDR_SURFACE_FLAGS 475 * 476 * @brief 477 * Surface flags 478 **************************************************************************************************** 479 */ 480 typedef union _ADDR_SURFACE_FLAGS 481 { 482 struct 483 { 484 UINT_32 color : 1; ///< Flag indicates this is a color buffer 485 UINT_32 depth : 1; ///< Flag indicates this is a depth/stencil buffer 486 UINT_32 stencil : 1; ///< Flag indicates this is a stencil buffer 487 UINT_32 texture : 1; ///< Flag indicates this is a texture 488 UINT_32 cube : 1; ///< Flag indicates this is a cubemap 489 UINT_32 volume : 1; ///< Flag indicates this is a volume texture 490 UINT_32 fmask : 1; ///< Flag indicates this is an fmask 491 UINT_32 cubeAsArray : 1; ///< Flag indicates if treat cubemap as arrays 492 UINT_32 compressZ : 1; ///< Flag indicates z buffer is compressed 493 UINT_32 overlay : 1; ///< Flag indicates this is an overlay surface 494 UINT_32 noStencil : 1; ///< Flag indicates this depth has no separate stencil 495 UINT_32 display : 1; ///< Flag indicates this should match display controller req. 496 UINT_32 opt4Space : 1; ///< Flag indicates this surface should be optimized for space 497 /// i.e. save some memory but may lose performance 498 UINT_32 prt : 1; ///< Flag for partially resident texture 499 UINT_32 qbStereo : 1; ///< Quad buffer stereo surface 500 UINT_32 pow2Pad : 1; ///< SI: Pad to pow2, must set for mipmap (include level0) 501 UINT_32 interleaved : 1; ///< Special flag for interleaved YUV surface padding 502 UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable 503 UINT_32 dispTileType : 1; ///< NI: force display Tiling for 128 bit shared resoruce 504 UINT_32 dccCompatible : 1; ///< VI: whether to make MSAA surface support dcc fast clear 505 UINT_32 dccPipeWorkaround : 1; ///< VI: whether to workaround the HW limit that 506 /// dcc can't be enabled if pipe config of tile mode 507 /// is different from that of ASIC, this flag 508 /// is address lib internal flag, client should ignore it 509 UINT_32 czDispCompatible : 1; ///< SI+: CZ family has a HW bug needs special alignment. 510 /// This flag indicates we need to follow the 511 /// alignment with CZ families or other ASICs under 512 /// PX configuration + CZ. 513 UINT_32 nonSplit : 1; ///< CI: depth texture should not be split 514 UINT_32 disableLinearOpt : 1; ///< Disable tile mode optimization to linear 515 UINT_32 needEquation : 1; ///< Make the surface tile setting equation compatible. 516 /// This flag indicates we need to override tile 517 /// mode to PRT_* tile mode to disable slice rotation, 518 /// which is needed by swizzle pattern equation. 519 UINT_32 skipIndicesOutput : 1; ///< Skipping indices in output. 520 UINT_32 rotateDisplay : 1; ///< Rotate micro tile type 521 UINT_32 minimizeAlignment : 1; ///< Minimize alignment 522 UINT_32 preferEquation : 1; ///< Return equation index without adjusting tile mode 523 UINT_32 matchStencilTileCfg : 1; ///< Select tile index of stencil as well as depth surface 524 /// to make sure they share same tile config parameters 525 UINT_32 disallowLargeThickDegrade : 1; ///< Disallow large thick tile degrade 526 UINT_32 reserved : 1; ///< Reserved bits 527 }; 528 529 UINT_32 value; 530 } ADDR_SURFACE_FLAGS; 531 532 /** 533 **************************************************************************************************** 534 * ADDR_COMPUTE_SURFACE_INFO_INPUT 535 * 536 * @brief 537 * Input structure for AddrComputeSurfaceInfo 538 **************************************************************************************************** 539 */ 540 typedef struct _ADDR_COMPUTE_SURFACE_INFO_INPUT 541 { 542 UINT_32 size; ///< Size of this structure in bytes 543 544 AddrTileMode tileMode; ///< Tile mode 545 AddrFormat format; ///< If format is set to valid one, bpp/width/height 546 /// might be overwritten 547 UINT_32 bpp; ///< Bits per pixel 548 UINT_32 numSamples; ///< Number of samples 549 UINT_32 width; ///< Width, in pixels 550 UINT_32 height; ///< Height, in pixels 551 UINT_32 numSlices; ///< Number of surface slices or depth 552 UINT_32 slice; ///< Slice index 553 UINT_32 mipLevel; ///< Current mipmap level 554 UINT_32 numMipLevels; ///< Number of mips in mip chain 555 ADDR_SURFACE_FLAGS flags; ///< Surface type flags 556 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 557 /// number of samples for normal AA; Set it to the 558 /// number of fragments for EQAA 559 /// r800 and later HWL parameters 560 // Needed by 2D tiling, for linear and 1D tiling, just keep them 0's 561 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Set to 0 to default/calculate 562 AddrTileType tileType; ///< Micro tiling type, not needed when tileIndex != -1 563 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 564 /// while the global useTileIndex is set to 1 565 UINT_32 basePitch; ///< Base level pitch in pixels, 0 means ignored, is a 566 /// must for mip levels from SI+. 567 /// Don't use pitch in blocks for compressed formats! 568 UINT_32 maxBaseAlign; ///< Max base alignment request from client 569 UINT_32 pitchAlign; ///< Pitch alignment request from client 570 UINT_32 heightAlign; ///< Height alignment request from client 571 } ADDR_COMPUTE_SURFACE_INFO_INPUT; 572 573 /** 574 **************************************************************************************************** 575 * ADDR_COMPUTE_SURFACE_INFO_OUTPUT 576 * 577 * @brief 578 * Output structure for AddrComputeSurfInfo 579 * @note 580 Element: AddrLib unit for computing. e.g. BCn: 4x4 blocks; R32B32B32: 32bit with 3x pitch 581 Pixel: Original pixel 582 **************************************************************************************************** 583 */ 584 typedef struct _ADDR_COMPUTE_SURFACE_INFO_OUTPUT 585 { 586 UINT_32 size; ///< Size of this structure in bytes 587 588 UINT_32 pitch; ///< Pitch in elements (in blocks for compressed formats) 589 UINT_32 height; ///< Height in elements (in blocks for compressed formats) 590 UINT_32 depth; ///< Number of slice/depth 591 UINT_64 surfSize; ///< Surface size in bytes 592 AddrTileMode tileMode; ///< Actual tile mode. May differ from that in input 593 UINT_32 baseAlign; ///< Base address alignment 594 UINT_32 pitchAlign; ///< Pitch alignment, in elements 595 UINT_32 heightAlign; ///< Height alignment, in elements 596 UINT_32 depthAlign; ///< Depth alignment, aligned to thickness, for 3d texture 597 UINT_32 bpp; ///< Bits per elements (e.g. blocks for BCn, 1/3 for 96bit) 598 UINT_32 pixelPitch; ///< Pitch in original pixels 599 UINT_32 pixelHeight; ///< Height in original pixels 600 UINT_32 pixelBits; ///< Original bits per pixel, passed from input 601 UINT_64 sliceSize; ///< Size of slice specified by input's slice 602 /// The result is controlled by surface flags & createFlags 603 /// By default this value equals to surfSize for volume 604 UINT_32 pitchTileMax; ///< PITCH_TILE_MAX value for h/w register 605 UINT_32 heightTileMax; ///< HEIGHT_TILE_MAX value for h/w register 606 UINT_32 sliceTileMax; ///< SLICE_TILE_MAX value for h/w register 607 608 UINT_32 numSamples; ///< Pass the effective numSamples processed in this call 609 610 /// r800 and later HWL parameters 611 ADDR_TILEINFO* pTileInfo; ///< Tile parameters used. Filled in if 0 on input 612 AddrTileType tileType; ///< Micro tiling type, only valid when tileIndex != -1 613 INT_32 tileIndex; ///< Tile index, MAY be "downgraded" 614 615 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 616 /// Output flags 617 struct 618 { 619 /// Special information to work around SI mipmap swizzle bug UBTS #317508 620 UINT_32 last2DLevel : 1; ///< TRUE if this is the last 2D(3D) tiled 621 ///< Only meaningful when create flag checkLast2DLevel is set 622 UINT_32 tcCompatible : 1; ///< If the surface can be shader compatible 623 UINT_32 dccUnsupport : 1; ///< If the surface can support DCC compressed rendering 624 UINT_32 prtTileIndex : 1; ///< SI only, indicate the returned tile index is for PRT 625 ///< If address lib return true for mip 0, client should set prt flag 626 ///< for child mips in subsequent compute surface info calls 627 UINT_32 reserved :28; ///< Reserved bits 628 }; 629 630 UINT_32 equationIndex; ///< Equation index in the equation table; 631 632 UINT_32 blockWidth; ///< Width in element inside one block(1D->Micro, 2D->Macro) 633 UINT_32 blockHeight; ///< Height in element inside one block(1D->Micro, 2D->Macro) 634 UINT_32 blockSlices; ///< Slice number inside one block(1D->Micro, 2D->Macro) 635 636 /// Stereo info 637 ADDR_QBSTEREOINFO* pStereoInfo;///< Stereo information, needed when .qbStereo flag is TRUE 638 639 INT_32 stencilTileIdx; ///< stencil tile index output when matchStencilTileCfg was set 640 } ADDR_COMPUTE_SURFACE_INFO_OUTPUT; 641 642 /** 643 **************************************************************************************************** 644 * AddrComputeSurfaceInfo 645 * 646 * @brief 647 * Compute surface width/height/depth/alignments and suitable tiling mode 648 **************************************************************************************************** 649 */ 650 ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceInfo( 651 ADDR_HANDLE hLib, 652 const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, 653 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut); 654 655 656 657 /** 658 **************************************************************************************************** 659 * ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT 660 * 661 * @brief 662 * Input structure for AddrComputeSurfaceAddrFromCoord 663 **************************************************************************************************** 664 */ 665 typedef struct _ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT 666 { 667 UINT_32 size; ///< Size of this structure in bytes 668 669 UINT_32 x; ///< X coordinate 670 UINT_32 y; ///< Y coordinate 671 UINT_32 slice; ///< Slice index 672 UINT_32 sample; ///< Sample index, use fragment index for EQAA 673 674 UINT_32 bpp; ///< Bits per pixel 675 UINT_32 pitch; ///< Surface pitch, in pixels 676 UINT_32 height; ///< Surface height, in pixels 677 UINT_32 numSlices; ///< Surface depth 678 UINT_32 numSamples; ///< Number of samples 679 680 AddrTileMode tileMode; ///< Tile mode 681 BOOL_32 isDepth; ///< TRUE if the surface uses depth sample ordering within 682 /// micro tile. Textures can also choose depth sample order 683 UINT_32 tileBase; ///< Base offset (in bits) inside micro tile which handles 684 /// the case that components are stored separately 685 UINT_32 compBits; ///< The component bits actually needed(for planar surface) 686 687 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 688 /// number of samples for normal AA; Set it to the 689 /// number of fragments for EQAA 690 /// r800 and later HWL parameters 691 // Used for 1D tiling above 692 AddrTileType tileType; ///< See defintion of AddrTileType 693 struct 694 { 695 UINT_32 ignoreSE : 1; ///< TRUE if shader engines are ignored. This is texture 696 /// only flag. Only non-RT texture can set this to TRUE 697 UINT_32 reserved :31; ///< Reserved for future use. 698 }; 699 // 2D tiling needs following structure 700 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data 701 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 702 /// while the global useTileIndex is set to 1 703 union 704 { 705 struct 706 { 707 UINT_32 bankSwizzle; ///< Bank swizzle 708 UINT_32 pipeSwizzle; ///< Pipe swizzle 709 }; 710 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE 711 }; 712 } ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT; 713 714 /** 715 **************************************************************************************************** 716 * ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT 717 * 718 * @brief 719 * Output structure for AddrComputeSurfaceAddrFromCoord 720 **************************************************************************************************** 721 */ 722 typedef struct _ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT 723 { 724 UINT_32 size; ///< Size of this structure in bytes 725 726 UINT_64 addr; ///< Byte address 727 UINT_32 bitPosition; ///< Bit position within surfaceAddr, 0-7. 728 /// For surface bpp < 8, e.g. FMT_1. 729 UINT_32 prtBlockIndex; ///< Index of a PRT tile (64K block) 730 } ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT; 731 732 /** 733 **************************************************************************************************** 734 * AddrComputeSurfaceAddrFromCoord 735 * 736 * @brief 737 * Compute surface address from a given coordinate. 738 **************************************************************************************************** 739 */ 740 ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceAddrFromCoord( 741 ADDR_HANDLE hLib, 742 const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 743 ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut); 744 745 746 747 /** 748 **************************************************************************************************** 749 * ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT 750 * 751 * @brief 752 * Input structure for AddrComputeSurfaceCoordFromAddr 753 **************************************************************************************************** 754 */ 755 typedef struct _ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT 756 { 757 UINT_32 size; ///< Size of this structure in bytes 758 759 UINT_64 addr; ///< Address in bytes 760 UINT_32 bitPosition; ///< Bit position in addr. 0-7. for surface bpp < 8, 761 /// e.g. FMT_1; 762 UINT_32 bpp; ///< Bits per pixel 763 UINT_32 pitch; ///< Pitch, in pixels 764 UINT_32 height; ///< Height in pixels 765 UINT_32 numSlices; ///< Surface depth 766 UINT_32 numSamples; ///< Number of samples 767 768 AddrTileMode tileMode; ///< Tile mode 769 BOOL_32 isDepth; ///< Surface uses depth sample ordering within micro tile. 770 /// Note: Textures can choose depth sample order as well. 771 UINT_32 tileBase; ///< Base offset (in bits) inside micro tile which handles 772 /// the case that components are stored separately 773 UINT_32 compBits; ///< The component bits actually needed(for planar surface) 774 775 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 776 /// number of samples for normal AA; Set it to the 777 /// number of fragments for EQAA 778 /// r800 and later HWL parameters 779 // Used for 1D tiling above 780 AddrTileType tileType; ///< See defintion of AddrTileType 781 struct 782 { 783 UINT_32 ignoreSE : 1; ///< TRUE if shader engines are ignored. This is texture 784 /// only flag. Only non-RT texture can set this to TRUE 785 UINT_32 reserved :31; ///< Reserved for future use. 786 }; 787 // 2D tiling needs following structure 788 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data 789 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 790 /// while the global useTileIndex is set to 1 791 union 792 { 793 struct 794 { 795 UINT_32 bankSwizzle; ///< Bank swizzle 796 UINT_32 pipeSwizzle; ///< Pipe swizzle 797 }; 798 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE 799 }; 800 } ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT; 801 802 /** 803 **************************************************************************************************** 804 * ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT 805 * 806 * @brief 807 * Output structure for AddrComputeSurfaceCoordFromAddr 808 **************************************************************************************************** 809 */ 810 typedef struct _ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT 811 { 812 UINT_32 size; ///< Size of this structure in bytes 813 814 UINT_32 x; ///< X coordinate 815 UINT_32 y; ///< Y coordinate 816 UINT_32 slice; ///< Index of slices 817 UINT_32 sample; ///< Index of samples, means fragment index for EQAA 818 } ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT; 819 820 /** 821 **************************************************************************************************** 822 * AddrComputeSurfaceCoordFromAddr 823 * 824 * @brief 825 * Compute coordinate from a given surface address 826 **************************************************************************************************** 827 */ 828 ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceCoordFromAddr( 829 ADDR_HANDLE hLib, 830 const ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn, 831 ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut); 832 833 //////////////////////////////////////////////////////////////////////////////////////////////////// 834 // HTile functions 835 //////////////////////////////////////////////////////////////////////////////////////////////////// 836 837 /** 838 **************************************************************************************************** 839 * ADDR_HTILE_FLAGS 840 * 841 * @brief 842 * HTILE flags 843 **************************************************************************************************** 844 */ 845 typedef union _ADDR_HTILE_FLAGS 846 { 847 struct 848 { 849 UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable 850 UINT_32 skipTcCompatSizeAlign : 1; ///< Flag indicates that addrLib will not align htile 851 /// size to 256xBankxPipe when computing tc-compatible 852 /// htile info. 853 UINT_32 reserved : 30; ///< Reserved bits 854 }; 855 856 UINT_32 value; 857 } ADDR_HTILE_FLAGS; 858 859 /** 860 **************************************************************************************************** 861 * ADDR_COMPUTE_HTILE_INFO_INPUT 862 * 863 * @brief 864 * Input structure of AddrComputeHtileInfo 865 **************************************************************************************************** 866 */ 867 typedef struct _ADDR_COMPUTE_HTILE_INFO_INPUT 868 { 869 UINT_32 size; ///< Size of this structure in bytes 870 871 ADDR_HTILE_FLAGS flags; ///< HTILE flags 872 UINT_32 pitch; ///< Surface pitch, in pixels 873 UINT_32 height; ///< Surface height, in pixels 874 UINT_32 numSlices; ///< Number of slices 875 BOOL_32 isLinear; ///< Linear or tiled HTILE layout 876 AddrHtileBlockSize blockWidth; ///< 4 or 8. EG above only support 8 877 AddrHtileBlockSize blockHeight; ///< 4 or 8. EG above only support 8 878 ADDR_TILEINFO* pTileInfo; ///< Tile info 879 880 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 881 /// while the global useTileIndex is set to 1 882 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 883 ///< README: When tileIndex is not -1, this must be valid 884 } ADDR_COMPUTE_HTILE_INFO_INPUT; 885 886 /** 887 **************************************************************************************************** 888 * ADDR_COMPUTE_HTILE_INFO_OUTPUT 889 * 890 * @brief 891 * Output structure of AddrComputeHtileInfo 892 **************************************************************************************************** 893 */ 894 typedef struct _ADDR_COMPUTE_HTILE_INFO_OUTPUT 895 { 896 UINT_32 size; ///< Size of this structure in bytes 897 898 UINT_32 pitch; ///< Pitch in pixels of depth buffer represented in this 899 /// HTile buffer. This might be larger than original depth 900 /// buffer pitch when called with an unaligned pitch. 901 UINT_32 height; ///< Height in pixels, as above 902 UINT_64 htileBytes; ///< Size of HTILE buffer, in bytes 903 UINT_32 baseAlign; ///< Base alignment 904 UINT_32 bpp; ///< Bits per pixel for HTILE is how many bits for an 8x8 block! 905 UINT_32 macroWidth; ///< Macro width in pixels, actually squared cache shape 906 UINT_32 macroHeight; ///< Macro height in pixels 907 UINT_64 sliceSize; ///< Slice size, in bytes. 908 BOOL_32 sliceInterleaved; ///< Flag to indicate if different slice's htile is interleaved 909 /// Compute engine clear can't be used if htile is interleaved 910 BOOL_32 nextMipLevelCompressible; ///< Flag to indicate whether HTILE can be enabled in 911 /// next mip level, it also indicates if memory set based 912 /// fast clear can be used for current mip level. 913 } ADDR_COMPUTE_HTILE_INFO_OUTPUT; 914 915 /** 916 **************************************************************************************************** 917 * AddrComputeHtileInfo 918 * 919 * @brief 920 * Compute Htile pitch, height, base alignment and size in bytes 921 **************************************************************************************************** 922 */ 923 ADDR_E_RETURNCODE ADDR_API AddrComputeHtileInfo( 924 ADDR_HANDLE hLib, 925 const ADDR_COMPUTE_HTILE_INFO_INPUT* pIn, 926 ADDR_COMPUTE_HTILE_INFO_OUTPUT* pOut); 927 928 929 930 /** 931 **************************************************************************************************** 932 * ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT 933 * 934 * @brief 935 * Input structure for AddrComputeHtileAddrFromCoord 936 **************************************************************************************************** 937 */ 938 typedef struct _ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT 939 { 940 UINT_32 size; ///< Size of this structure in bytes 941 942 UINT_32 pitch; ///< Pitch, in pixels 943 UINT_32 height; ///< Height in pixels 944 UINT_32 x; ///< X coordinate 945 UINT_32 y; ///< Y coordinate 946 UINT_32 slice; ///< Index of slice 947 UINT_32 numSlices; ///< Number of slices 948 BOOL_32 isLinear; ///< Linear or tiled HTILE layout 949 ADDR_HTILE_FLAGS flags; ///< htile flags 950 AddrHtileBlockSize blockWidth; ///< 4 or 8. 1 means 8, 0 means 4. EG above only support 8 951 AddrHtileBlockSize blockHeight; ///< 4 or 8. 1 means 8, 0 means 4. EG above only support 8 952 ADDR_TILEINFO* pTileInfo; ///< Tile info 953 954 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 955 /// while the global useTileIndex is set to 1 956 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 957 ///< README: When tileIndex is not -1, this must be valid 958 UINT_32 bpp; ///< depth/stencil buffer bit per pixel size 959 UINT_32 zStencilAddr; ///< tcCompatible Z/Stencil surface address 960 } ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT; 961 962 /** 963 **************************************************************************************************** 964 * ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT 965 * 966 * @brief 967 * Output structure for AddrComputeHtileAddrFromCoord 968 **************************************************************************************************** 969 */ 970 typedef struct _ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT 971 { 972 UINT_32 size; ///< Size of this structure in bytes 973 974 UINT_64 addr; ///< Address in bytes 975 UINT_32 bitPosition; ///< Bit position, 0 or 4. CMASK and HTILE shares some lib method. 976 /// So we keep bitPosition for HTILE as well 977 } ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT; 978 979 /** 980 **************************************************************************************************** 981 * AddrComputeHtileAddrFromCoord 982 * 983 * @brief 984 * Compute Htile address according to coordinates (of depth buffer) 985 **************************************************************************************************** 986 */ 987 ADDR_E_RETURNCODE ADDR_API AddrComputeHtileAddrFromCoord( 988 ADDR_HANDLE hLib, 989 const ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, 990 ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut); 991 992 993 994 /** 995 **************************************************************************************************** 996 * ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT 997 * 998 * @brief 999 * Input structure for AddrComputeHtileCoordFromAddr 1000 **************************************************************************************************** 1001 */ 1002 typedef struct _ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT 1003 { 1004 UINT_32 size; ///< Size of this structure in bytes 1005 1006 UINT_64 addr; ///< Address 1007 UINT_32 bitPosition; ///< Bit position 0 or 4. CMASK and HTILE share some methods 1008 /// so we keep bitPosition for HTILE as well 1009 UINT_32 pitch; ///< Pitch, in pixels 1010 UINT_32 height; ///< Height, in pixels 1011 UINT_32 numSlices; ///< Number of slices 1012 BOOL_32 isLinear; ///< Linear or tiled HTILE layout 1013 AddrHtileBlockSize blockWidth; ///< 4 or 8. 1 means 8, 0 means 4. R8xx/R9xx only support 8 1014 AddrHtileBlockSize blockHeight; ///< 4 or 8. 1 means 8, 0 means 4. R8xx/R9xx only support 8 1015 ADDR_TILEINFO* pTileInfo; ///< Tile info 1016 1017 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1018 /// while the global useTileIndex is set to 1 1019 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1020 ///< README: When tileIndex is not -1, this must be valid 1021 } ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT; 1022 1023 /** 1024 **************************************************************************************************** 1025 * ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT 1026 * 1027 * @brief 1028 * Output structure for AddrComputeHtileCoordFromAddr 1029 **************************************************************************************************** 1030 */ 1031 typedef struct _ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT 1032 { 1033 UINT_32 size; ///< Size of this structure in bytes 1034 1035 UINT_32 x; ///< X coordinate 1036 UINT_32 y; ///< Y coordinate 1037 UINT_32 slice; ///< Slice index 1038 } ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT; 1039 1040 /** 1041 **************************************************************************************************** 1042 * AddrComputeHtileCoordFromAddr 1043 * 1044 * @brief 1045 * Compute coordinates within depth buffer (1st pixel of a micro tile) according to 1046 * Htile address 1047 **************************************************************************************************** 1048 */ 1049 ADDR_E_RETURNCODE ADDR_API AddrComputeHtileCoordFromAddr( 1050 ADDR_HANDLE hLib, 1051 const ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, 1052 ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut); 1053 1054 1055 1056 //////////////////////////////////////////////////////////////////////////////////////////////////// 1057 // C-mask functions 1058 //////////////////////////////////////////////////////////////////////////////////////////////////// 1059 1060 /** 1061 **************************************************************************************************** 1062 * ADDR_CMASK_FLAGS 1063 * 1064 * @brief 1065 * CMASK flags 1066 **************************************************************************************************** 1067 */ 1068 typedef union _ADDR_CMASK_FLAGS 1069 { 1070 struct 1071 { 1072 UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable 1073 UINT_32 reserved :31; ///< Reserved bits 1074 }; 1075 1076 UINT_32 value; 1077 } ADDR_CMASK_FLAGS; 1078 1079 /** 1080 **************************************************************************************************** 1081 * ADDR_COMPUTE_CMASK_INFO_INPUT 1082 * 1083 * @brief 1084 * Input structure of AddrComputeCmaskInfo 1085 **************************************************************************************************** 1086 */ 1087 typedef struct _ADDR_COMPUTE_CMASKINFO_INPUT 1088 { 1089 UINT_32 size; ///< Size of this structure in bytes 1090 1091 ADDR_CMASK_FLAGS flags; ///< CMASK flags 1092 UINT_32 pitch; ///< Pitch, in pixels, of color buffer 1093 UINT_32 height; ///< Height, in pixels, of color buffer 1094 UINT_32 numSlices; ///< Number of slices, of color buffer 1095 BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear 1096 ADDR_TILEINFO* pTileInfo; ///< Tile info 1097 1098 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1099 /// while the global useTileIndex is set to 1 1100 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1101 ///< README: When tileIndex is not -1, this must be valid 1102 } ADDR_COMPUTE_CMASK_INFO_INPUT; 1103 1104 /** 1105 **************************************************************************************************** 1106 * ADDR_COMPUTE_CMASK_INFO_OUTPUT 1107 * 1108 * @brief 1109 * Output structure of AddrComputeCmaskInfo 1110 **************************************************************************************************** 1111 */ 1112 typedef struct _ADDR_COMPUTE_CMASK_INFO_OUTPUT 1113 { 1114 UINT_32 size; ///< Size of this structure in bytes 1115 1116 UINT_32 pitch; ///< Pitch in pixels of color buffer which 1117 /// this Cmask matches. The size might be larger than 1118 /// original color buffer pitch when called with 1119 /// an unaligned pitch. 1120 UINT_32 height; ///< Height in pixels, as above 1121 UINT_64 cmaskBytes; ///< Size in bytes of CMask buffer 1122 UINT_32 baseAlign; ///< Base alignment 1123 UINT_32 blockMax; ///< Cmask block size. Need this to set CB_COLORn_MASK register 1124 UINT_32 macroWidth; ///< Macro width in pixels, actually squared cache shape 1125 UINT_32 macroHeight; ///< Macro height in pixels 1126 UINT_64 sliceSize; ///< Slice size, in bytes. 1127 } ADDR_COMPUTE_CMASK_INFO_OUTPUT; 1128 1129 /** 1130 **************************************************************************************************** 1131 * AddrComputeCmaskInfo 1132 * 1133 * @brief 1134 * Compute Cmask pitch, height, base alignment and size in bytes from color buffer 1135 * info 1136 **************************************************************************************************** 1137 */ 1138 ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskInfo( 1139 ADDR_HANDLE hLib, 1140 const ADDR_COMPUTE_CMASK_INFO_INPUT* pIn, 1141 ADDR_COMPUTE_CMASK_INFO_OUTPUT* pOut); 1142 1143 1144 1145 /** 1146 **************************************************************************************************** 1147 * ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT 1148 * 1149 * @brief 1150 * Input structure for AddrComputeCmaskAddrFromCoord 1151 * 1152 **************************************************************************************************** 1153 */ 1154 typedef struct _ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT 1155 { 1156 UINT_32 size; ///< Size of this structure in bytes 1157 UINT_32 x; ///< X coordinate 1158 UINT_32 y; ///< Y coordinate 1159 UINT_64 fmaskAddr; ///< Fmask addr for tc compatible Cmask 1160 UINT_32 slice; ///< Slice index 1161 UINT_32 pitch; ///< Pitch in pixels, of color buffer 1162 UINT_32 height; ///< Height in pixels, of color buffer 1163 UINT_32 numSlices; ///< Number of slices 1164 UINT_32 bpp; 1165 BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear 1166 ADDR_CMASK_FLAGS flags; ///< CMASK flags 1167 ADDR_TILEINFO* pTileInfo; ///< Tile info 1168 1169 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1170 ///< while the global useTileIndex is set to 1 1171 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1172 ///< README: When tileIndex is not -1, this must be valid 1173 } ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT; 1174 1175 /** 1176 **************************************************************************************************** 1177 * ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT 1178 * 1179 * @brief 1180 * Output structure for AddrComputeCmaskAddrFromCoord 1181 **************************************************************************************************** 1182 */ 1183 typedef struct _ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT 1184 { 1185 UINT_32 size; ///< Size of this structure in bytes 1186 1187 UINT_64 addr; ///< CMASK address in bytes 1188 UINT_32 bitPosition; ///< Bit position within addr, 0-7. CMASK is 4 bpp, 1189 /// so the address may be located in bit 0 (0) or 4 (4) 1190 } ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT; 1191 1192 /** 1193 **************************************************************************************************** 1194 * AddrComputeCmaskAddrFromCoord 1195 * 1196 * @brief 1197 * Compute Cmask address according to coordinates (of MSAA color buffer) 1198 **************************************************************************************************** 1199 */ 1200 ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskAddrFromCoord( 1201 ADDR_HANDLE hLib, 1202 const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, 1203 ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut); 1204 1205 1206 1207 /** 1208 **************************************************************************************************** 1209 * ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT 1210 * 1211 * @brief 1212 * Input structure for AddrComputeCmaskCoordFromAddr 1213 **************************************************************************************************** 1214 */ 1215 typedef struct _ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT 1216 { 1217 UINT_32 size; ///< Size of this structure in bytes 1218 1219 UINT_64 addr; ///< CMASK address in bytes 1220 UINT_32 bitPosition; ///< Bit position within addr, 0-7. CMASK is 4 bpp, 1221 /// so the address may be located in bit 0 (0) or 4 (4) 1222 UINT_32 pitch; ///< Pitch, in pixels 1223 UINT_32 height; ///< Height in pixels 1224 UINT_32 numSlices; ///< Number of slices 1225 BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear 1226 ADDR_TILEINFO* pTileInfo; ///< Tile info 1227 1228 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1229 /// while the global useTileIndex is set to 1 1230 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1231 ///< README: When tileIndex is not -1, this must be valid 1232 } ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT; 1233 1234 /** 1235 **************************************************************************************************** 1236 * ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT 1237 * 1238 * @brief 1239 * Output structure for AddrComputeCmaskCoordFromAddr 1240 **************************************************************************************************** 1241 */ 1242 typedef struct _ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT 1243 { 1244 UINT_32 size; ///< Size of this structure in bytes 1245 1246 UINT_32 x; ///< X coordinate 1247 UINT_32 y; ///< Y coordinate 1248 UINT_32 slice; ///< Slice index 1249 } ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT; 1250 1251 /** 1252 **************************************************************************************************** 1253 * AddrComputeCmaskCoordFromAddr 1254 * 1255 * @brief 1256 * Compute coordinates within color buffer (1st pixel of a micro tile) according to 1257 * Cmask address 1258 **************************************************************************************************** 1259 */ 1260 ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskCoordFromAddr( 1261 ADDR_HANDLE hLib, 1262 const ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn, 1263 ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut); 1264 1265 1266 1267 //////////////////////////////////////////////////////////////////////////////////////////////////// 1268 // F-mask functions 1269 //////////////////////////////////////////////////////////////////////////////////////////////////// 1270 1271 /** 1272 **************************************************************************************************** 1273 * ADDR_COMPUTE_FMASK_INFO_INPUT 1274 * 1275 * @brief 1276 * Input structure for AddrComputeFmaskInfo 1277 **************************************************************************************************** 1278 */ 1279 typedef struct _ADDR_COMPUTE_FMASK_INFO_INPUT 1280 { 1281 UINT_32 size; ///< Size of this structure in bytes 1282 1283 AddrTileMode tileMode; ///< Tile mode 1284 UINT_32 pitch; ///< Surface pitch, in pixels 1285 UINT_32 height; ///< Surface height, in pixels 1286 UINT_32 numSlices; ///< Number of slice/depth 1287 UINT_32 numSamples; ///< Number of samples 1288 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 1289 /// number of samples for normal AA; Set it to the 1290 /// number of fragments for EQAA 1291 /// r800 and later HWL parameters 1292 struct 1293 { 1294 UINT_32 resolved: 1; ///< TRUE if the surface is for resolved fmask, only used 1295 /// by H/W clients. S/W should always set it to FALSE. 1296 UINT_32 reserved: 31; ///< Reserved for future use. 1297 }; 1298 ADDR_TILEINFO* pTileInfo; ///< 2D tiling parameters. Clients must give valid data 1299 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1300 /// while the global useTileIndex is set to 1 1301 } ADDR_COMPUTE_FMASK_INFO_INPUT; 1302 1303 /** 1304 **************************************************************************************************** 1305 * ADDR_COMPUTE_FMASK_INFO_OUTPUT 1306 * 1307 * @brief 1308 * Output structure for AddrComputeFmaskInfo 1309 **************************************************************************************************** 1310 */ 1311 typedef struct _ADDR_COMPUTE_FMASK_INFO_OUTPUT 1312 { 1313 UINT_32 size; ///< Size of this structure in bytes 1314 1315 UINT_32 pitch; ///< Pitch of fmask in pixels 1316 UINT_32 height; ///< Height of fmask in pixels 1317 UINT_32 numSlices; ///< Slices of fmask 1318 UINT_64 fmaskBytes; ///< Size of fmask in bytes 1319 UINT_32 baseAlign; ///< Base address alignment 1320 UINT_32 pitchAlign; ///< Pitch alignment 1321 UINT_32 heightAlign; ///< Height alignment 1322 UINT_32 bpp; ///< Bits per pixel of FMASK is: number of bit planes 1323 UINT_32 numSamples; ///< Number of samples, used for dump, export this since input 1324 /// may be changed in 9xx and above 1325 /// r800 and later HWL parameters 1326 ADDR_TILEINFO* pTileInfo; ///< Tile parameters used. Fmask can have different 1327 /// bank_height from color buffer 1328 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1329 /// while the global useTileIndex is set to 1 1330 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1331 UINT_64 sliceSize; ///< Size of slice in bytes 1332 } ADDR_COMPUTE_FMASK_INFO_OUTPUT; 1333 1334 /** 1335 **************************************************************************************************** 1336 * AddrComputeFmaskInfo 1337 * 1338 * @brief 1339 * Compute Fmask pitch/height/depth/alignments and size in bytes 1340 **************************************************************************************************** 1341 */ 1342 ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskInfo( 1343 ADDR_HANDLE hLib, 1344 const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn, 1345 ADDR_COMPUTE_FMASK_INFO_OUTPUT* pOut); 1346 1347 1348 1349 /** 1350 **************************************************************************************************** 1351 * ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT 1352 * 1353 * @brief 1354 * Input structure for AddrComputeFmaskAddrFromCoord 1355 **************************************************************************************************** 1356 */ 1357 typedef struct _ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT 1358 { 1359 UINT_32 size; ///< Size of this structure in bytes 1360 1361 UINT_32 x; ///< X coordinate 1362 UINT_32 y; ///< Y coordinate 1363 UINT_32 slice; ///< Slice index 1364 UINT_32 plane; ///< Plane number 1365 UINT_32 sample; ///< Sample index (fragment index for EQAA) 1366 1367 UINT_32 pitch; ///< Surface pitch, in pixels 1368 UINT_32 height; ///< Surface height, in pixels 1369 UINT_32 numSamples; ///< Number of samples 1370 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 1371 /// number of samples for normal AA; Set it to the 1372 /// number of fragments for EQAA 1373 1374 AddrTileMode tileMode; ///< Tile mode 1375 union 1376 { 1377 struct 1378 { 1379 UINT_32 bankSwizzle; ///< Bank swizzle 1380 UINT_32 pipeSwizzle; ///< Pipe swizzle 1381 }; 1382 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE 1383 }; 1384 1385 /// r800 and later HWL parameters 1386 struct 1387 { 1388 UINT_32 resolved: 1; ///< TRUE if this is a resolved fmask, used by H/W clients 1389 UINT_32 ignoreSE: 1; ///< TRUE if shader engines are ignored. 1390 UINT_32 reserved: 30; ///< Reserved for future use. 1391 }; 1392 ADDR_TILEINFO* pTileInfo; ///< 2D tiling parameters. Client must provide all data 1393 1394 } ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT; 1395 1396 /** 1397 **************************************************************************************************** 1398 * ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT 1399 * 1400 * @brief 1401 * Output structure for AddrComputeFmaskAddrFromCoord 1402 **************************************************************************************************** 1403 */ 1404 typedef struct _ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT 1405 { 1406 UINT_32 size; ///< Size of this structure in bytes 1407 1408 UINT_64 addr; ///< Fmask address 1409 UINT_32 bitPosition; ///< Bit position within fmaskAddr, 0-7. 1410 } ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT; 1411 1412 /** 1413 **************************************************************************************************** 1414 * AddrComputeFmaskAddrFromCoord 1415 * 1416 * @brief 1417 * Compute Fmask address according to coordinates (x,y,slice,sample,plane) 1418 **************************************************************************************************** 1419 */ 1420 ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskAddrFromCoord( 1421 ADDR_HANDLE hLib, 1422 const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn, 1423 ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut); 1424 1425 1426 1427 /** 1428 **************************************************************************************************** 1429 * ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT 1430 * 1431 * @brief 1432 * Input structure for AddrComputeFmaskCoordFromAddr 1433 **************************************************************************************************** 1434 */ 1435 typedef struct _ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT 1436 { 1437 UINT_32 size; ///< Size of this structure in bytes 1438 1439 UINT_64 addr; ///< Address 1440 UINT_32 bitPosition; ///< Bit position within addr, 0-7. 1441 1442 UINT_32 pitch; ///< Pitch, in pixels 1443 UINT_32 height; ///< Height in pixels 1444 UINT_32 numSamples; ///< Number of samples 1445 UINT_32 numFrags; ///< Number of fragments 1446 AddrTileMode tileMode; ///< Tile mode 1447 union 1448 { 1449 struct 1450 { 1451 UINT_32 bankSwizzle; ///< Bank swizzle 1452 UINT_32 pipeSwizzle; ///< Pipe swizzle 1453 }; 1454 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE 1455 }; 1456 1457 /// r800 and later HWL parameters 1458 struct 1459 { 1460 UINT_32 resolved: 1; ///< TRUE if this is a resolved fmask, used by HW components 1461 UINT_32 ignoreSE: 1; ///< TRUE if shader engines are ignored. 1462 UINT_32 reserved: 30; ///< Reserved for future use. 1463 }; 1464 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data 1465 1466 } ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT; 1467 1468 /** 1469 **************************************************************************************************** 1470 * ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT 1471 * 1472 * @brief 1473 * Output structure for AddrComputeFmaskCoordFromAddr 1474 **************************************************************************************************** 1475 */ 1476 typedef struct _ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT 1477 { 1478 UINT_32 size; ///< Size of this structure in bytes 1479 1480 UINT_32 x; ///< X coordinate 1481 UINT_32 y; ///< Y coordinate 1482 UINT_32 slice; ///< Slice index 1483 UINT_32 plane; ///< Plane number 1484 UINT_32 sample; ///< Sample index (fragment index for EQAA) 1485 } ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT; 1486 1487 /** 1488 **************************************************************************************************** 1489 * AddrComputeFmaskCoordFromAddr 1490 * 1491 * @brief 1492 * Compute FMASK coordinate from an given address 1493 **************************************************************************************************** 1494 */ 1495 ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskCoordFromAddr( 1496 ADDR_HANDLE hLib, 1497 const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn, 1498 ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut); 1499 1500 1501 1502 //////////////////////////////////////////////////////////////////////////////////////////////////// 1503 // Element/utility functions 1504 //////////////////////////////////////////////////////////////////////////////////////////////////// 1505 1506 /** 1507 **************************************************************************************************** 1508 * AddrGetVersion 1509 * 1510 * @brief 1511 * Get AddrLib version number 1512 **************************************************************************************************** 1513 */ 1514 UINT_32 ADDR_API AddrGetVersion(ADDR_HANDLE hLib); 1515 1516 /** 1517 **************************************************************************************************** 1518 * AddrUseTileIndex 1519 * 1520 * @brief 1521 * Return TRUE if tileIndex is enabled in this address library 1522 **************************************************************************************************** 1523 */ 1524 BOOL_32 ADDR_API AddrUseTileIndex(ADDR_HANDLE hLib); 1525 1526 /** 1527 **************************************************************************************************** 1528 * AddrUseCombinedSwizzle 1529 * 1530 * @brief 1531 * Return TRUE if combined swizzle is enabled in this address library 1532 **************************************************************************************************** 1533 */ 1534 BOOL_32 ADDR_API AddrUseCombinedSwizzle(ADDR_HANDLE hLib); 1535 1536 /** 1537 **************************************************************************************************** 1538 * ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT 1539 * 1540 * @brief 1541 * Input structure of AddrExtractBankPipeSwizzle 1542 **************************************************************************************************** 1543 */ 1544 typedef struct _ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT 1545 { 1546 UINT_32 size; ///< Size of this structure in bytes 1547 1548 UINT_32 base256b; ///< Base256b value 1549 1550 /// r800 and later HWL parameters 1551 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data 1552 1553 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1554 /// while the global useTileIndex is set to 1 1555 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1556 ///< README: When tileIndex is not -1, this must be valid 1557 } ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT; 1558 1559 /** 1560 **************************************************************************************************** 1561 * ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT 1562 * 1563 * @brief 1564 * Output structure of AddrExtractBankPipeSwizzle 1565 **************************************************************************************************** 1566 */ 1567 typedef struct _ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT 1568 { 1569 UINT_32 size; ///< Size of this structure in bytes 1570 1571 UINT_32 bankSwizzle; ///< Bank swizzle 1572 UINT_32 pipeSwizzle; ///< Pipe swizzle 1573 } ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT; 1574 1575 /** 1576 **************************************************************************************************** 1577 * AddrExtractBankPipeSwizzle 1578 * 1579 * @brief 1580 * Extract Bank and Pipe swizzle from base256b 1581 * @return 1582 * ADDR_OK if no error 1583 **************************************************************************************************** 1584 */ 1585 ADDR_E_RETURNCODE ADDR_API AddrExtractBankPipeSwizzle( 1586 ADDR_HANDLE hLib, 1587 const ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT* pIn, 1588 ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT* pOut); 1589 1590 1591 /** 1592 **************************************************************************************************** 1593 * ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT 1594 * 1595 * @brief 1596 * Input structure of AddrCombineBankPipeSwizzle 1597 **************************************************************************************************** 1598 */ 1599 typedef struct _ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT 1600 { 1601 UINT_32 size; ///< Size of this structure in bytes 1602 1603 UINT_32 bankSwizzle; ///< Bank swizzle 1604 UINT_32 pipeSwizzle; ///< Pipe swizzle 1605 UINT_64 baseAddr; ///< Base address (leave it zero for driver clients) 1606 1607 /// r800 and later HWL parameters 1608 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data 1609 1610 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1611 /// while the global useTileIndex is set to 1 1612 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1613 ///< README: When tileIndex is not -1, this must be valid 1614 } ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT; 1615 1616 /** 1617 **************************************************************************************************** 1618 * ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT 1619 * 1620 * @brief 1621 * Output structure of AddrCombineBankPipeSwizzle 1622 **************************************************************************************************** 1623 */ 1624 typedef struct _ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT 1625 { 1626 UINT_32 size; ///< Size of this structure in bytes 1627 1628 UINT_32 tileSwizzle; ///< Combined swizzle 1629 } ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT; 1630 1631 /** 1632 **************************************************************************************************** 1633 * AddrCombineBankPipeSwizzle 1634 * 1635 * @brief 1636 * Combine Bank and Pipe swizzle 1637 * @return 1638 * ADDR_OK if no error 1639 * @note 1640 * baseAddr here is full MCAddress instead of base256b 1641 **************************************************************************************************** 1642 */ 1643 ADDR_E_RETURNCODE ADDR_API AddrCombineBankPipeSwizzle( 1644 ADDR_HANDLE hLib, 1645 const ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT* pIn, 1646 ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT* pOut); 1647 1648 1649 1650 /** 1651 **************************************************************************************************** 1652 * ADDR_COMPUTE_SLICESWIZZLE_INPUT 1653 * 1654 * @brief 1655 * Input structure of AddrComputeSliceSwizzle 1656 **************************************************************************************************** 1657 */ 1658 typedef struct _ADDR_COMPUTE_SLICESWIZZLE_INPUT 1659 { 1660 UINT_32 size; ///< Size of this structure in bytes 1661 1662 AddrTileMode tileMode; ///< Tile Mode 1663 UINT_32 baseSwizzle; ///< Base tile swizzle 1664 UINT_32 slice; ///< Slice index 1665 UINT_64 baseAddr; ///< Base address, driver should leave it 0 in most cases 1666 1667 /// r800 and later HWL parameters 1668 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Actually banks needed here! 1669 1670 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1671 /// while the global useTileIndex is set to 1 1672 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1673 ///< README: When tileIndex is not -1, this must be valid 1674 } ADDR_COMPUTE_SLICESWIZZLE_INPUT; 1675 1676 1677 1678 /** 1679 **************************************************************************************************** 1680 * ADDR_COMPUTE_SLICESWIZZLE_OUTPUT 1681 * 1682 * @brief 1683 * Output structure of AddrComputeSliceSwizzle 1684 **************************************************************************************************** 1685 */ 1686 typedef struct _ADDR_COMPUTE_SLICESWIZZLE_OUTPUT 1687 { 1688 UINT_32 size; ///< Size of this structure in bytes 1689 1690 UINT_32 tileSwizzle; ///< Recalculated tileSwizzle value 1691 } ADDR_COMPUTE_SLICESWIZZLE_OUTPUT; 1692 1693 /** 1694 **************************************************************************************************** 1695 * AddrComputeSliceSwizzle 1696 * 1697 * @brief 1698 * Extract Bank and Pipe swizzle from base256b 1699 * @return 1700 * ADDR_OK if no error 1701 **************************************************************************************************** 1702 */ 1703 ADDR_E_RETURNCODE ADDR_API AddrComputeSliceSwizzle( 1704 ADDR_HANDLE hLib, 1705 const ADDR_COMPUTE_SLICESWIZZLE_INPUT* pIn, 1706 ADDR_COMPUTE_SLICESWIZZLE_OUTPUT* pOut); 1707 1708 1709 /** 1710 **************************************************************************************************** 1711 * AddrSwizzleGenOption 1712 * 1713 * @brief 1714 * Which swizzle generating options: legacy or linear 1715 **************************************************************************************************** 1716 */ 1717 typedef enum _AddrSwizzleGenOption 1718 { 1719 ADDR_SWIZZLE_GEN_DEFAULT = 0, ///< As is in client driver implemention for swizzle 1720 ADDR_SWIZZLE_GEN_LINEAR = 1, ///< Using a linear increment of swizzle 1721 } AddrSwizzleGenOption; 1722 1723 /** 1724 **************************************************************************************************** 1725 * AddrBlockType 1726 * 1727 * @brief 1728 * Macro define resource block type 1729 **************************************************************************************************** 1730 */ 1731 typedef enum 1732 { 1733 AddrBlockLinear = 0, // Resource uses linear swizzle mode 1734 AddrBlockMicro = 1, // Resource uses 256B block 1735 AddrBlockThin4KB = 2, // Resource uses thin 4KB block 1736 AddrBlockThick4KB = 3, // Resource uses thick 4KB block 1737 AddrBlockThin64KB = 4, // Resource uses thin 64KB block 1738 AddrBlockThick64KB = 5, // Resource uses thick 64KB block 1739 AddrBlockThinVar = 6, // Resource uses thin var block 1740 AddrBlockThickVar = 7, // Resource uses thick var block 1741 AddrBlockMaxTiledType, 1742 1743 AddrBlockThin256KB = AddrBlockThinVar, 1744 AddrBlockThick256KB = AddrBlockThickVar, 1745 } AddrBlockType; 1746 1747 /** 1748 **************************************************************************************************** 1749 * AddrSwizzleOption 1750 * 1751 * @brief 1752 * Controls how swizzle is generated 1753 **************************************************************************************************** 1754 */ 1755 typedef union _ADDR_SWIZZLE_OPTION 1756 { 1757 struct 1758 { 1759 UINT_32 genOption : 1; ///< The way swizzle is generated, see AddrSwizzleGenOption 1760 UINT_32 reduceBankBit : 1; ///< TRUE if we need reduce swizzle bits 1761 UINT_32 reserved :30; ///< Reserved bits 1762 }; 1763 1764 UINT_32 value; 1765 1766 } ADDR_SWIZZLE_OPTION; 1767 1768 /** 1769 **************************************************************************************************** 1770 * ADDR_COMPUTE_BASE_SWIZZLE_INPUT 1771 * 1772 * @brief 1773 * Input structure of AddrComputeBaseSwizzle 1774 **************************************************************************************************** 1775 */ 1776 typedef struct _ADDR_COMPUTE_BASE_SWIZZLE_INPUT 1777 { 1778 UINT_32 size; ///< Size of this structure in bytes 1779 1780 ADDR_SWIZZLE_OPTION option; ///< Swizzle option 1781 UINT_32 surfIndex; ///< Index of this surface type 1782 AddrTileMode tileMode; ///< Tile Mode 1783 1784 /// r800 and later HWL parameters 1785 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Actually banks needed here! 1786 1787 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1788 /// while the global useTileIndex is set to 1 1789 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1790 ///< README: When tileIndex is not -1, this must be valid 1791 } ADDR_COMPUTE_BASE_SWIZZLE_INPUT; 1792 1793 /** 1794 **************************************************************************************************** 1795 * ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT 1796 * 1797 * @brief 1798 * Output structure of AddrComputeBaseSwizzle 1799 **************************************************************************************************** 1800 */ 1801 typedef struct _ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT 1802 { 1803 UINT_32 size; ///< Size of this structure in bytes 1804 1805 UINT_32 tileSwizzle; ///< Combined swizzle 1806 } ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT; 1807 1808 /** 1809 **************************************************************************************************** 1810 * AddrComputeBaseSwizzle 1811 * 1812 * @brief 1813 * Return a Combined Bank and Pipe swizzle base on surface based on surface type/index 1814 * @return 1815 * ADDR_OK if no error 1816 **************************************************************************************************** 1817 */ 1818 ADDR_E_RETURNCODE ADDR_API AddrComputeBaseSwizzle( 1819 ADDR_HANDLE hLib, 1820 const ADDR_COMPUTE_BASE_SWIZZLE_INPUT* pIn, 1821 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT* pOut); 1822 1823 1824 1825 /** 1826 **************************************************************************************************** 1827 * ELEM_GETEXPORTNORM_INPUT 1828 * 1829 * @brief 1830 * Input structure for ElemGetExportNorm 1831 * 1832 **************************************************************************************************** 1833 */ 1834 typedef struct _ELEM_GETEXPORTNORM_INPUT 1835 { 1836 UINT_32 size; ///< Size of this structure in bytes 1837 1838 AddrColorFormat format; ///< Color buffer format; Client should use ColorFormat 1839 AddrSurfaceNumber num; ///< Surface number type; Client should use NumberType 1840 AddrSurfaceSwap swap; ///< Surface swap byte swap; Client should use SurfaceSwap 1841 UINT_32 numSamples; ///< Number of samples 1842 } ELEM_GETEXPORTNORM_INPUT; 1843 1844 /** 1845 **************************************************************************************************** 1846 * ElemGetExportNorm 1847 * 1848 * @brief 1849 * Helper function to check one format can be EXPORT_NUM, which is a register 1850 * CB_COLOR_INFO.SURFACE_FORMAT. FP16 can be reported as EXPORT_NORM for rv770 in r600 1851 * family 1852 * @note 1853 * The implementation is only for r600. 1854 * 00 - EXPORT_FULL: PS exports are 4 pixels with 4 components with 32-bits-per-component. (two 1855 * clocks per export) 1856 * 01 - EXPORT_NORM: PS exports are 4 pixels with 4 components with 16-bits-per-component. (one 1857 * clock per export) 1858 * 1859 **************************************************************************************************** 1860 */ 1861 BOOL_32 ADDR_API ElemGetExportNorm( 1862 ADDR_HANDLE hLib, 1863 const ELEM_GETEXPORTNORM_INPUT* pIn); 1864 1865 1866 1867 /** 1868 **************************************************************************************************** 1869 * ELEM_FLT32TODEPTHPIXEL_INPUT 1870 * 1871 * @brief 1872 * Input structure for addrFlt32ToDepthPixel 1873 * 1874 **************************************************************************************************** 1875 */ 1876 typedef struct _ELEM_FLT32TODEPTHPIXEL_INPUT 1877 { 1878 UINT_32 size; ///< Size of this structure in bytes 1879 1880 AddrDepthFormat format; ///< Depth buffer format 1881 ADDR_FLT_32 comps[2]; ///< Component values (Z/stencil) 1882 } ELEM_FLT32TODEPTHPIXEL_INPUT; 1883 1884 /** 1885 **************************************************************************************************** 1886 * ELEM_FLT32TODEPTHPIXEL_INPUT 1887 * 1888 * @brief 1889 * Output structure for ElemFlt32ToDepthPixel 1890 * 1891 **************************************************************************************************** 1892 */ 1893 typedef struct _ELEM_FLT32TODEPTHPIXEL_OUTPUT 1894 { 1895 UINT_32 size; ///< Size of this structure in bytes 1896 1897 UINT_8* pPixel; ///< Real depth value. Same data type as depth buffer. 1898 /// Client must provide enough storage for this type. 1899 UINT_32 depthBase; ///< Tile base in bits for depth bits 1900 UINT_32 stencilBase; ///< Tile base in bits for stencil bits 1901 UINT_32 depthBits; ///< Bits for depth 1902 UINT_32 stencilBits; ///< Bits for stencil 1903 } ELEM_FLT32TODEPTHPIXEL_OUTPUT; 1904 1905 /** 1906 **************************************************************************************************** 1907 * ElemFlt32ToDepthPixel 1908 * 1909 * @brief 1910 * Convert a FLT_32 value to a depth/stencil pixel value 1911 * 1912 * @return 1913 * Return code 1914 * 1915 **************************************************************************************************** 1916 */ 1917 ADDR_E_RETURNCODE ADDR_API ElemFlt32ToDepthPixel( 1918 ADDR_HANDLE hLib, 1919 const ELEM_FLT32TODEPTHPIXEL_INPUT* pIn, 1920 ELEM_FLT32TODEPTHPIXEL_OUTPUT* pOut); 1921 1922 1923 1924 /** 1925 **************************************************************************************************** 1926 * ELEM_FLT32TOCOLORPIXEL_INPUT 1927 * 1928 * @brief 1929 * Input structure for addrFlt32ToColorPixel 1930 * 1931 **************************************************************************************************** 1932 */ 1933 typedef struct _ELEM_FLT32TOCOLORPIXEL_INPUT 1934 { 1935 UINT_32 size; ///< Size of this structure in bytes 1936 1937 AddrColorFormat format; ///< Color buffer format 1938 AddrSurfaceNumber surfNum; ///< Surface number 1939 AddrSurfaceSwap surfSwap; ///< Surface swap 1940 ADDR_FLT_32 comps[4]; ///< Component values (r/g/b/a) 1941 } ELEM_FLT32TOCOLORPIXEL_INPUT; 1942 1943 /** 1944 **************************************************************************************************** 1945 * ELEM_FLT32TOCOLORPIXEL_INPUT 1946 * 1947 * @brief 1948 * Output structure for ElemFlt32ToColorPixel 1949 * 1950 **************************************************************************************************** 1951 */ 1952 typedef struct _ELEM_FLT32TOCOLORPIXEL_OUTPUT 1953 { 1954 UINT_32 size; ///< Size of this structure in bytes 1955 1956 UINT_8* pPixel; ///< Real color value. Same data type as color buffer. 1957 /// Client must provide enough storage for this type. 1958 } ELEM_FLT32TOCOLORPIXEL_OUTPUT; 1959 1960 /** 1961 **************************************************************************************************** 1962 * ElemFlt32ToColorPixel 1963 * 1964 * @brief 1965 * Convert a FLT_32 value to a red/green/blue/alpha pixel value 1966 * 1967 * @return 1968 * Return code 1969 * 1970 **************************************************************************************************** 1971 */ 1972 ADDR_E_RETURNCODE ADDR_API ElemFlt32ToColorPixel( 1973 ADDR_HANDLE hLib, 1974 const ELEM_FLT32TOCOLORPIXEL_INPUT* pIn, 1975 ELEM_FLT32TOCOLORPIXEL_OUTPUT* pOut); 1976 1977 /** 1978 **************************************************************************************************** 1979 * ElemSize 1980 * 1981 * @brief 1982 * Get bits-per-element for specified format 1983 * 1984 * @return 1985 * Bits-per-element of specified format 1986 * 1987 **************************************************************************************************** 1988 */ 1989 UINT_32 ADDR_API ElemSize( 1990 ADDR_HANDLE hLib, 1991 AddrFormat format); 1992 1993 /** 1994 **************************************************************************************************** 1995 * ADDR_CONVERT_TILEINFOTOHW_INPUT 1996 * 1997 * @brief 1998 * Input structure for AddrConvertTileInfoToHW 1999 * @note 2000 * When reverse is TRUE, indices are igonred 2001 **************************************************************************************************** 2002 */ 2003 typedef struct _ADDR_CONVERT_TILEINFOTOHW_INPUT 2004 { 2005 UINT_32 size; ///< Size of this structure in bytes 2006 BOOL_32 reverse; ///< Convert control flag. 2007 /// FALSE: convert from real value to HW value; 2008 /// TRUE: convert from HW value to real value. 2009 2010 /// r800 and later HWL parameters 2011 ADDR_TILEINFO* pTileInfo; ///< Tile parameters with real value 2012 2013 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 2014 /// while the global useTileIndex is set to 1 2015 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 2016 ///< README: When tileIndex is not -1, this must be valid 2017 UINT_32 bpp; ///< Bits per pixel 2018 } ADDR_CONVERT_TILEINFOTOHW_INPUT; 2019 2020 /** 2021 **************************************************************************************************** 2022 * ADDR_CONVERT_TILEINFOTOHW_OUTPUT 2023 * 2024 * @brief 2025 * Output structure for AddrConvertTileInfoToHW 2026 **************************************************************************************************** 2027 */ 2028 typedef struct _ADDR_CONVERT_TILEINFOTOHW_OUTPUT 2029 { 2030 UINT_32 size; ///< Size of this structure in bytes 2031 2032 /// r800 and later HWL parameters 2033 ADDR_TILEINFO* pTileInfo; ///< Tile parameters with hardware register value 2034 2035 } ADDR_CONVERT_TILEINFOTOHW_OUTPUT; 2036 2037 /** 2038 **************************************************************************************************** 2039 * AddrConvertTileInfoToHW 2040 * 2041 * @brief 2042 * Convert tile info from real value to hardware register value 2043 **************************************************************************************************** 2044 */ 2045 ADDR_E_RETURNCODE ADDR_API AddrConvertTileInfoToHW( 2046 ADDR_HANDLE hLib, 2047 const ADDR_CONVERT_TILEINFOTOHW_INPUT* pIn, 2048 ADDR_CONVERT_TILEINFOTOHW_OUTPUT* pOut); 2049 2050 2051 2052 /** 2053 **************************************************************************************************** 2054 * ADDR_CONVERT_TILEINDEX_INPUT 2055 * 2056 * @brief 2057 * Input structure for AddrConvertTileIndex 2058 **************************************************************************************************** 2059 */ 2060 typedef struct _ADDR_CONVERT_TILEINDEX_INPUT 2061 { 2062 UINT_32 size; ///< Size of this structure in bytes 2063 2064 INT_32 tileIndex; ///< Tile index 2065 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 2066 UINT_32 bpp; ///< Bits per pixel 2067 BOOL_32 tileInfoHw; ///< Set to TRUE if client wants HW enum, otherwise actual 2068 } ADDR_CONVERT_TILEINDEX_INPUT; 2069 2070 /** 2071 **************************************************************************************************** 2072 * ADDR_CONVERT_TILEINDEX_OUTPUT 2073 * 2074 * @brief 2075 * Output structure for AddrConvertTileIndex 2076 **************************************************************************************************** 2077 */ 2078 typedef struct _ADDR_CONVERT_TILEINDEX_OUTPUT 2079 { 2080 UINT_32 size; ///< Size of this structure in bytes 2081 2082 AddrTileMode tileMode; ///< Tile mode 2083 AddrTileType tileType; ///< Tile type 2084 ADDR_TILEINFO* pTileInfo; ///< Tile info 2085 2086 } ADDR_CONVERT_TILEINDEX_OUTPUT; 2087 2088 /** 2089 **************************************************************************************************** 2090 * AddrConvertTileIndex 2091 * 2092 * @brief 2093 * Convert tile index to tile mode/type/info 2094 **************************************************************************************************** 2095 */ 2096 ADDR_E_RETURNCODE ADDR_API AddrConvertTileIndex( 2097 ADDR_HANDLE hLib, 2098 const ADDR_CONVERT_TILEINDEX_INPUT* pIn, 2099 ADDR_CONVERT_TILEINDEX_OUTPUT* pOut); 2100 2101 /** 2102 **************************************************************************************************** 2103 * ADDR_GET_MACROMODEINDEX_INPUT 2104 * 2105 * @brief 2106 * Input structure for AddrGetMacroModeIndex 2107 **************************************************************************************************** 2108 */ 2109 typedef struct _ADDR_GET_MACROMODEINDEX_INPUT 2110 { 2111 UINT_32 size; ///< Size of this structure in bytes 2112 ADDR_SURFACE_FLAGS flags; ///< Surface flag 2113 INT_32 tileIndex; ///< Tile index 2114 UINT_32 bpp; ///< Bits per pixel 2115 UINT_32 numFrags; ///< Number of color fragments 2116 } ADDR_GET_MACROMODEINDEX_INPUT; 2117 2118 /** 2119 **************************************************************************************************** 2120 * ADDR_GET_MACROMODEINDEX_OUTPUT 2121 * 2122 * @brief 2123 * Output structure for AddrGetMacroModeIndex 2124 **************************************************************************************************** 2125 */ 2126 typedef struct _ADDR_GET_MACROMODEINDEX_OUTPUT 2127 { 2128 UINT_32 size; ///< Size of this structure in bytes 2129 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 2130 } ADDR_GET_MACROMODEINDEX_OUTPUT; 2131 2132 /** 2133 **************************************************************************************************** 2134 * AddrGetMacroModeIndex 2135 * 2136 * @brief 2137 * Get macro mode index based on input parameters 2138 **************************************************************************************************** 2139 */ 2140 ADDR_E_RETURNCODE ADDR_API AddrGetMacroModeIndex( 2141 ADDR_HANDLE hLib, 2142 const ADDR_GET_MACROMODEINDEX_INPUT* pIn, 2143 ADDR_GET_MACROMODEINDEX_OUTPUT* pOut); 2144 2145 /** 2146 **************************************************************************************************** 2147 * ADDR_CONVERT_TILEINDEX1_INPUT 2148 * 2149 * @brief 2150 * Input structure for AddrConvertTileIndex1 (without macro mode index) 2151 **************************************************************************************************** 2152 */ 2153 typedef struct _ADDR_CONVERT_TILEINDEX1_INPUT 2154 { 2155 UINT_32 size; ///< Size of this structure in bytes 2156 2157 INT_32 tileIndex; ///< Tile index 2158 UINT_32 bpp; ///< Bits per pixel 2159 UINT_32 numSamples; ///< Number of samples 2160 BOOL_32 tileInfoHw; ///< Set to TRUE if client wants HW enum, otherwise actual 2161 } ADDR_CONVERT_TILEINDEX1_INPUT; 2162 2163 /** 2164 **************************************************************************************************** 2165 * AddrConvertTileIndex1 2166 * 2167 * @brief 2168 * Convert tile index to tile mode/type/info 2169 **************************************************************************************************** 2170 */ 2171 ADDR_E_RETURNCODE ADDR_API AddrConvertTileIndex1( 2172 ADDR_HANDLE hLib, 2173 const ADDR_CONVERT_TILEINDEX1_INPUT* pIn, 2174 ADDR_CONVERT_TILEINDEX_OUTPUT* pOut); 2175 2176 2177 2178 /** 2179 **************************************************************************************************** 2180 * ADDR_GET_TILEINDEX_INPUT 2181 * 2182 * @brief 2183 * Input structure for AddrGetTileIndex 2184 **************************************************************************************************** 2185 */ 2186 typedef struct _ADDR_GET_TILEINDEX_INPUT 2187 { 2188 UINT_32 size; ///< Size of this structure in bytes 2189 2190 AddrTileMode tileMode; ///< Tile mode 2191 AddrTileType tileType; ///< Tile-type: disp/non-disp/... 2192 ADDR_TILEINFO* pTileInfo; ///< Pointer to tile-info structure, can be NULL for linear/1D 2193 } ADDR_GET_TILEINDEX_INPUT; 2194 2195 /** 2196 **************************************************************************************************** 2197 * ADDR_GET_TILEINDEX_OUTPUT 2198 * 2199 * @brief 2200 * Output structure for AddrGetTileIndex 2201 **************************************************************************************************** 2202 */ 2203 typedef struct _ADDR_GET_TILEINDEX_OUTPUT 2204 { 2205 UINT_32 size; ///< Size of this structure in bytes 2206 2207 INT_32 index; ///< index in table 2208 } ADDR_GET_TILEINDEX_OUTPUT; 2209 2210 /** 2211 **************************************************************************************************** 2212 * AddrGetTileIndex 2213 * 2214 * @brief 2215 * Get the tiling mode index in table 2216 **************************************************************************************************** 2217 */ 2218 ADDR_E_RETURNCODE ADDR_API AddrGetTileIndex( 2219 ADDR_HANDLE hLib, 2220 const ADDR_GET_TILEINDEX_INPUT* pIn, 2221 ADDR_GET_TILEINDEX_OUTPUT* pOut); 2222 2223 2224 2225 /** 2226 **************************************************************************************************** 2227 * ADDR_PRT_INFO_INPUT 2228 * 2229 * @brief 2230 * Input structure for AddrComputePrtInfo 2231 **************************************************************************************************** 2232 */ 2233 typedef struct _ADDR_PRT_INFO_INPUT 2234 { 2235 AddrFormat format; ///< Surface format 2236 UINT_32 baseMipWidth; ///< Base mipmap width 2237 UINT_32 baseMipHeight; ///< Base mipmap height 2238 UINT_32 baseMipDepth; ///< Base mipmap depth 2239 UINT_32 numFrags; ///< Number of fragments, 2240 } ADDR_PRT_INFO_INPUT; 2241 2242 /** 2243 **************************************************************************************************** 2244 * ADDR_PRT_INFO_OUTPUT 2245 * 2246 * @brief 2247 * Input structure for AddrComputePrtInfo 2248 **************************************************************************************************** 2249 */ 2250 typedef struct _ADDR_PRT_INFO_OUTPUT 2251 { 2252 UINT_32 prtTileWidth; 2253 UINT_32 prtTileHeight; 2254 } ADDR_PRT_INFO_OUTPUT; 2255 2256 /** 2257 **************************************************************************************************** 2258 * AddrComputePrtInfo 2259 * 2260 * @brief 2261 * Compute prt surface related information 2262 **************************************************************************************************** 2263 */ 2264 ADDR_E_RETURNCODE ADDR_API AddrComputePrtInfo( 2265 ADDR_HANDLE hLib, 2266 const ADDR_PRT_INFO_INPUT* pIn, 2267 ADDR_PRT_INFO_OUTPUT* pOut); 2268 2269 2270 2271 //////////////////////////////////////////////////////////////////////////////////////////////////// 2272 // DCC key functions 2273 //////////////////////////////////////////////////////////////////////////////////////////////////// 2274 2275 /** 2276 **************************************************************************************************** 2277 * _ADDR_COMPUTE_DCCINFO_INPUT 2278 * 2279 * @brief 2280 * Input structure of AddrComputeDccInfo 2281 **************************************************************************************************** 2282 */ 2283 typedef struct _ADDR_COMPUTE_DCCINFO_INPUT 2284 { 2285 UINT_32 size; ///< Size of this structure in bytes 2286 UINT_32 bpp; ///< BitPP of color surface 2287 UINT_32 numSamples; ///< Sample number of color surface 2288 UINT_64 colorSurfSize; ///< Size of color surface to which dcc key is bound 2289 AddrTileMode tileMode; ///< Tile mode of color surface 2290 ADDR_TILEINFO tileInfo; ///< Tile info of color surface 2291 UINT_32 tileSwizzle; ///< Tile swizzle 2292 INT_32 tileIndex; ///< Tile index of color surface, 2293 ///< MUST be -1 if you don't want to use it 2294 ///< while the global useTileIndex is set to 1 2295 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 2296 ///< README: When tileIndex is not -1, this must be valid 2297 } ADDR_COMPUTE_DCCINFO_INPUT; 2298 2299 /** 2300 **************************************************************************************************** 2301 * ADDR_COMPUTE_DCCINFO_OUTPUT 2302 * 2303 * @brief 2304 * Output structure of AddrComputeDccInfo 2305 **************************************************************************************************** 2306 */ 2307 typedef struct _ADDR_COMPUTE_DCCINFO_OUTPUT 2308 { 2309 UINT_32 size; ///< Size of this structure in bytes 2310 UINT_32 dccRamBaseAlign; ///< Base alignment of dcc key 2311 UINT_64 dccRamSize; ///< Size of dcc key 2312 UINT_64 dccFastClearSize; ///< Size of dcc key portion that can be fast cleared 2313 BOOL_32 subLvlCompressible; ///< Whether sub resource is compressiable 2314 BOOL_32 dccRamSizeAligned; ///< Whether the dcc key size is aligned 2315 } ADDR_COMPUTE_DCCINFO_OUTPUT; 2316 2317 /** 2318 **************************************************************************************************** 2319 * AddrComputeDccInfo 2320 * 2321 * @brief 2322 * Compute DCC key size, base alignment 2323 * info 2324 **************************************************************************************************** 2325 */ 2326 ADDR_E_RETURNCODE ADDR_API AddrComputeDccInfo( 2327 ADDR_HANDLE hLib, 2328 const ADDR_COMPUTE_DCCINFO_INPUT* pIn, 2329 ADDR_COMPUTE_DCCINFO_OUTPUT* pOut); 2330 2331 2332 2333 /** 2334 **************************************************************************************************** 2335 * ADDR_GET_MAX_ALIGNMENTS_OUTPUT 2336 * 2337 * @brief 2338 * Output structure of AddrGetMaxAlignments 2339 **************************************************************************************************** 2340 */ 2341 typedef struct ADDR_GET_MAX_ALINGMENTS_OUTPUT 2342 { 2343 UINT_32 size; ///< Size of this structure in bytes 2344 UINT_32 baseAlign; ///< Maximum base alignment in bytes 2345 } ADDR_GET_MAX_ALIGNMENTS_OUTPUT; 2346 2347 /** 2348 **************************************************************************************************** 2349 * AddrGetMaxAlignments 2350 * 2351 * @brief 2352 * Gets maximnum alignments 2353 **************************************************************************************************** 2354 */ 2355 ADDR_E_RETURNCODE ADDR_API AddrGetMaxAlignments( 2356 ADDR_HANDLE hLib, 2357 ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut); 2358 2359 /** 2360 **************************************************************************************************** 2361 * AddrGetMaxMetaAlignments 2362 * 2363 * @brief 2364 * Gets maximnum alignments for metadata 2365 **************************************************************************************************** 2366 */ 2367 ADDR_E_RETURNCODE ADDR_API AddrGetMaxMetaAlignments( 2368 ADDR_HANDLE hLib, 2369 ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut); 2370 2371 /** 2372 **************************************************************************************************** 2373 * Address library interface version 2 2374 * available from Gfx9 hardware 2375 **************************************************************************************************** 2376 * Addr2ComputeSurfaceInfo() 2377 * Addr2ComputeSurfaceAddrFromCoord() 2378 * Addr2ComputeSurfaceCoordFromAddr() 2379 2380 * Addr2ComputeHtileInfo() 2381 * Addr2ComputeHtileAddrFromCoord() 2382 * Addr2ComputeHtileCoordFromAddr() 2383 * 2384 * Addr2ComputeCmaskInfo() 2385 * Addr2ComputeCmaskAddrFromCoord() 2386 * Addr2ComputeCmaskCoordFromAddr() 2387 * 2388 * Addr2ComputeFmaskInfo() 2389 * Addr2ComputeFmaskAddrFromCoord() 2390 * Addr2ComputeFmaskCoordFromAddr() 2391 * 2392 * Addr2ComputeDccInfo() 2393 * 2394 **/ 2395 2396 2397 //////////////////////////////////////////////////////////////////////////////////////////////////// 2398 // Surface functions for Gfx9 2399 //////////////////////////////////////////////////////////////////////////////////////////////////// 2400 2401 /** 2402 **************************************************************************************************** 2403 * ADDR2_SURFACE_FLAGS 2404 * 2405 * @brief 2406 * Surface flags 2407 **************************************************************************************************** 2408 */ 2409 typedef union _ADDR2_SURFACE_FLAGS 2410 { 2411 struct 2412 { 2413 UINT_32 color : 1; ///< This resource is a color buffer, can be used with RTV 2414 UINT_32 depth : 1; ///< Thie resource is a depth buffer, can be used with DSV 2415 UINT_32 stencil : 1; ///< Thie resource is a stencil buffer, can be used with DSV 2416 UINT_32 fmask : 1; ///< This is an fmask surface 2417 UINT_32 overlay : 1; ///< This is an overlay surface 2418 UINT_32 display : 1; ///< This resource is displable, can be used with DRV 2419 UINT_32 prt : 1; ///< This is a partially resident texture 2420 UINT_32 qbStereo : 1; ///< This is a quad buffer stereo surface 2421 UINT_32 interleaved : 1; ///< Special flag for interleaved YUV surface padding 2422 UINT_32 texture : 1; ///< This resource can be used with SRV 2423 UINT_32 unordered : 1; ///< This resource can be used with UAV 2424 UINT_32 rotated : 1; ///< This resource is rotated and displable 2425 UINT_32 needEquation : 1; ///< This resource needs equation to be generated if possible 2426 UINT_32 opt4space : 1; ///< This resource should be optimized for space 2427 UINT_32 minimizeAlign : 1; ///< This resource should use minimum alignment 2428 UINT_32 noMetadata : 1; ///< This resource has no metadata 2429 UINT_32 metaRbUnaligned : 1; ///< This resource has rb unaligned metadata 2430 UINT_32 metaPipeUnaligned : 1; ///< This resource has pipe unaligned metadata 2431 UINT_32 view3dAs2dArray : 1; ///< This resource is a 3D resource viewed as 2D array 2432 UINT_32 allowExtEquation : 1; ///< If unset, only legacy DX eqs are allowed (2 XORs) 2433 UINT_32 reserved : 12; ///< Reserved bits 2434 }; 2435 2436 UINT_32 value; 2437 } ADDR2_SURFACE_FLAGS; 2438 2439 /** 2440 **************************************************************************************************** 2441 * ADDR2_COMPUTE_SURFACE_INFO_INPUT 2442 * 2443 * @brief 2444 * Input structure for Addr2ComputeSurfaceInfo 2445 **************************************************************************************************** 2446 */ 2447 typedef struct _ADDR2_COMPUTE_SURFACE_INFO_INPUT 2448 { 2449 UINT_32 size; ///< Size of this structure in bytes 2450 2451 ADDR2_SURFACE_FLAGS flags; ///< Surface flags 2452 AddrSwizzleMode swizzleMode; ///< Swizzle Mode for Gfx9 2453 AddrResourceType resourceType; ///< Surface type 2454 AddrFormat format; ///< Surface format 2455 UINT_32 bpp; ///< bits per pixel 2456 UINT_32 width; ///< Width (of mip0), in pixels 2457 UINT_32 height; ///< Height (of mip0), in pixels 2458 UINT_32 numSlices; ///< Number surface slice/depth (of mip0), 2459 UINT_32 numMipLevels; ///< Total mipmap levels. 2460 UINT_32 numSamples; ///< Number of samples 2461 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 2462 /// number of samples for normal AA; Set it to the 2463 /// number of fragments for EQAA 2464 UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats) 2465 UINT_32 sliceAlign; ///< Required slice size in bytes 2466 } ADDR2_COMPUTE_SURFACE_INFO_INPUT; 2467 2468 /** 2469 **************************************************************************************************** 2470 * ADDR2_MIP_INFO 2471 * 2472 * @brief 2473 * Structure that contains information for mip level 2474 * 2475 **************************************************************************************************** 2476 */ 2477 typedef struct _ADDR2_MIP_INFO 2478 { 2479 UINT_32 pitch; ///< Pitch in elements 2480 UINT_32 height; ///< Padded height in elements 2481 UINT_32 depth; ///< Padded depth 2482 UINT_32 pixelPitch; ///< Pitch in pixels 2483 UINT_32 pixelHeight; ///< Padded height in pixels 2484 UINT_32 equationIndex; ///< Equation index in the equation table 2485 UINT_64 offset; ///< Offset in bytes from mip base, should only be used 2486 ///< to setup vam surface descriptor, can't be used 2487 ///< to setup swizzle pattern 2488 UINT_64 macroBlockOffset; ///< macro block offset in bytes from mip base 2489 UINT_32 mipTailOffset; ///< mip tail offset in bytes 2490 UINT_32 mipTailCoordX; ///< mip tail coord x 2491 UINT_32 mipTailCoordY; ///< mip tail coord y 2492 UINT_32 mipTailCoordZ; ///< mip tail coord z 2493 } ADDR2_MIP_INFO; 2494 2495 /** 2496 **************************************************************************************************** 2497 * ADDR2_COMPUTE_SURFACE_INFO_OUTPUT 2498 * 2499 * @brief 2500 * Output structure for Addr2ComputeSurfInfo 2501 * @note 2502 Element: AddrLib unit for computing. e.g. BCn: 4x4 blocks; R32B32B32: 32bit with 3x pitch 2503 Pixel: Original pixel 2504 **************************************************************************************************** 2505 */ 2506 typedef struct _ADDR2_COMPUTE_SURFACE_INFO_OUTPUT 2507 { 2508 UINT_32 size; ///< Size of this structure in bytes 2509 2510 UINT_32 pitch; ///< Pitch in elements (blocks for compressed formats) 2511 UINT_32 height; ///< Padded height (of mip0) in elements 2512 UINT_32 numSlices; ///< Padded depth for 3d resource 2513 ///< or padded number of slices for 2d array resource 2514 UINT_32 mipChainPitch; ///< Pitch (of total mip chain) in elements 2515 UINT_32 mipChainHeight; ///< Padded height (of total mip chain) in elements 2516 UINT_32 mipChainSlice; ///< Padded depth (of total mip chain) 2517 UINT_64 sliceSize; ///< Slice (total mip chain) size in bytes 2518 UINT_64 surfSize; ///< Surface (total mip chain) size in bytes 2519 UINT_32 baseAlign; ///< Base address alignment 2520 UINT_32 bpp; ///< Bits per elements 2521 /// (e.g. blocks for BCn, 1/3 for 96bit) 2522 UINT_32 pixelMipChainPitch; ///< Mip chain pitch in original pixels 2523 UINT_32 pixelMipChainHeight; ///< Mip chain height in original pixels 2524 UINT_32 pixelPitch; ///< Pitch in original pixels 2525 UINT_32 pixelHeight; ///< Height in original pixels 2526 UINT_32 pixelBits; ///< Original bits per pixel, passed from input 2527 2528 UINT_32 blockWidth; ///< Width in element inside one block 2529 UINT_32 blockHeight; ///< Height in element inside one block 2530 UINT_32 blockSlices; ///< Slice number inside one block 2531 ///< Prt tile is one block, its width/height/slice 2532 ///< equals to blcok width/height/slice 2533 2534 BOOL_32 epitchIsHeight; ///< Whether to use height to program epitch register 2535 /// Stereo info 2536 ADDR_QBSTEREOINFO* pStereoInfo; ///< Stereo info, needed if qbStereo flag is TRUE 2537 /// Mip info 2538 ADDR2_MIP_INFO* pMipInfo; ///< Pointer to mip information array 2539 /// if it is not NULL, the array is assumed to 2540 /// contain numMipLevels entries 2541 2542 UINT_32 equationIndex; ///< Equation index in the equation table of mip0 2543 BOOL_32 mipChainInTail; ///< If whole mipchain falls into mip tail block 2544 UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if there is no mip 2545 /// in tail, it will be set to number of mip levels 2546 } ADDR2_COMPUTE_SURFACE_INFO_OUTPUT; 2547 2548 /** 2549 **************************************************************************************************** 2550 * Addr2ComputeSurfaceInfo 2551 * 2552 * @brief 2553 * Compute surface width/height/slices/alignments and suitable tiling mode 2554 **************************************************************************************************** 2555 */ 2556 ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceInfo( 2557 ADDR_HANDLE hLib, 2558 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 2559 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut); 2560 2561 2562 2563 /** 2564 **************************************************************************************************** 2565 * ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT 2566 * 2567 * @brief 2568 * Input structure for Addr2ComputeSurfaceAddrFromCoord 2569 **************************************************************************************************** 2570 */ 2571 typedef struct _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT 2572 { 2573 UINT_32 size; ///< Size of this structure in bytes 2574 2575 UINT_32 x; ///< X coordinate 2576 UINT_32 y; ///< Y coordinate 2577 UINT_32 slice; ///< Slice index 2578 UINT_32 sample; ///< Sample index, use fragment index for EQAA 2579 UINT_32 mipId; ///< the mip ID in mip chain 2580 2581 AddrSwizzleMode swizzleMode; ///< Swizzle mode for Gfx9 2582 ADDR2_SURFACE_FLAGS flags; ///< Surface flags 2583 AddrResourceType resourceType; ///< Surface type 2584 UINT_32 bpp; ///< Bits per pixel 2585 UINT_32 unalignedWidth; ///< Surface original width (of mip0) 2586 UINT_32 unalignedHeight; ///< Surface original height (of mip0) 2587 UINT_32 numSlices; ///< Surface original slices (of mip0) 2588 UINT_32 numMipLevels; ///< Total mipmap levels 2589 UINT_32 numSamples; ///< Number of samples 2590 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 2591 /// number of samples for normal AA; Set it to the 2592 /// number of fragments for EQAA 2593 2594 UINT_32 pipeBankXor; ///< Combined swizzle used to do bank/pipe rotation 2595 UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats) 2596 } ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT; 2597 2598 /** 2599 **************************************************************************************************** 2600 * ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT 2601 * 2602 * @brief 2603 * Output structure for Addr2ComputeSurfaceAddrFromCoord 2604 **************************************************************************************************** 2605 */ 2606 typedef struct _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT 2607 { 2608 UINT_32 size; ///< Size of this structure in bytes 2609 2610 UINT_64 addr; ///< Byte offset from the image starting address 2611 UINT_32 bitPosition; ///< Bit position within surfaceAddr, 0-7. 2612 /// For surface bpp < 8, e.g. FMT_1. 2613 UINT_32 prtBlockIndex; ///< Index of a PRT tile (64K block) 2614 } ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT; 2615 2616 /** 2617 **************************************************************************************************** 2618 * Addr2ComputeSurfaceAddrFromCoord 2619 * 2620 * @brief 2621 * Compute surface address from a given coordinate. 2622 **************************************************************************************************** 2623 */ 2624 ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceAddrFromCoord( 2625 ADDR_HANDLE hLib, 2626 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 2627 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut); 2628 2629 2630 2631 /** 2632 **************************************************************************************************** 2633 * ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT 2634 * 2635 * @brief 2636 * Input structure for Addr2ComputeSurfaceCoordFromAddr 2637 **************************************************************************************************** 2638 */ 2639 typedef struct _ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT 2640 { 2641 UINT_32 size; ///< Size of this structure in bytes 2642 2643 UINT_64 addr; ///< Address in bytes 2644 UINT_32 bitPosition; ///< Bit position in addr. 0-7. for surface bpp < 8, 2645 /// e.g. FMT_1; 2646 2647 AddrSwizzleMode swizzleMode; ///< Swizzle mode for Gfx9 2648 ADDR2_SURFACE_FLAGS flags; ///< Surface flags 2649 AddrResourceType resourceType; ///< Surface type 2650 UINT_32 bpp; ///< Bits per pixel 2651 UINT_32 unalignedWidth; ///< Surface original width (of mip0) 2652 UINT_32 unalignedHeight; ///< Surface original height (of mip0) 2653 UINT_32 numSlices; ///< Surface original slices (of mip0) 2654 UINT_32 numMipLevels; ///< Total mipmap levels. 2655 UINT_32 numSamples; ///< Number of samples 2656 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 2657 /// number of samples for normal AA; Set it to the 2658 /// number of fragments for EQAA 2659 2660 UINT_32 pipeBankXor; ///< Combined swizzle used to do bank/pipe rotation 2661 UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats) 2662 } ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT; 2663 2664 /** 2665 **************************************************************************************************** 2666 * ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT 2667 * 2668 * @brief 2669 * Output structure for Addr2ComputeSurfaceCoordFromAddr 2670 **************************************************************************************************** 2671 */ 2672 typedef struct _ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT 2673 { 2674 UINT_32 size; ///< Size of this structure in bytes 2675 2676 UINT_32 x; ///< X coordinate 2677 UINT_32 y; ///< Y coordinate 2678 UINT_32 slice; ///< Index of slices 2679 UINT_32 sample; ///< Index of samples, means fragment index for EQAA 2680 UINT_32 mipId; ///< mipmap level id 2681 } ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT; 2682 2683 /** 2684 **************************************************************************************************** 2685 * Addr2ComputeSurfaceCoordFromAddr 2686 * 2687 * @brief 2688 * Compute coordinate from a given surface address 2689 **************************************************************************************************** 2690 */ 2691 ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceCoordFromAddr( 2692 ADDR_HANDLE hLib, 2693 const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn, 2694 ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut); 2695 2696 2697 2698 //////////////////////////////////////////////////////////////////////////////////////////////////// 2699 // HTile functions for Gfx9 2700 //////////////////////////////////////////////////////////////////////////////////////////////////// 2701 2702 /** 2703 **************************************************************************************************** 2704 * ADDR2_META_FLAGS 2705 * 2706 * @brief 2707 * Metadata flags 2708 **************************************************************************************************** 2709 */ 2710 typedef union _ADDR2_META_FLAGS 2711 { 2712 struct 2713 { 2714 UINT_32 pipeAligned : 1; ///< if Metadata being pipe aligned 2715 UINT_32 rbAligned : 1; ///< if Metadata being RB aligned 2716 UINT_32 linear : 1; ///< if Metadata linear, GFX9 does not suppord this! 2717 UINT_32 reserved : 29; ///< Reserved bits 2718 }; 2719 2720 UINT_32 value; 2721 } ADDR2_META_FLAGS; 2722 2723 /** 2724 **************************************************************************************************** 2725 * ADDR2_META_MIP_INFO 2726 * 2727 * @brief 2728 * Structure to store per mip metadata information 2729 **************************************************************************************************** 2730 */ 2731 typedef struct _ADDR2_META_MIP_INFO 2732 { 2733 BOOL_32 inMiptail; 2734 union 2735 { 2736 struct 2737 { 2738 UINT_32 startX; 2739 UINT_32 startY; 2740 UINT_32 startZ; 2741 UINT_32 width; 2742 UINT_32 height; 2743 UINT_32 depth; 2744 }; 2745 2746 // GFX10 2747 struct 2748 { 2749 UINT_32 offset; ///< Metadata offset within one slice, 2750 /// the thickness of a slice is meta block depth. 2751 UINT_32 sliceSize; ///< Metadata size within one slice, 2752 /// the thickness of a slice is meta block depth. 2753 }; 2754 }; 2755 } ADDR2_META_MIP_INFO; 2756 2757 /** 2758 **************************************************************************************************** 2759 * ADDR2_COMPUTE_HTILE_INFO_INPUT 2760 * 2761 * @brief 2762 * Input structure of Addr2ComputeHtileInfo 2763 **************************************************************************************************** 2764 */ 2765 typedef struct _ADDR2_COMPUTE_HTILE_INFO_INPUT 2766 { 2767 UINT_32 size; ///< Size of this structure in bytes 2768 2769 ADDR2_META_FLAGS hTileFlags; ///< HTILE flags 2770 ADDR2_SURFACE_FLAGS depthFlags; ///< Depth surface flags 2771 AddrSwizzleMode swizzleMode; ///< Depth surface swizzle mode 2772 UINT_32 unalignedWidth; ///< Depth surface original width (of mip0) 2773 UINT_32 unalignedHeight; ///< Depth surface original height (of mip0) 2774 UINT_32 numSlices; ///< Number of slices of depth surface (of mip0) 2775 UINT_32 numMipLevels; ///< Total mipmap levels of color surface 2776 UINT_32 firstMipIdInTail; /// Id of the first mip in tail, 2777 /// if no mip is in tail, it should be set to 2778 /// number of mip levels 2779 /// Only for GFX10 2780 } ADDR2_COMPUTE_HTILE_INFO_INPUT; 2781 2782 /** 2783 **************************************************************************************************** 2784 * ADDR2_COMPUTE_HTILE_INFO_OUTPUT 2785 * 2786 * @brief 2787 * Output structure of Addr2ComputeHtileInfo 2788 **************************************************************************************************** 2789 */ 2790 typedef struct _ADDR2_COMPUTE_HTILE_INFO_OUTPUT 2791 { 2792 UINT_32 size; ///< Size of this structure in bytes 2793 2794 UINT_32 pitch; ///< Pitch in pixels of depth buffer represented in this 2795 /// HTile buffer. This might be larger than original depth 2796 /// buffer pitch when called with an unaligned pitch. 2797 UINT_32 height; ///< Height in pixels, as above 2798 UINT_32 baseAlign; ///< Base alignment 2799 UINT_32 sliceSize; ///< Slice size, in bytes. 2800 UINT_32 htileBytes; ///< Size of HTILE buffer, in bytes 2801 UINT_32 metaBlkWidth; ///< Meta block width 2802 UINT_32 metaBlkHeight; ///< Meta block height 2803 UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice 2804 2805 ADDR2_META_MIP_INFO* pMipInfo; ///< HTILE mip information 2806 2807 struct { 2808 UINT_16* gfx10_bits; /* 72 2-byte elements */ 2809 } equation; 2810 } ADDR2_COMPUTE_HTILE_INFO_OUTPUT; 2811 2812 /** 2813 **************************************************************************************************** 2814 * Addr2ComputeHtileInfo 2815 * 2816 * @brief 2817 * Compute Htile pitch, height, base alignment and size in bytes 2818 **************************************************************************************************** 2819 */ 2820 ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileInfo( 2821 ADDR_HANDLE hLib, 2822 const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn, 2823 ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut); 2824 2825 2826 2827 /** 2828 **************************************************************************************************** 2829 * ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT 2830 * 2831 * @brief 2832 * Input structure for Addr2ComputeHtileAddrFromCoord 2833 **************************************************************************************************** 2834 */ 2835 typedef struct _ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT 2836 { 2837 UINT_32 size; ///< Size of this structure in bytes 2838 2839 UINT_32 x; ///< X coordinate 2840 UINT_32 y; ///< Y coordinate 2841 UINT_32 slice; ///< Index of slices 2842 UINT_32 mipId; ///< mipmap level id 2843 2844 ADDR2_META_FLAGS hTileFlags; ///< HTILE flags 2845 ADDR2_SURFACE_FLAGS depthflags; ///< Depth surface flags 2846 AddrSwizzleMode swizzleMode; ///< Depth surface swizzle mode 2847 UINT_32 bpp; ///< Depth surface bits per pixel 2848 UINT_32 unalignedWidth; ///< Depth surface original width (of mip0) 2849 UINT_32 unalignedHeight; ///< Depth surface original height (of mip0) 2850 UINT_32 numSlices; ///< Depth surface original depth (of mip0) 2851 UINT_32 numMipLevels; ///< Depth surface total mipmap levels 2852 UINT_32 numSamples; ///< Depth surface number of samples 2853 UINT_32 pipeXor; ///< Pipe xor setting 2854 } ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT; 2855 2856 /** 2857 **************************************************************************************************** 2858 * ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT 2859 * 2860 * @brief 2861 * Output structure for Addr2ComputeHtileAddrFromCoord 2862 **************************************************************************************************** 2863 */ 2864 typedef struct _ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT 2865 { 2866 UINT_32 size; ///< Size of this structure in bytes 2867 2868 UINT_64 addr; ///< Address in bytes 2869 } ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT; 2870 2871 /** 2872 **************************************************************************************************** 2873 * Addr2ComputeHtileAddrFromCoord 2874 * 2875 * @brief 2876 * Compute Htile address according to coordinates (of depth buffer) 2877 **************************************************************************************************** 2878 */ 2879 ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileAddrFromCoord( 2880 ADDR_HANDLE hLib, 2881 const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, 2882 ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut); 2883 2884 2885 2886 /** 2887 **************************************************************************************************** 2888 * ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT 2889 * 2890 * @brief 2891 * Input structure for Addr2ComputeHtileCoordFromAddr 2892 **************************************************************************************************** 2893 */ 2894 typedef struct _ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT 2895 { 2896 UINT_32 size; ///< Size of this structure in bytes 2897 2898 UINT_64 addr; ///< Address 2899 2900 ADDR2_META_FLAGS hTileFlags; ///< HTILE flags 2901 ADDR2_SURFACE_FLAGS depthFlags; ///< Depth surface flags 2902 AddrSwizzleMode swizzleMode; ///< Depth surface swizzle mode 2903 UINT_32 bpp; ///< Depth surface bits per pixel 2904 UINT_32 unalignedWidth; ///< Depth surface original width (of mip0) 2905 UINT_32 unalignedHeight; ///< Depth surface original height (of mip0) 2906 UINT_32 numSlices; ///< Depth surface original depth (of mip0) 2907 UINT_32 numMipLevels; ///< Depth surface total mipmap levels 2908 UINT_32 numSamples; ///< Depth surface number of samples 2909 UINT_32 pipeXor; ///< Pipe xor setting 2910 } ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT; 2911 2912 /** 2913 **************************************************************************************************** 2914 * ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT 2915 * 2916 * @brief 2917 * Output structure for Addr2ComputeHtileCoordFromAddr 2918 **************************************************************************************************** 2919 */ 2920 typedef struct _ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT 2921 { 2922 UINT_32 size; ///< Size of this structure in bytes 2923 2924 UINT_32 x; ///< X coordinate 2925 UINT_32 y; ///< Y coordinate 2926 UINT_32 slice; ///< Index of slices 2927 UINT_32 mipId; ///< mipmap level id 2928 } ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT; 2929 2930 /** 2931 **************************************************************************************************** 2932 * Addr2ComputeHtileCoordFromAddr 2933 * 2934 * @brief 2935 * Compute coordinates within depth buffer (1st pixel of a micro tile) according to 2936 * Htile address 2937 **************************************************************************************************** 2938 */ 2939 ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileCoordFromAddr( 2940 ADDR_HANDLE hLib, 2941 const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, 2942 ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut); 2943 2944 2945 2946 //////////////////////////////////////////////////////////////////////////////////////////////////// 2947 // C-mask functions for Gfx9 2948 //////////////////////////////////////////////////////////////////////////////////////////////////// 2949 2950 /** 2951 **************************************************************************************************** 2952 * ADDR2_COMPUTE_CMASK_INFO_INPUT 2953 * 2954 * @brief 2955 * Input structure of Addr2ComputeCmaskInfo 2956 **************************************************************************************************** 2957 */ 2958 typedef struct _ADDR2_COMPUTE_CMASKINFO_INPUT 2959 { 2960 UINT_32 size; ///< Size of this structure in bytes 2961 2962 ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags 2963 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags 2964 AddrResourceType resourceType; ///< Color surface type 2965 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 2966 UINT_32 unalignedWidth; ///< Color surface original width 2967 UINT_32 unalignedHeight; ///< Color surface original height 2968 UINT_32 numSlices; ///< Number of slices of color buffer 2969 UINT_32 numMipLevels; ///< Number of mip levels 2970 UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if no mip is in tail, 2971 /// it should be number of mip levels 2972 /// Only for GFX10 2973 } ADDR2_COMPUTE_CMASK_INFO_INPUT; 2974 2975 /* DCC addr meta equation for GFX9. */ 2976 struct gfx9_addr_meta_equation { 2977 UINT_8 num_bits; 2978 2979 struct { 2980 struct { 2981 UINT_8 dim; /* 0..4 as index, 5 means invalid */ 2982 UINT_8 ord; /* 0..31 */ 2983 } coord[8]; /* 0..num_coords */ 2984 } bit[32]; /* 0..num_bits */ 2985 2986 UINT_8 numPipeBits; 2987 }; 2988 2989 /** 2990 **************************************************************************************************** 2991 * ADDR2_COMPUTE_CMASK_INFO_OUTPUT 2992 * 2993 * @brief 2994 * Output structure of Addr2ComputeCmaskInfo 2995 **************************************************************************************************** 2996 */ 2997 typedef struct _ADDR2_COMPUTE_CMASK_INFO_OUTPUT 2998 { 2999 UINT_32 size; ///< Size of this structure in bytes 3000 3001 UINT_32 pitch; ///< Pitch in pixels of color buffer which 3002 /// this Cmask matches. The size might be larger than 3003 /// original color buffer pitch when called with 3004 /// an unaligned pitch. 3005 UINT_32 height; ///< Height in pixels, as above 3006 UINT_32 baseAlign; ///< Base alignment 3007 UINT_32 sliceSize; ///< Slice size, in bytes. 3008 UINT_32 cmaskBytes; ///< Size in bytes of CMask buffer 3009 UINT_32 metaBlkWidth; ///< Meta block width 3010 UINT_32 metaBlkHeight; ///< Meta block height 3011 3012 UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice 3013 3014 ADDR2_META_MIP_INFO* pMipInfo; ///< CMASK mip information 3015 3016 /* The equation for doing CMASK address computations in shaders. */ 3017 union { 3018 /* This is chip-specific, and it varies with: 3019 * - resource type 3020 * - swizzle_mode 3021 * - bpp 3022 * - pipe_aligned 3023 * - rb_aligned 3024 */ 3025 struct gfx9_addr_meta_equation gfx9; 3026 3027 /* This is chip-specific, it requires 64KB_Z_X. */ 3028 UINT_16 *gfx10_bits; /* 68 2-byte elements */ 3029 } equation; 3030 } ADDR2_COMPUTE_CMASK_INFO_OUTPUT; 3031 3032 /** 3033 **************************************************************************************************** 3034 * Addr2ComputeCmaskInfo 3035 * 3036 * @brief 3037 * Compute Cmask pitch, height, base alignment and size in bytes from color buffer 3038 * info 3039 **************************************************************************************************** 3040 */ 3041 ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskInfo( 3042 ADDR_HANDLE hLib, 3043 const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn, 3044 ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut); 3045 3046 3047 3048 /** 3049 **************************************************************************************************** 3050 * ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT 3051 * 3052 * @brief 3053 * Input structure for Addr2ComputeCmaskAddrFromCoord 3054 * 3055 **************************************************************************************************** 3056 */ 3057 typedef struct _ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT 3058 { 3059 UINT_32 size; ///< Size of this structure in bytes 3060 3061 UINT_32 x; ///< X coordinate 3062 UINT_32 y; ///< Y coordinate 3063 UINT_32 slice; ///< Index of slices 3064 3065 ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags 3066 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags 3067 AddrResourceType resourceType; ///< Color surface type 3068 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 3069 3070 UINT_32 unalignedWidth; ///< Color surface original width (of mip0) 3071 UINT_32 unalignedHeight; ///< Color surface original height (of mip0) 3072 UINT_32 numSlices; ///< Color surface original slices (of mip0) 3073 3074 UINT_32 numSamples; ///< Color surfae sample number 3075 UINT_32 numFrags; ///< Color surface fragment number 3076 3077 UINT_32 pipeXor; ///< pipe Xor setting 3078 } ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT; 3079 3080 /** 3081 **************************************************************************************************** 3082 * ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT 3083 * 3084 * @brief 3085 * Output structure for Addr2ComputeCmaskAddrFromCoord 3086 **************************************************************************************************** 3087 */ 3088 typedef struct _ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT 3089 { 3090 UINT_32 size; ///< Size of this structure in bytes 3091 3092 UINT_64 addr; ///< CMASK address in bytes 3093 UINT_32 bitPosition; ///< Bit position within addr, 0 or 4 3094 } ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT; 3095 3096 /** 3097 **************************************************************************************************** 3098 * Addr2ComputeCmaskAddrFromCoord 3099 * 3100 * @brief 3101 * Compute Cmask address according to coordinates (of MSAA color buffer) 3102 **************************************************************************************************** 3103 */ 3104 ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskAddrFromCoord( 3105 ADDR_HANDLE hLib, 3106 const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, 3107 ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut); 3108 3109 3110 3111 /** 3112 **************************************************************************************************** 3113 * ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT 3114 * 3115 * @brief 3116 * Input structure for Addr2ComputeCmaskCoordFromAddr 3117 **************************************************************************************************** 3118 */ 3119 typedef struct _ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT 3120 { 3121 UINT_32 size; ///< Size of this structure in bytes 3122 3123 UINT_64 addr; ///< CMASK address in bytes 3124 UINT_32 bitPosition; ///< Bit position within addr, 0 or 4 3125 3126 ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags 3127 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags 3128 AddrResourceType resourceType; ///< Color surface type 3129 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 3130 3131 UINT_32 unalignedWidth; ///< Color surface original width (of mip0) 3132 UINT_32 unalignedHeight; ///< Color surface original height (of mip0) 3133 UINT_32 numSlices; ///< Color surface original slices (of mip0) 3134 UINT_32 numMipLevels; ///< Color surface total mipmap levels. 3135 } ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT; 3136 3137 /** 3138 **************************************************************************************************** 3139 * ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT 3140 * 3141 * @brief 3142 * Output structure for Addr2ComputeCmaskCoordFromAddr 3143 **************************************************************************************************** 3144 */ 3145 typedef struct _ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT 3146 { 3147 UINT_32 size; ///< Size of this structure in bytes 3148 3149 UINT_32 x; ///< X coordinate 3150 UINT_32 y; ///< Y coordinate 3151 UINT_32 slice; ///< Index of slices 3152 UINT_32 mipId; ///< mipmap level id 3153 } ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT; 3154 3155 /** 3156 **************************************************************************************************** 3157 * Addr2ComputeCmaskCoordFromAddr 3158 * 3159 * @brief 3160 * Compute coordinates within color buffer (1st pixel of a micro tile) according to 3161 * Cmask address 3162 **************************************************************************************************** 3163 */ 3164 ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskCoordFromAddr( 3165 ADDR_HANDLE hLib, 3166 const ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn, 3167 ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut); 3168 3169 3170 3171 //////////////////////////////////////////////////////////////////////////////////////////////////// 3172 // F-mask functions for Gfx9 3173 //////////////////////////////////////////////////////////////////////////////////////////////////// 3174 3175 /** 3176 **************************************************************************************************** 3177 * ADDR2_FMASK_FLAGS 3178 * 3179 * @brief 3180 * FMASK flags 3181 **************************************************************************************************** 3182 */ 3183 typedef union _ADDR2_FMASK_FLAGS 3184 { 3185 struct 3186 { 3187 UINT_32 resolved : 1; ///< TRUE if this is a resolved fmask, used by H/W clients 3188 /// by H/W clients. S/W should always set it to FALSE. 3189 UINT_32 reserved : 31; ///< Reserved for future use. 3190 }; 3191 3192 UINT_32 value; 3193 } ADDR2_FMASK_FLAGS; 3194 3195 /** 3196 **************************************************************************************************** 3197 * ADDR2_COMPUTE_FMASK_INFO_INPUT 3198 * 3199 * @brief 3200 * Input structure for Addr2ComputeFmaskInfo 3201 **************************************************************************************************** 3202 */ 3203 typedef struct _ADDR2_COMPUTE_FMASK_INFO_INPUT 3204 { 3205 UINT_32 size; ///< Size of this structure in bytes 3206 3207 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 3208 UINT_32 unalignedWidth; ///< Color surface original width 3209 UINT_32 unalignedHeight; ///< Color surface original height 3210 UINT_32 numSlices; ///< Number of slices/depth 3211 UINT_32 numSamples; ///< Number of samples 3212 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 3213 /// number of samples for normal AA; Set it to the 3214 /// number of fragments for EQAA 3215 ADDR2_FMASK_FLAGS fMaskFlags; ///< FMASK flags 3216 } ADDR2_COMPUTE_FMASK_INFO_INPUT; 3217 3218 /** 3219 **************************************************************************************************** 3220 * ADDR2_COMPUTE_FMASK_INFO_OUTPUT 3221 * 3222 * @brief 3223 * Output structure for Addr2ComputeFmaskInfo 3224 **************************************************************************************************** 3225 */ 3226 typedef struct _ADDR2_COMPUTE_FMASK_INFO_OUTPUT 3227 { 3228 UINT_32 size; ///< Size of this structure in bytes 3229 3230 UINT_32 pitch; ///< Pitch of fmask in pixels 3231 UINT_32 height; ///< Height of fmask in pixels 3232 UINT_32 baseAlign; ///< Base alignment 3233 UINT_32 numSlices; ///< Slices of fmask 3234 UINT_32 fmaskBytes; ///< Size of fmask in bytes 3235 UINT_32 bpp; ///< Bits per pixel of FMASK is: number of bit planes 3236 UINT_32 numSamples; ///< Number of samples 3237 UINT_32 sliceSize; ///< Size of slice in bytes 3238 } ADDR2_COMPUTE_FMASK_INFO_OUTPUT; 3239 3240 /** 3241 **************************************************************************************************** 3242 * Addr2ComputeFmaskInfo 3243 * 3244 * @brief 3245 * Compute Fmask pitch/height/slices/alignments and size in bytes 3246 **************************************************************************************************** 3247 */ 3248 ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskInfo( 3249 ADDR_HANDLE hLib, 3250 const ADDR2_COMPUTE_FMASK_INFO_INPUT* pIn, 3251 ADDR2_COMPUTE_FMASK_INFO_OUTPUT* pOut); 3252 3253 3254 3255 /** 3256 **************************************************************************************************** 3257 * ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT 3258 * 3259 * @brief 3260 * Input structure for Addr2ComputeFmaskAddrFromCoord 3261 **************************************************************************************************** 3262 */ 3263 typedef struct _ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT 3264 { 3265 UINT_32 size; ///< Size of this structure in bytes 3266 3267 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 3268 UINT_32 x; ///< X coordinate 3269 UINT_32 y; ///< Y coordinate 3270 UINT_32 slice; ///< Slice index 3271 UINT_32 sample; ///< Sample index (fragment index for EQAA) 3272 UINT_32 plane; ///< Plane number 3273 3274 UINT_32 unalignedWidth; ///< Color surface original width 3275 UINT_32 unalignedHeight; ///< Color surface original height 3276 UINT_32 numSamples; ///< Number of samples 3277 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 3278 /// number of samples for normal AA; Set it to the 3279 /// number of fragments for EQAA 3280 UINT_32 tileSwizzle; ///< Combined swizzle used to do bank/pipe rotation 3281 3282 ADDR2_FMASK_FLAGS fMaskFlags; ///< FMASK flags 3283 } ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT; 3284 3285 /** 3286 **************************************************************************************************** 3287 * ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT 3288 * 3289 * @brief 3290 * Output structure for Addr2ComputeFmaskAddrFromCoord 3291 **************************************************************************************************** 3292 */ 3293 typedef struct _ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT 3294 { 3295 UINT_32 size; ///< Size of this structure in bytes 3296 3297 UINT_64 addr; ///< Fmask address 3298 UINT_32 bitPosition; ///< Bit position within fmaskAddr, 0-7. 3299 } ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT; 3300 3301 /** 3302 **************************************************************************************************** 3303 * Addr2ComputeFmaskAddrFromCoord 3304 * 3305 * @brief 3306 * Compute Fmask address according to coordinates (x,y,slice,sample,plane) 3307 **************************************************************************************************** 3308 */ 3309 ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskAddrFromCoord( 3310 ADDR_HANDLE hLib, 3311 const ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn, 3312 ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut); 3313 3314 3315 3316 /** 3317 **************************************************************************************************** 3318 * ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT 3319 * 3320 * @brief 3321 * Input structure for Addr2ComputeFmaskCoordFromAddr 3322 **************************************************************************************************** 3323 */ 3324 typedef struct _ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT 3325 { 3326 UINT_32 size; ///< Size of this structure in bytes 3327 3328 UINT_64 addr; ///< Address 3329 UINT_32 bitPosition; ///< Bit position within addr, 0-7. 3330 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 3331 3332 UINT_32 unalignedWidth; ///< Color surface original width 3333 UINT_32 unalignedHeight; ///< Color surface original height 3334 UINT_32 numSamples; ///< Number of samples 3335 UINT_32 numFrags; ///< Number of fragments 3336 3337 UINT_32 tileSwizzle; ///< Combined swizzle used to do bank/pipe rotation 3338 3339 ADDR2_FMASK_FLAGS fMaskFlags; ///< FMASK flags 3340 } ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT; 3341 3342 /** 3343 **************************************************************************************************** 3344 * ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT 3345 * 3346 * @brief 3347 * Output structure for Addr2ComputeFmaskCoordFromAddr 3348 **************************************************************************************************** 3349 */ 3350 typedef struct _ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT 3351 { 3352 UINT_32 size; ///< Size of this structure in bytes 3353 3354 UINT_32 x; ///< X coordinate 3355 UINT_32 y; ///< Y coordinate 3356 UINT_32 slice; ///< Slice index 3357 UINT_32 sample; ///< Sample index (fragment index for EQAA) 3358 UINT_32 plane; ///< Plane number 3359 } ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT; 3360 3361 /** 3362 **************************************************************************************************** 3363 * Addr2ComputeFmaskCoordFromAddr 3364 * 3365 * @brief 3366 * Compute FMASK coordinate from an given address 3367 **************************************************************************************************** 3368 */ 3369 ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskCoordFromAddr( 3370 ADDR_HANDLE hLib, 3371 const ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn, 3372 ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut); 3373 3374 3375 3376 //////////////////////////////////////////////////////////////////////////////////////////////////// 3377 // DCC key functions for Gfx9 3378 //////////////////////////////////////////////////////////////////////////////////////////////////// 3379 3380 /** 3381 **************************************************************************************************** 3382 * _ADDR2_COMPUTE_DCCINFO_INPUT 3383 * 3384 * @brief 3385 * Input structure of Addr2ComputeDccInfo 3386 **************************************************************************************************** 3387 */ 3388 typedef struct _ADDR2_COMPUTE_DCCINFO_INPUT 3389 { 3390 UINT_32 size; ///< Size of this structure in bytes 3391 3392 ADDR2_META_FLAGS dccKeyFlags; ///< DCC key flags 3393 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags 3394 AddrResourceType resourceType; ///< Color surface type 3395 AddrSwizzleMode swizzleMode; ///< Color surface swizzle mode 3396 UINT_32 bpp; ///< bits per pixel 3397 UINT_32 unalignedWidth; ///< Color surface original width (of mip0) 3398 UINT_32 unalignedHeight; ///< Color surface original height (of mip0) 3399 UINT_32 numSlices; ///< Number of slices, of color surface (of mip0) 3400 UINT_32 numFrags; ///< Fragment number of color surface 3401 UINT_32 numMipLevels; ///< Total mipmap levels of color surface 3402 UINT_32 dataSurfaceSize; ///< The padded size of all slices and mip levels 3403 ///< useful in meta linear case 3404 UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if no mip is in tail, 3405 /// it should be number of mip levels 3406 /// Only for GFX10 3407 } ADDR2_COMPUTE_DCCINFO_INPUT; 3408 3409 /** 3410 **************************************************************************************************** 3411 * ADDR2_COMPUTE_DCCINFO_OUTPUT 3412 * 3413 * @brief 3414 * Output structure of Addr2ComputeDccInfo 3415 **************************************************************************************************** 3416 */ 3417 typedef struct _ADDR2_COMPUTE_DCCINFO_OUTPUT 3418 { 3419 UINT_32 size; ///< Size of this structure in bytes 3420 3421 UINT_32 dccRamBaseAlign; ///< Base alignment of dcc key 3422 UINT_32 dccRamSize; ///< Size of dcc key 3423 3424 UINT_32 pitch; ///< DCC surface mip chain pitch 3425 UINT_32 height; ///< DCC surface mip chain height 3426 UINT_32 depth; ///< DCC surface mip chain depth 3427 3428 UINT_32 compressBlkWidth; ///< DCC compress block width 3429 UINT_32 compressBlkHeight; ///< DCC compress block height 3430 UINT_32 compressBlkDepth; ///< DCC compress block depth 3431 3432 UINT_32 metaBlkWidth; ///< DCC meta block width 3433 UINT_32 metaBlkHeight; ///< DCC meta block height 3434 UINT_32 metaBlkDepth; ///< DCC meta block depth 3435 UINT_32 metaBlkSize; ///< DCC meta block size in bytes 3436 UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice 3437 3438 union 3439 { 3440 UINT_32 fastClearSizePerSlice; ///< Size of DCC within a slice should be fast cleared 3441 UINT_32 dccRamSliceSize; ///< DCC ram size per slice. For mipmap, it's 3442 /// the slize size of a mip chain, the thickness of a 3443 /// a slice is meta block depth 3444 /// Only for GFX10 3445 }; 3446 3447 ADDR2_META_MIP_INFO* pMipInfo; ///< DCC mip information 3448 3449 /* The equation for doing DCC address computations in shaders. */ 3450 union { 3451 /* This is chip-specific, and it varies with: 3452 * - resource type 3453 * - swizzle_mode 3454 * - bpp 3455 * - number of fragments 3456 * - pipe_aligned 3457 * - rb_aligned 3458 */ 3459 struct gfx9_addr_meta_equation gfx9; 3460 3461 /* This is chip-specific, it requires 64KB_R_X, and it varies with: 3462 * - bpp 3463 * - pipe_aligned 3464 */ 3465 UINT_16 *gfx10_bits; /* 68 2-byte elements */ 3466 } equation; 3467 } ADDR2_COMPUTE_DCCINFO_OUTPUT; 3468 3469 /** 3470 **************************************************************************************************** 3471 * Addr2ComputeDccInfo 3472 * 3473 * @brief 3474 * Compute DCC key size, base alignment 3475 * info 3476 **************************************************************************************************** 3477 */ 3478 ADDR_E_RETURNCODE ADDR_API Addr2ComputeDccInfo( 3479 ADDR_HANDLE hLib, 3480 const ADDR2_COMPUTE_DCCINFO_INPUT* pIn, 3481 ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut); 3482 3483 3484 /** 3485 **************************************************************************************************** 3486 * ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT 3487 * 3488 * @brief 3489 * Input structure for Addr2ComputeDccAddrFromCoord 3490 * 3491 **************************************************************************************************** 3492 */ 3493 typedef struct _ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT 3494 { 3495 UINT_32 size; ///< Size of this structure in bytes 3496 3497 UINT_32 x; ///< X coordinate 3498 UINT_32 y; ///< Y coordinate 3499 UINT_32 slice; ///< Index of slices 3500 UINT_32 sample; ///< Index of samples, means fragment index for EQAA 3501 UINT_32 mipId; ///< mipmap level id 3502 3503 ADDR2_META_FLAGS dccKeyFlags; ///< DCC flags 3504 ADDR2_SURFACE_FLAGS colorFlags; ///< Color surface flags 3505 AddrResourceType resourceType; ///< Color surface type 3506 AddrSwizzleMode swizzleMode; ///< Color surface swizzle mode 3507 UINT_32 bpp; ///< Color surface bits per pixel 3508 UINT_32 unalignedWidth; ///< Color surface original width (of mip0) 3509 UINT_32 unalignedHeight; ///< Color surface original height (of mip0) 3510 UINT_32 numSlices; ///< Color surface original slices (of mip0) 3511 UINT_32 numMipLevels; ///< Color surface mipmap levels 3512 UINT_32 numFrags; ///< Color surface fragment number 3513 3514 UINT_32 pipeXor; ///< pipe Xor setting 3515 UINT_32 pitch; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::pitch 3516 UINT_32 height; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::height 3517 UINT_32 compressBlkWidth; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::compressBlkWidth 3518 UINT_32 compressBlkHeight; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::compressBlkHeight 3519 UINT_32 compressBlkDepth; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::compressBlkDepth 3520 UINT_32 metaBlkWidth; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::metaBlkWidth 3521 UINT_32 metaBlkHeight; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::metaBlkHeight 3522 UINT_32 metaBlkDepth; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::metaBlkDepth 3523 UINT_32 dccRamSliceSize; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::dccRamSliceSize 3524 } ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT; 3525 3526 /** 3527 **************************************************************************************************** 3528 * ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT 3529 * 3530 * @brief 3531 * Output structure for Addr2ComputeDccAddrFromCoord 3532 **************************************************************************************************** 3533 */ 3534 typedef struct _ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT 3535 { 3536 UINT_32 size; ///< Size of this structure in bytes 3537 3538 UINT_64 addr; ///< DCC address in bytes 3539 } ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT; 3540 3541 /** 3542 **************************************************************************************************** 3543 * Addr2ComputeDccAddrFromCoord 3544 * 3545 * @brief 3546 * Compute DCC address according to coordinates (of MSAA color buffer) 3547 **************************************************************************************************** 3548 */ 3549 ADDR_E_RETURNCODE ADDR_API Addr2ComputeDccAddrFromCoord( 3550 ADDR_HANDLE hLib, 3551 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn, 3552 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut); 3553 3554 //////////////////////////////////////////////////////////////////////////////////////////////////// 3555 // Misc functions for Gfx9 3556 //////////////////////////////////////////////////////////////////////////////////////////////////// 3557 3558 /** 3559 **************************************************************************************************** 3560 * ADDR2_COMPUTE_PIPEBANKXOR_INPUT 3561 * 3562 * @brief 3563 * Input structure of Addr2ComputePipebankXor 3564 **************************************************************************************************** 3565 */ 3566 typedef struct _ADDR2_COMPUTE_PIPEBANKXOR_INPUT 3567 { 3568 UINT_32 size; ///< Size of this structure in bytes 3569 UINT_32 surfIndex; ///< Input surface index 3570 ADDR2_SURFACE_FLAGS flags; ///< Surface flag 3571 AddrSwizzleMode swizzleMode; ///< Surface swizzle mode 3572 AddrResourceType resourceType; ///< Surface resource type 3573 AddrFormat format; ///< Surface format 3574 UINT_32 numSamples; ///< Number of samples 3575 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 3576 /// number of samples for normal AA; Set it to the 3577 /// number of fragments for EQAA 3578 } ADDR2_COMPUTE_PIPEBANKXOR_INPUT; 3579 3580 /** 3581 **************************************************************************************************** 3582 * ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT 3583 * 3584 * @brief 3585 * Output structure of Addr2ComputePipebankXor 3586 **************************************************************************************************** 3587 */ 3588 typedef struct _ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT 3589 { 3590 UINT_32 size; ///< Size of this structure in bytes 3591 UINT_32 pipeBankXor; ///< Pipe bank xor 3592 } ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT; 3593 3594 /** 3595 **************************************************************************************************** 3596 * Addr2ComputePipeBankXor 3597 * 3598 * @brief 3599 * Calculate a valid bank pipe xor value for client to use. 3600 **************************************************************************************************** 3601 */ 3602 ADDR_E_RETURNCODE ADDR_API Addr2ComputePipeBankXor( 3603 ADDR_HANDLE hLib, 3604 const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn, 3605 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut); 3606 3607 /** 3608 **************************************************************************************************** 3609 * ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT 3610 * 3611 * @brief 3612 * Input structure of Addr2ComputeSlicePipeBankXor 3613 **************************************************************************************************** 3614 */ 3615 typedef struct _ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT 3616 { 3617 UINT_32 size; ///< Size of this structure in bytes 3618 AddrSwizzleMode swizzleMode; ///< Surface swizzle mode 3619 AddrResourceType resourceType; ///< Surface resource type 3620 UINT_32 bpe; ///< bits per element (e.g. block size for BCn format) 3621 UINT_32 basePipeBankXor; ///< Base pipe bank xor 3622 UINT_32 slice; ///< Slice id 3623 UINT_32 numSamples; ///< Number of samples 3624 } ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT; 3625 3626 /** 3627 **************************************************************************************************** 3628 * ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT 3629 * 3630 * @brief 3631 * Output structure of Addr2ComputeSlicePipeBankXor 3632 **************************************************************************************************** 3633 */ 3634 typedef struct _ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT 3635 { 3636 UINT_32 size; ///< Size of this structure in bytes 3637 UINT_32 pipeBankXor; ///< Pipe bank xor 3638 } ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT; 3639 3640 /** 3641 **************************************************************************************************** 3642 * Addr2ComputeSlicePipeBankXor 3643 * 3644 * @brief 3645 * Calculate slice pipe bank xor value based on base pipe bank xor and slice id. 3646 **************************************************************************************************** 3647 */ 3648 ADDR_E_RETURNCODE ADDR_API Addr2ComputeSlicePipeBankXor( 3649 ADDR_HANDLE hLib, 3650 const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn, 3651 ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut); 3652 3653 /** 3654 **************************************************************************************************** 3655 * ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT 3656 * 3657 * @brief 3658 * Input structure of Addr2ComputeSubResourceOffsetForSwizzlePattern 3659 **************************************************************************************************** 3660 */ 3661 typedef struct _ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT 3662 { 3663 UINT_32 size; ///< Size of this structure in bytes 3664 AddrSwizzleMode swizzleMode; ///< Surface swizzle mode 3665 AddrResourceType resourceType; ///< Surface resource type 3666 UINT_32 pipeBankXor; ///< Per resource xor 3667 UINT_32 slice; ///< Slice id 3668 UINT_64 sliceSize; ///< Slice size of a mip chain 3669 UINT_64 macroBlockOffset; ///< Macro block offset, returned in ADDR2_MIP_INFO 3670 UINT_32 mipTailOffset; ///< Mip tail offset, returned in ADDR2_MIP_INFO 3671 } ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT; 3672 3673 /** 3674 **************************************************************************************************** 3675 * ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT 3676 * 3677 * @brief 3678 * Output structure of Addr2ComputeSubResourceOffsetForSwizzlePattern 3679 **************************************************************************************************** 3680 */ 3681 typedef struct _ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT 3682 { 3683 UINT_32 size; ///< Size of this structure in bytes 3684 UINT_64 offset; ///< offset 3685 } ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT; 3686 3687 /** 3688 **************************************************************************************************** 3689 * Addr2ComputeSubResourceOffsetForSwizzlePattern 3690 * 3691 * @brief 3692 * Calculate sub resource offset to support swizzle pattern. 3693 **************************************************************************************************** 3694 */ 3695 ADDR_E_RETURNCODE ADDR_API Addr2ComputeSubResourceOffsetForSwizzlePattern( 3696 ADDR_HANDLE hLib, 3697 const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn, 3698 ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut); 3699 3700 /** 3701 **************************************************************************************************** 3702 * ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT 3703 * 3704 * @brief 3705 * Input structure of Addr2ComputeNonBlockCompressedView 3706 **************************************************************************************************** 3707 */ 3708 typedef struct _ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT 3709 { 3710 UINT_32 size; ///< Size of this structure in bytes 3711 ADDR2_SURFACE_FLAGS flags; ///< Surface flags 3712 AddrSwizzleMode swizzleMode; ///< Swizzle Mode for Gfx9 3713 AddrResourceType resourceType; ///< Surface type 3714 AddrFormat format; ///< Surface format 3715 UINT_32 width; ///< Width of mip0 in texels (not in compressed block) 3716 UINT_32 height; ///< Height of mip0 in texels (not in compressed block) 3717 UINT_32 numSlices; ///< Number surface slice/depth of mip0 3718 UINT_32 numMipLevels; ///< Total mipmap levels. 3719 UINT_32 pipeBankXor; ///< Combined swizzle used to do bank/pipe rotation 3720 UINT_32 slice; ///< Index of slice to view 3721 UINT_32 mipId; ///< Id of mip to view 3722 } ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT; 3723 3724 /** 3725 **************************************************************************************************** 3726 * ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT 3727 * 3728 * @brief 3729 * Output structure of Addr2ComputeNonBlockCompressedView 3730 **************************************************************************************************** 3731 */ 3732 typedef struct _ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT 3733 { 3734 UINT_32 size; ///< Size of this structure in bytes 3735 UINT_64 offset; ///< Offset shifted from resource base for the view 3736 UINT_32 pipeBankXor; ///< Pipe bank xor for the view 3737 UINT_32 unalignedWidth; ///< Mip0 width (in element) for the view 3738 UINT_32 unalignedHeight; ///< Mip0 height (in element) for the view 3739 UINT_32 numMipLevels; ///< Total mipmap levels for the view 3740 UINT_32 mipId; ///< Mip ID for the view 3741 } ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT; 3742 3743 /** 3744 **************************************************************************************************** 3745 * Addr2ComputeNonBlockCompressedView 3746 * 3747 * @brief 3748 * Compute non-block-compressed view for a given mipmap level/slice 3749 **************************************************************************************************** 3750 */ 3751 ADDR_E_RETURNCODE ADDR_API Addr2ComputeNonBlockCompressedView( 3752 ADDR_HANDLE hLib, 3753 const ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT* pIn, 3754 ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT* pOut); 3755 3756 /** 3757 **************************************************************************************************** 3758 * ADDR2_BLOCK_SET 3759 * 3760 * @brief 3761 * Bit field that defines block type 3762 **************************************************************************************************** 3763 */ 3764 typedef union _ADDR2_BLOCK_SET 3765 { 3766 struct 3767 { 3768 UINT_32 micro : 1; // 256B block for 2D resource 3769 UINT_32 macroThin4KB : 1; // Thin 4KB for 2D/3D resource 3770 UINT_32 macroThick4KB : 1; // Thick 4KB for 3D resource 3771 UINT_32 macroThin64KB : 1; // Thin 64KB for 2D/3D resource 3772 UINT_32 macroThick64KB : 1; // Thick 64KB for 3D resource 3773 UINT_32 var : 1; // VAR block 3774 UINT_32 : 1; 3775 UINT_32 linear : 1; // Linear block 3776 UINT_32 reserved : 24; 3777 }; 3778 3779 struct 3780 { 3781 UINT_32 : 5; 3782 UINT_32 thin256KB : 1; // Thin 256KB block 3783 UINT_32 thick256KB : 1; // Thick 256KB block 3784 UINT_32 : 25; 3785 } gfx11; 3786 3787 UINT_32 value; 3788 } ADDR2_BLOCK_SET; 3789 3790 /** 3791 **************************************************************************************************** 3792 * ADDR2_SWTYPE_SET 3793 * 3794 * @brief 3795 * Bit field that defines swizzle type 3796 **************************************************************************************************** 3797 */ 3798 typedef union _ADDR2_SWTYPE_SET 3799 { 3800 struct 3801 { 3802 UINT_32 sw_Z : 1; // SW_*_Z_* 3803 UINT_32 sw_S : 1; // SW_*_S_* 3804 UINT_32 sw_D : 1; // SW_*_D_* 3805 UINT_32 sw_R : 1; // SW_*_R_* 3806 UINT_32 reserved : 28; 3807 }; 3808 3809 UINT_32 value; 3810 } ADDR2_SWTYPE_SET; 3811 3812 /** 3813 **************************************************************************************************** 3814 * ADDR2_SWMODE_SET 3815 * 3816 * @brief 3817 * Bit field that defines swizzle type 3818 **************************************************************************************************** 3819 */ 3820 typedef union _ADDR2_SWMODE_SET 3821 { 3822 struct 3823 { 3824 UINT_32 swLinear : 1; 3825 UINT_32 sw256B_S : 1; 3826 UINT_32 sw256B_D : 1; 3827 UINT_32 sw256B_R : 1; 3828 UINT_32 sw4KB_Z : 1; 3829 UINT_32 sw4KB_S : 1; 3830 UINT_32 sw4KB_D : 1; 3831 UINT_32 sw4KB_R : 1; 3832 UINT_32 sw64KB_Z : 1; 3833 UINT_32 sw64KB_S : 1; 3834 UINT_32 sw64KB_D : 1; 3835 UINT_32 sw64KB_R : 1; 3836 UINT_32 swMiscDef12 : 1; 3837 UINT_32 swMiscDef13 : 1; 3838 UINT_32 swMiscDef14 : 1; 3839 UINT_32 swMiscDef15 : 1; 3840 UINT_32 sw64KB_Z_T : 1; 3841 UINT_32 sw64KB_S_T : 1; 3842 UINT_32 sw64KB_D_T : 1; 3843 UINT_32 sw64KB_R_T : 1; 3844 UINT_32 sw4KB_Z_X : 1; 3845 UINT_32 sw4KB_S_X : 1; 3846 UINT_32 sw4KB_D_X : 1; 3847 UINT_32 sw4KB_R_X : 1; 3848 UINT_32 sw64KB_Z_X : 1; 3849 UINT_32 sw64KB_S_X : 1; 3850 UINT_32 sw64KB_D_X : 1; 3851 UINT_32 sw64KB_R_X : 1; 3852 UINT_32 swMiscDef28 : 1; 3853 UINT_32 swMiscDef29 : 1; 3854 UINT_32 swMiscDef30 : 1; 3855 UINT_32 swMiscDef31 : 1; 3856 }; 3857 3858 struct 3859 { 3860 UINT_32 : 28; 3861 UINT_32 swVar_Z_X : 1; 3862 UINT_32 : 2; 3863 UINT_32 swVar_R_X : 1; 3864 } gfx10; 3865 3866 struct 3867 { 3868 UINT_32 : 28; 3869 UINT_32 sw256KB_Z_X : 1; 3870 UINT_32 sw256KB_S_X : 1; 3871 UINT_32 sw256KB_D_X : 1; 3872 UINT_32 sw256KB_R_X : 1; 3873 } gfx11; 3874 3875 UINT_32 value; 3876 } ADDR2_SWMODE_SET; 3877 3878 /** 3879 **************************************************************************************************** 3880 * ADDR2_GET_PREFERRED_SURF_SETTING_INPUT 3881 * 3882 * @brief 3883 * Input structure of Addr2GetPreferredSurfaceSetting 3884 **************************************************************************************************** 3885 */ 3886 typedef struct _ADDR2_GET_PREFERRED_SURF_SETTING_INPUT 3887 { 3888 UINT_32 size; ///< Size of this structure in bytes 3889 3890 ADDR2_SURFACE_FLAGS flags; ///< Surface flags 3891 AddrResourceType resourceType; ///< Surface type 3892 AddrFormat format; ///< Surface format 3893 AddrResrouceLocation resourceLoction; ///< Surface heap choice 3894 ADDR2_BLOCK_SET forbiddenBlock; ///< Client can use it to disable some block setting 3895 ///< such as linear for DXTn, tiled for YUV 3896 ADDR2_SWTYPE_SET preferredSwSet; ///< Client can use it to specify sw type(s) wanted 3897 BOOL_32 noXor; ///< Do not use xor mode for this resource 3898 UINT_32 bpp; ///< bits per pixel 3899 UINT_32 width; ///< Width (of mip0), in pixels 3900 UINT_32 height; ///< Height (of mip0), in pixels 3901 UINT_32 numSlices; ///< Number surface slice/depth (of mip0), 3902 UINT_32 numMipLevels; ///< Total mipmap levels. 3903 UINT_32 numSamples; ///< Number of samples 3904 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 3905 /// number of samples for normal AA; Set it to the 3906 /// number of fragments for EQAA 3907 UINT_32 maxAlign; ///< maximum base/size alignment requested by client 3908 UINT_32 minSizeAlign; ///< memory allocated for surface in client driver will 3909 /// be padded to multiple of this value (in bytes) 3910 DOUBLE memoryBudget; ///< Memory consumption ratio based on minimum possible 3911 /// size. 3912 } ADDR2_GET_PREFERRED_SURF_SETTING_INPUT; 3913 3914 /** 3915 **************************************************************************************************** 3916 * ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT 3917 * 3918 * @brief 3919 * Output structure of Addr2GetPreferredSurfaceSetting 3920 **************************************************************************************************** 3921 */ 3922 typedef struct _ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT 3923 { 3924 UINT_32 size; ///< Size of this structure in bytes 3925 3926 AddrSwizzleMode swizzleMode; ///< Suggested swizzle mode to be used 3927 AddrResourceType resourceType; ///< Suggested resource type to program HW 3928 ADDR2_BLOCK_SET validBlockSet; ///< Valid block type bit conbination 3929 BOOL_32 canXor; ///< If client can use xor on a valid macro block 3930 /// type 3931 ADDR2_SWTYPE_SET validSwTypeSet; ///< Valid swizzle type bit combination 3932 ADDR2_SWTYPE_SET clientPreferredSwSet; ///< Client-preferred swizzle type bit combination 3933 ADDR2_SWMODE_SET validSwModeSet; ///< Valid swizzle mode bit combination 3934 } ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT; 3935 3936 /** 3937 **************************************************************************************************** 3938 * Addr2GetPreferredSurfaceSetting 3939 * 3940 * @brief 3941 * Suggest a preferred setting for client driver to program HW register 3942 **************************************************************************************************** 3943 */ 3944 ADDR_E_RETURNCODE ADDR_API Addr2GetPreferredSurfaceSetting( 3945 ADDR_HANDLE hLib, 3946 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn, 3947 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut); 3948 3949 /** 3950 **************************************************************************************************** 3951 * Addr2GetPossibleSwizzleModes 3952 * 3953 * @brief 3954 * Returns a list of swizzle modes that are valid from the hardware's perspective for the 3955 * client to choose from 3956 **************************************************************************************************** 3957 */ 3958 ADDR_E_RETURNCODE ADDR_API Addr2GetPossibleSwizzleModes( 3959 ADDR_HANDLE hLib, 3960 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn, 3961 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut); 3962 3963 /** 3964 **************************************************************************************************** 3965 * Addr2IsValidDisplaySwizzleMode 3966 * 3967 * @brief 3968 * Return whether the swizzle mode is supported by display engine 3969 **************************************************************************************************** 3970 */ 3971 ADDR_E_RETURNCODE ADDR_API Addr2IsValidDisplaySwizzleMode( 3972 ADDR_HANDLE hLib, 3973 AddrSwizzleMode swizzleMode, 3974 UINT_32 bpp, 3975 BOOL_32 *pResult); 3976 3977 /** 3978 **************************************************************************************************** 3979 * Addr2GetAllowedBlockSet 3980 * 3981 * @brief 3982 * Returns the set of allowed block sizes given the allowed swizzle modes and resource type 3983 **************************************************************************************************** 3984 */ 3985 ADDR_E_RETURNCODE ADDR_API Addr2GetAllowedBlockSet( 3986 ADDR_HANDLE hLib, 3987 ADDR2_SWMODE_SET allowedSwModeSet, 3988 AddrResourceType rsrcType, 3989 ADDR2_BLOCK_SET* pAllowedBlockSet); 3990 3991 /** 3992 **************************************************************************************************** 3993 * Addr2GetAllowedSwSet 3994 * 3995 * @brief 3996 * Returns the set of allowed swizzle types given the allowed swizzle modes 3997 **************************************************************************************************** 3998 */ 3999 ADDR_E_RETURNCODE ADDR_API Addr2GetAllowedSwSet( 4000 ADDR_HANDLE hLib, 4001 ADDR2_SWMODE_SET allowedSwModeSet, 4002 ADDR2_SWTYPE_SET* pAllowedSwSet); 4003 4004 /** 4005 **************************************************************************************************** 4006 * Addr2IsBlockTypeAvailable 4007 * 4008 * @brief 4009 * Determine whether a block type is allowed in a given blockSet 4010 **************************************************************************************************** 4011 */ 4012 BOOL_32 Addr2IsBlockTypeAvailable(ADDR2_BLOCK_SET blockSet, AddrBlockType blockType); 4013 4014 /** 4015 **************************************************************************************************** 4016 * Addr2BlockTypeWithinMemoryBudget 4017 * 4018 * @brief 4019 * Determine whether a new block type is acceptable based on memory waste ratio. Will favor 4020 * larger block types. 4021 **************************************************************************************************** 4022 */ 4023 BOOL_32 Addr2BlockTypeWithinMemoryBudget( 4024 UINT_64 minSize, 4025 UINT_64 newBlockTypeSize, 4026 UINT_32 ratioLow, 4027 UINT_32 ratioHi, 4028 #if defined(__cplusplus) 4029 DOUBLE memoryBudget = 0.0f, 4030 BOOL_32 newBlockTypeBigger = TRUE); 4031 #else 4032 DOUBLE memoryBudget, 4033 BOOL_32 newBlockTypeBigger); 4034 #endif 4035 4036 #if defined(__cplusplus) 4037 } 4038 #endif 4039 4040 #endif // __ADDR_INTERFACE_H__ 4041