1 /*
2 * Copyright © 2016 Broadcom
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #ifndef V3D_COMPILER_H
25 #define V3D_COMPILER_H
26
27 #include <assert.h>
28 #include <stdio.h>
29 #include <stdlib.h>
30 #include <stdbool.h>
31 #include <stdint.h>
32 #include <string.h>
33
34 #include "util/blend.h"
35 #include "util/macros.h"
36 #include "common/v3d_debug.h"
37 #include "common/v3d_device_info.h"
38 #include "common/v3d_limits.h"
39 #include "compiler/nir/nir.h"
40 #include "util/list.h"
41 #include "util/u_math.h"
42
43 #include "qpu/qpu_instr.h"
44
45 /**
46 * Maximum number of outstanding TMU operations we can queue for execution.
47 *
48 * This is mostly limited by the size of the TMU fifos. The Input and Config
49 * fifos can stall, but we prefer that than injecting TMU flushes manually
50 * in the driver, so we can ignore these, but we can't overflow the Output fifo,
51 * which has 16 / threads per-thread entries, meaning that the maximum number
52 * of outstanding LDTMUs we can ever have is 8, for a 2-way threaded shader.
53 * This means that at most we can have 8 outstanding TMU loads, if each load
54 * is just one component.
55 *
56 * NOTE: we could actually have a larger value here because TMU stores don't
57 * consume any entries in the Output fifo (so we could have any number of
58 * outstanding stores) and the driver keeps track of used Output fifo entries
59 * and will flush if we ever needs more than 8, but since loads are much more
60 * common than stores, it is probably not worth it.
61 */
62 #define MAX_TMU_QUEUE_SIZE 8
63
64 /**
65 * Maximum offset distance in bytes between two consecutive constant UBO loads
66 * for the same UBO where we would favor updating the unifa address by emitting
67 * dummy ldunifa instructions to avoid writing the unifa register.
68 */
69 #define MAX_UNIFA_SKIP_DISTANCE 16
70
71 struct nir_builder;
72
73 struct v3d_fs_inputs {
74 /**
75 * Array of the meanings of the VPM inputs this shader needs.
76 *
77 * It doesn't include those that aren't part of the VPM, like
78 * point/line coordinates.
79 */
80 struct v3d_varying_slot *input_slots;
81 uint32_t num_inputs;
82 };
83
84 enum qfile {
85 /** An unused source or destination register. */
86 QFILE_NULL,
87
88 /** A physical register, such as the W coordinate payload. */
89 QFILE_REG,
90 /** One of the registers for fixed function interactions. */
91 QFILE_MAGIC,
92
93 /**
94 * A virtual register, that will be allocated to actual accumulator
95 * or physical registers later.
96 */
97 QFILE_TEMP,
98
99 /**
100 * Stores an immediate value in the index field that will be used
101 * directly by qpu_load_imm().
102 */
103 QFILE_LOAD_IMM,
104
105 /**
106 * Stores an immediate value in the index field that can be turned
107 * into a small immediate field by qpu_encode_small_immediate().
108 */
109 QFILE_SMALL_IMM,
110 };
111
112 /**
113 * A reference to a QPU register or a virtual temp register.
114 */
115 struct qreg {
116 enum qfile file;
117 uint32_t index;
118 };
119
vir_reg(enum qfile file,uint32_t index)120 static inline struct qreg vir_reg(enum qfile file, uint32_t index)
121 {
122 return (struct qreg){file, index};
123 }
124
vir_magic_reg(uint32_t index)125 static inline struct qreg vir_magic_reg(uint32_t index)
126 {
127 return (struct qreg){QFILE_MAGIC, index};
128 }
129
vir_nop_reg(void)130 static inline struct qreg vir_nop_reg(void)
131 {
132 return (struct qreg){QFILE_NULL, 0};
133 }
134
135 /**
136 * A reference to an actual register at the QPU level, for register
137 * allocation.
138 */
139 struct qpu_reg {
140 bool magic;
141 bool smimm;
142 int index;
143 };
144
145 struct qinst {
146 /** Entry in qblock->instructions */
147 struct list_head link;
148
149 /**
150 * The instruction being wrapped. Its condition codes, pack flags,
151 * signals, etc. will all be used, with just the register references
152 * being replaced by the contents of qinst->dst and qinst->src[].
153 */
154 struct v3d_qpu_instr qpu;
155
156 /* Pre-register-allocation references to src/dst registers */
157 struct qreg dst;
158 struct qreg src[3];
159 bool is_last_thrsw;
160
161 /* If the instruction reads a uniform (other than through src[i].file
162 * == QFILE_UNIF), that uniform's index in c->uniform_contents. ~0
163 * otherwise.
164 */
165 int uniform;
166
167 /* If this is a a TLB Z write */
168 bool is_tlb_z_write;
169
170 /* If this is a retiring TMU instruction (the last in a lookup sequence),
171 * how many ldtmu instructions are required to read the results.
172 */
173 uint32_t ldtmu_count;
174
175 /* Position of this instruction in the program. Filled in during
176 * register allocation.
177 */
178 int32_t ip;
179 };
180
181 enum quniform_contents {
182 /**
183 * Indicates that a constant 32-bit value is copied from the program's
184 * uniform contents.
185 */
186 QUNIFORM_CONSTANT,
187 /**
188 * Indicates that the program's uniform contents are used as an index
189 * into the GL uniform storage.
190 */
191 QUNIFORM_UNIFORM,
192
193 /** @{
194 * Scaling factors from clip coordinates to relative to the viewport
195 * center.
196 *
197 * This is used by the coordinate and vertex shaders to produce the
198 * 32-bit entry consisting of 2 16-bit fields with 12.4 signed fixed
199 * point offsets from the viewport ccenter.
200 */
201 QUNIFORM_VIEWPORT_X_SCALE,
202 QUNIFORM_VIEWPORT_Y_SCALE,
203 /** @} */
204
205 QUNIFORM_VIEWPORT_Z_OFFSET,
206 QUNIFORM_VIEWPORT_Z_SCALE,
207
208 QUNIFORM_USER_CLIP_PLANE,
209
210 /**
211 * A reference to a V3D 3.x texture config parameter 0 uniform.
212 *
213 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
214 * defines texture type, miplevels, and such. It will be found as a
215 * parameter to the first QOP_TEX_[STRB] instruction in a sequence.
216 */
217 QUNIFORM_TEXTURE_CONFIG_P0_0,
218 QUNIFORM_TEXTURE_CONFIG_P0_1,
219 QUNIFORM_TEXTURE_CONFIG_P0_2,
220 QUNIFORM_TEXTURE_CONFIG_P0_3,
221 QUNIFORM_TEXTURE_CONFIG_P0_4,
222 QUNIFORM_TEXTURE_CONFIG_P0_5,
223 QUNIFORM_TEXTURE_CONFIG_P0_6,
224 QUNIFORM_TEXTURE_CONFIG_P0_7,
225 QUNIFORM_TEXTURE_CONFIG_P0_8,
226 QUNIFORM_TEXTURE_CONFIG_P0_9,
227 QUNIFORM_TEXTURE_CONFIG_P0_10,
228 QUNIFORM_TEXTURE_CONFIG_P0_11,
229 QUNIFORM_TEXTURE_CONFIG_P0_12,
230 QUNIFORM_TEXTURE_CONFIG_P0_13,
231 QUNIFORM_TEXTURE_CONFIG_P0_14,
232 QUNIFORM_TEXTURE_CONFIG_P0_15,
233 QUNIFORM_TEXTURE_CONFIG_P0_16,
234 QUNIFORM_TEXTURE_CONFIG_P0_17,
235 QUNIFORM_TEXTURE_CONFIG_P0_18,
236 QUNIFORM_TEXTURE_CONFIG_P0_19,
237 QUNIFORM_TEXTURE_CONFIG_P0_20,
238 QUNIFORM_TEXTURE_CONFIG_P0_21,
239 QUNIFORM_TEXTURE_CONFIG_P0_22,
240 QUNIFORM_TEXTURE_CONFIG_P0_23,
241 QUNIFORM_TEXTURE_CONFIG_P0_24,
242 QUNIFORM_TEXTURE_CONFIG_P0_25,
243 QUNIFORM_TEXTURE_CONFIG_P0_26,
244 QUNIFORM_TEXTURE_CONFIG_P0_27,
245 QUNIFORM_TEXTURE_CONFIG_P0_28,
246 QUNIFORM_TEXTURE_CONFIG_P0_29,
247 QUNIFORM_TEXTURE_CONFIG_P0_30,
248 QUNIFORM_TEXTURE_CONFIG_P0_31,
249 QUNIFORM_TEXTURE_CONFIG_P0_32,
250
251 /**
252 * A reference to a V3D 3.x texture config parameter 1 uniform.
253 *
254 * This is a uniform implicitly loaded with a QPU_W_TMU* write, which
255 * has the pointer to the indirect texture state. Our data[] field
256 * will have a packed p1 value, but the address field will be just
257 * which texture unit's texture should be referenced.
258 */
259 QUNIFORM_TEXTURE_CONFIG_P1,
260
261 /* A V3D 4.x texture config parameter. The high 8 bits will be
262 * which texture or sampler is being sampled, and the driver must
263 * replace the address field with the appropriate address.
264 */
265 QUNIFORM_TMU_CONFIG_P0,
266 QUNIFORM_TMU_CONFIG_P1,
267
268 QUNIFORM_IMAGE_TMU_CONFIG_P0,
269
270 QUNIFORM_TEXTURE_FIRST_LEVEL,
271
272 QUNIFORM_TEXTURE_WIDTH,
273 QUNIFORM_TEXTURE_HEIGHT,
274 QUNIFORM_TEXTURE_DEPTH,
275 QUNIFORM_TEXTURE_ARRAY_SIZE,
276 QUNIFORM_TEXTURE_LEVELS,
277 QUNIFORM_TEXTURE_SAMPLES,
278
279 QUNIFORM_UBO_ADDR,
280
281 QUNIFORM_TEXRECT_SCALE_X,
282 QUNIFORM_TEXRECT_SCALE_Y,
283
284 /* Returns the base offset of the SSBO given by the data value. */
285 QUNIFORM_SSBO_OFFSET,
286
287 /* Returns the size of the SSBO or UBO given by the data value. */
288 QUNIFORM_GET_SSBO_SIZE,
289 QUNIFORM_GET_UBO_SIZE,
290
291 /* Sizes (in pixels) of a shader image given by the data value. */
292 QUNIFORM_IMAGE_WIDTH,
293 QUNIFORM_IMAGE_HEIGHT,
294 QUNIFORM_IMAGE_DEPTH,
295 QUNIFORM_IMAGE_ARRAY_SIZE,
296
297 QUNIFORM_LINE_WIDTH,
298
299 /* The line width sent to hardware. This includes the expanded width
300 * when anti-aliasing is enabled.
301 */
302 QUNIFORM_AA_LINE_WIDTH,
303
304 /* Number of workgroups passed to glDispatchCompute in the dimension
305 * selected by the data value.
306 */
307 QUNIFORM_NUM_WORK_GROUPS,
308
309 /* Base workgroup offset passed to vkCmdDispatchBase in the dimension
310 * selected by the data value.
311 */
312 QUNIFORM_WORK_GROUP_BASE,
313
314 /**
315 * Returns the the offset of the scratch buffer for register spilling.
316 */
317 QUNIFORM_SPILL_OFFSET,
318 QUNIFORM_SPILL_SIZE_PER_THREAD,
319
320 /**
321 * Returns the offset of the shared memory for compute shaders.
322 *
323 * This will be accessed using TMU general memory operations, so the
324 * L2T cache will effectively be the shared memory area.
325 */
326 QUNIFORM_SHARED_OFFSET,
327
328 /**
329 * Returns the number of layers in the framebuffer.
330 *
331 * This is used to cap gl_Layer in geometry shaders to avoid
332 * out-of-bounds accesses into the tile state during binning.
333 */
334 QUNIFORM_FB_LAYERS,
335
336 /**
337 * Current value of gl_ViewIndex for Multiview rendering.
338 */
339 QUNIFORM_VIEW_INDEX,
340
341 /**
342 * Inline uniform buffers
343 */
344 QUNIFORM_INLINE_UBO_0,
345 QUNIFORM_INLINE_UBO_1,
346 QUNIFORM_INLINE_UBO_2,
347 QUNIFORM_INLINE_UBO_3,
348
349 /**
350 * Current value of DrawIndex for Multidraw
351 */
352 QUNIFORM_DRAW_ID,
353 };
354
v3d_unit_data_create(uint32_t unit,uint32_t value)355 static inline uint32_t v3d_unit_data_create(uint32_t unit, uint32_t value)
356 {
357 assert(value < (1 << 24));
358 return unit << 24 | value;
359 }
360
v3d_unit_data_get_unit(uint32_t data)361 static inline uint32_t v3d_unit_data_get_unit(uint32_t data)
362 {
363 return data >> 24;
364 }
365
v3d_unit_data_get_offset(uint32_t data)366 static inline uint32_t v3d_unit_data_get_offset(uint32_t data)
367 {
368 return data & 0xffffff;
369 }
370
371 struct v3d_varying_slot {
372 uint8_t slot_and_component;
373 };
374
375 static inline struct v3d_varying_slot
v3d_slot_from_slot_and_component(uint8_t slot,uint8_t component)376 v3d_slot_from_slot_and_component(uint8_t slot, uint8_t component)
377 {
378 assert(slot < 255 / 4);
379 return (struct v3d_varying_slot){ (slot << 2) + component };
380 }
381
v3d_slot_get_slot(struct v3d_varying_slot slot)382 static inline uint8_t v3d_slot_get_slot(struct v3d_varying_slot slot)
383 {
384 return slot.slot_and_component >> 2;
385 }
386
v3d_slot_get_component(struct v3d_varying_slot slot)387 static inline uint8_t v3d_slot_get_component(struct v3d_varying_slot slot)
388 {
389 return slot.slot_and_component & 3;
390 }
391
392 struct v3d_key {
393 struct {
394 uint8_t swizzle[4];
395 } tex[V3D_MAX_TEXTURE_SAMPLERS];
396 struct {
397 uint8_t return_size;
398 uint8_t return_channels;
399 } sampler[V3D_MAX_TEXTURE_SAMPLERS];
400
401 uint8_t num_tex_used;
402 uint8_t num_samplers_used;
403 uint8_t ucp_enables;
404 bool is_last_geometry_stage;
405 bool robust_uniform_access;
406 bool robust_storage_access;
407 bool robust_image_access;
408 };
409
410 struct v3d_fs_key {
411 struct v3d_key base;
412 bool is_points;
413 bool is_lines;
414 bool line_smoothing;
415 bool point_coord_upper_left;
416 bool msaa;
417 bool sample_alpha_to_coverage;
418 bool sample_alpha_to_one;
419 /* Mask of which color render targets are present. */
420 uint8_t cbufs;
421 uint8_t swap_color_rb;
422 /* Mask of which render targets need to be written as 32-bit floats */
423 uint8_t f32_color_rb;
424 /* Masks of which render targets need to be written as ints/uints.
425 * Used by gallium to work around lost information in TGSI.
426 */
427 uint8_t int_color_rb;
428 uint8_t uint_color_rb;
429
430 /* Color format information per render target. Only set when logic
431 * operations are enabled.
432 */
433 struct {
434 enum pipe_format format;
435 uint8_t swizzle[4];
436 } color_fmt[V3D_MAX_DRAW_BUFFERS];
437
438 enum pipe_logicop logicop_func;
439 uint32_t point_sprite_mask;
440
441 /* If the fragment shader reads gl_PrimitiveID then we have 2 scenarios:
442 *
443 * - If there is a geometry shader, then gl_PrimitiveID must be written
444 * by it and the fragment shader loads it as a regular explicit input
445 * varying. This is the only valid use case in GLES 3.1.
446 *
447 * - If there is not a geometry shader (allowed since GLES 3.2 and
448 * Vulkan 1.0), then gl_PrimitiveID must be implicitly written by
449 * hardware and is considered an implicit input varying in the
450 * fragment shader.
451 */
452 bool has_gs;
453 };
454
455 struct v3d_gs_key {
456 struct v3d_key base;
457
458 struct v3d_varying_slot used_outputs[V3D_MAX_FS_INPUTS];
459 uint8_t num_used_outputs;
460
461 bool is_coord;
462 bool per_vertex_point_size;
463 };
464
465 struct v3d_vs_key {
466 struct v3d_key base;
467
468 struct v3d_varying_slot used_outputs[V3D_MAX_ANY_STAGE_INPUTS];
469 uint8_t num_used_outputs;
470
471 /* A bit-mask indicating if we need to swap the R/B channels for
472 * vertex attributes. Since the hardware doesn't provide any
473 * means to swizzle vertex attributes we need to do it in the shader.
474 */
475 uint32_t va_swap_rb_mask;
476
477 bool is_coord;
478 bool per_vertex_point_size;
479 bool clamp_color;
480 };
481
482 /** A basic block of VIR instructions. */
483 struct qblock {
484 struct list_head link;
485
486 struct list_head instructions;
487
488 struct set *predecessors;
489 struct qblock *successors[2];
490
491 int index;
492
493 /* Instruction IPs for the first and last instruction of the block.
494 * Set by qpu_schedule.c.
495 */
496 uint32_t start_qpu_ip;
497 uint32_t end_qpu_ip;
498
499 /* Instruction IP for the branch instruction of the block. Set by
500 * qpu_schedule.c.
501 */
502 uint32_t branch_qpu_ip;
503
504 /** Offset within the uniform stream at the start of the block. */
505 uint32_t start_uniform;
506 /** Offset within the uniform stream of the branch instruction */
507 uint32_t branch_uniform;
508
509 /**
510 * Has the terminating branch of this block already been emitted
511 * by a break or continue?
512 */
513 bool branch_emitted;
514
515 /** @{ used by v3d_vir_live_variables.c */
516 BITSET_WORD *def;
517 BITSET_WORD *defin;
518 BITSET_WORD *defout;
519 BITSET_WORD *use;
520 BITSET_WORD *live_in;
521 BITSET_WORD *live_out;
522 int start_ip, end_ip;
523 /** @} */
524 };
525
526 /** Which util/list.h add mode we should use when inserting an instruction. */
527 enum vir_cursor_mode {
528 vir_cursor_add,
529 vir_cursor_addtail,
530 };
531
532 /**
533 * Tracking structure for where new instructions should be inserted. Create
534 * with one of the vir_after_inst()-style helper functions.
535 *
536 * This does not protect against removal of the block or instruction, so we
537 * have an assert in instruction removal to try to catch it.
538 */
539 struct vir_cursor {
540 enum vir_cursor_mode mode;
541 struct list_head *link;
542 };
543
544 static inline struct vir_cursor
vir_before_inst(struct qinst * inst)545 vir_before_inst(struct qinst *inst)
546 {
547 return (struct vir_cursor){ vir_cursor_addtail, &inst->link };
548 }
549
550 static inline struct vir_cursor
vir_after_inst(struct qinst * inst)551 vir_after_inst(struct qinst *inst)
552 {
553 return (struct vir_cursor){ vir_cursor_add, &inst->link };
554 }
555
556 static inline struct vir_cursor
vir_before_block(struct qblock * block)557 vir_before_block(struct qblock *block)
558 {
559 return (struct vir_cursor){ vir_cursor_add, &block->instructions };
560 }
561
562 static inline struct vir_cursor
vir_after_block(struct qblock * block)563 vir_after_block(struct qblock *block)
564 {
565 return (struct vir_cursor){ vir_cursor_addtail, &block->instructions };
566 }
567
568 enum v3d_compilation_result {
569 V3D_COMPILATION_SUCCEEDED,
570 V3D_COMPILATION_FAILED_REGISTER_ALLOCATION,
571 V3D_COMPILATION_FAILED,
572 };
573
574 /**
575 * Compiler state saved across compiler invocations, for any expensive global
576 * setup.
577 */
578 struct v3d_compiler {
579 const struct v3d_device_info *devinfo;
580 uint32_t max_inline_uniform_buffers;
581 struct ra_regs *regs;
582 struct ra_class *reg_class_any[3];
583 struct ra_class *reg_class_r5[3];
584 struct ra_class *reg_class_phys[3];
585 struct ra_class *reg_class_phys_or_acc[3];
586 };
587
588 /**
589 * This holds partially interpolated inputs as provided by hardware
590 * (The Vp = A*(x - x0) + B*(y - y0) term), as well as the C coefficient
591 * required to compute the final interpolated value.
592 */
593 struct v3d_interp_input {
594 struct qreg vp;
595 struct qreg C;
596 unsigned mode; /* interpolation mode */
597 };
598
599 struct v3d_ra_node_info {
600 struct {
601 uint32_t priority;
602 uint8_t class_bits;
603 bool is_program_end;
604 bool unused;
605
606 /* V3D 7.x */
607 bool is_ldunif_dst;
608 } *info;
609 uint32_t alloc_count;
610 };
611
612 struct v3d_compile {
613 const struct v3d_device_info *devinfo;
614 nir_shader *s;
615 nir_function_impl *impl;
616 struct exec_list *cf_node_list;
617 const struct v3d_compiler *compiler;
618
619 void (*debug_output)(const char *msg,
620 void *debug_output_data);
621 void *debug_output_data;
622
623 /**
624 * Mapping from nir_register * or nir_def * to array of struct
625 * qreg for the values.
626 */
627 struct hash_table *def_ht;
628
629 /* For each temp, the instruction generating its value. */
630 struct qinst **defs;
631 uint32_t defs_array_size;
632
633 /* TMU pipelining tracking */
634 struct {
635 /* NIR registers that have been updated with a TMU operation
636 * that has not been flushed yet.
637 */
638 struct set *outstanding_regs;
639
640 uint32_t output_fifo_size;
641
642 struct {
643 nir_def *def;
644 uint8_t num_components;
645 uint8_t component_mask;
646 } flush[MAX_TMU_QUEUE_SIZE];
647 uint32_t flush_count;
648 uint32_t total_count;
649 } tmu;
650
651 /**
652 * Inputs to the shader, arranged by TGSI declaration order.
653 *
654 * Not all fragment shader QFILE_VARY reads are present in this array.
655 */
656 struct qreg *inputs;
657 /**
658 * Partially interpolated inputs to the shader.
659 */
660 struct v3d_interp_input *interp;
661 struct qreg *outputs;
662 bool msaa_per_sample_output;
663 struct qreg color_reads[V3D_MAX_DRAW_BUFFERS * V3D_MAX_SAMPLES * 4];
664 struct qreg sample_colors[V3D_MAX_DRAW_BUFFERS * V3D_MAX_SAMPLES * 4];
665 uint32_t inputs_array_size;
666 uint32_t outputs_array_size;
667 uint32_t uniforms_array_size;
668
669 /* Booleans for whether the corresponding QFILE_VARY[i] is
670 * flat-shaded. This includes gl_FragColor flat-shading, which is
671 * customized based on the shademodel_flat shader key.
672 */
673 uint32_t flat_shade_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
674
675 uint32_t noperspective_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
676
677 uint32_t centroid_flags[BITSET_WORDS(V3D_MAX_FS_INPUTS)];
678
679 bool uses_center_w;
680 bool writes_z;
681 bool writes_z_from_fep;
682 bool reads_z;
683 bool uses_implicit_point_line_varyings;
684
685 /* True if a fragment shader reads gl_PrimitiveID */
686 bool fs_uses_primitive_id;
687
688 /* Whether we are using the fallback scheduler. This will be set after
689 * register allocation has failed once.
690 */
691 bool fallback_scheduler;
692
693 /* Disable TMU pipelining. This may increase the chances of being able
694 * to compile shaders with high register pressure that require to emit
695 * TMU spills.
696 */
697 bool disable_tmu_pipelining;
698 bool pipelined_any_tmu;
699
700 /* Disable sorting of UBO loads with constant offset. This may
701 * increase the chances of being able to compile shaders with high
702 * register pressure.
703 */
704 bool disable_constant_ubo_load_sorting;
705 bool sorted_any_ubo_loads;
706
707 /* Moves UBO/SSBO loads right before their first user (nir_opt_move).
708 * This can reduce register pressure.
709 */
710 bool move_buffer_loads;
711
712 /* Emits ldunif for each new uniform, even if the uniform was already
713 * emitted in the same block. Useful to compile shaders with high
714 * register pressure or to disable the optimization during uniform
715 * spills.
716 */
717 bool disable_ldunif_opt;
718
719 /* Disables loop unrolling to reduce register pressure. */
720 bool disable_loop_unrolling;
721 bool unrolled_any_loops;
722
723 /* Disables nir_opt_gcm to reduce register pressure. */
724 bool disable_gcm;
725
726 /* If calling nir_opt_gcm made any progress. Used to skip new rebuilds
727 * if possible
728 */
729 bool gcm_progress;
730
731 /* Disables scheduling of general TMU loads (and unfiltered image load).
732 */
733 bool disable_general_tmu_sched;
734 bool has_general_tmu_load;
735
736 /* Minimum number of threads we are willing to use to register allocate
737 * a shader with the current compilation strategy. This only prevents
738 * us from lowering the thread count to register allocate successfully,
739 * which can be useful when we prefer doing other changes to the
740 * compilation strategy before dropping thread count.
741 */
742 uint32_t min_threads_for_reg_alloc;
743
744 /* Whether TMU spills are allowed. If this is disabled it may cause
745 * register allocation to fail. We set this to favor other compilation
746 * strategies that can reduce register pressure and hopefully reduce or
747 * eliminate TMU spills in the shader.
748 */
749 uint32_t max_tmu_spills;
750
751 uint32_t compile_strategy_idx;
752
753 /* The UBO index and block used with the last unifa load, as well as the
754 * current unifa offset *after* emitting that load. This is used to skip
755 * unifa writes (and their 3 delay slot) when the next UBO load reads
756 * right after the previous one in the same block.
757 */
758 struct qblock *current_unifa_block;
759 int32_t current_unifa_index;
760 uint32_t current_unifa_offset;
761 bool current_unifa_is_ubo;
762
763 /* State for whether we're executing on each channel currently. 0 if
764 * yes, otherwise a block number + 1 that the channel jumped to.
765 */
766 struct qreg execute;
767 bool in_control_flow;
768
769 struct qreg line_x, point_x, point_y, primitive_id;
770
771 /**
772 * Instance ID, which comes in before the vertex attribute payload if
773 * the shader record requests it.
774 */
775 struct qreg iid;
776
777 /**
778 * Base Instance ID, which comes in before the vertex attribute payload
779 * (after Instance ID) if the shader record requests it.
780 */
781 struct qreg biid;
782
783 /**
784 * Vertex ID, which comes in before the vertex attribute payload
785 * (after Base Instance) if the shader record requests it.
786 */
787 struct qreg vid;
788
789 /* Fragment shader payload regs. */
790 struct qreg payload_w, payload_w_centroid, payload_z;
791
792 struct qreg cs_payload[2];
793 struct qreg cs_shared_offset;
794 int local_invocation_index_bits;
795
796 /* Starting value of the sample mask in a fragment shader. We use
797 * this to identify lanes that have been terminated/discarded.
798 */
799 struct qreg start_msf;
800
801 /* If the shader uses subgroup functionality */
802 bool has_subgroups;
803
804 uint8_t vattr_sizes[V3D_MAX_VS_INPUTS / 4];
805 uint32_t vpm_output_size;
806
807 /* Size in bytes of registers that have been spilled. This is how much
808 * space needs to be available in the spill BO per thread per QPU.
809 */
810 uint32_t spill_size;
811 /* Shader-db stats */
812 uint32_t spills, fills, loops;
813
814 /* Whether we are in the process of spilling registers for
815 * register allocation
816 */
817 bool spilling;
818
819 /**
820 * Register spilling's per-thread base address, shared between each
821 * spill/fill's addressing calculations (also used for scratch
822 * access).
823 */
824 struct qreg spill_base;
825
826 /* Bit vector of which temps may be spilled */
827 BITSET_WORD *spillable;
828
829 /* Used during register allocation */
830 int thread_index;
831 struct v3d_ra_node_info nodes;
832 struct ra_graph *g;
833
834 /**
835 * Array of the VARYING_SLOT_* of all FS QFILE_VARY reads.
836 *
837 * This includes those that aren't part of the VPM varyings, like
838 * point/line coordinates.
839 */
840 struct v3d_varying_slot input_slots[V3D_MAX_FS_INPUTS];
841
842 /**
843 * An entry per outputs[] in the VS indicating what the VARYING_SLOT_*
844 * of the output is. Used to emit from the VS in the order that the
845 * FS needs.
846 */
847 struct v3d_varying_slot *output_slots;
848
849 struct pipe_shader_state *shader_state;
850 struct v3d_key *key;
851 struct v3d_fs_key *fs_key;
852 struct v3d_gs_key *gs_key;
853 struct v3d_vs_key *vs_key;
854
855 /* Live ranges of temps. */
856 int *temp_start, *temp_end;
857 bool live_intervals_valid;
858
859 uint32_t *uniform_data;
860 enum quniform_contents *uniform_contents;
861 uint32_t uniform_array_size;
862 uint32_t num_uniforms;
863 uint32_t output_position_index;
864 nir_variable *output_color_var[V3D_MAX_DRAW_BUFFERS];
865 uint32_t output_sample_mask_index;
866
867 struct qreg undef;
868 uint32_t num_temps;
869 /* Number of temps in the program right before we spill a new temp. We
870 * use this to know which temps existed before a spill and which were
871 * added with the spill itself.
872 */
873 uint32_t spill_start_num_temps;
874
875 struct vir_cursor cursor;
876 struct list_head blocks;
877 int next_block_index;
878 struct qblock *cur_block;
879 struct qblock *loop_cont_block;
880 struct qblock *loop_break_block;
881 /**
882 * Which temp, if any, do we currently have in the flags?
883 * This is set when processing a comparison instruction, and
884 * reset to -1 by anything else that touches the flags.
885 */
886 int32_t flags_temp;
887 enum v3d_qpu_cond flags_cond;
888
889 uint64_t *qpu_insts;
890 uint32_t qpu_inst_count;
891 uint32_t qpu_inst_size;
892 uint32_t qpu_inst_stalled_count;
893 uint32_t nop_count;
894
895 /* For the FS, the number of varying inputs not counting the
896 * point/line varyings payload
897 */
898 uint32_t num_inputs;
899
900 uint32_t program_id;
901 uint32_t variant_id;
902
903 /* Set to compile program in in 1x, 2x, or 4x threaded mode, where
904 * SIG_THREAD_SWITCH is used to hide texturing latency at the cost of
905 * limiting ourselves to the part of the physical reg space.
906 *
907 * On V3D 3.x, 2x or 4x divide the physical reg space by 2x or 4x. On
908 * V3D 4.x, all shaders are 2x threaded, and 4x only divides the
909 * physical reg space in half.
910 */
911 uint8_t threads;
912 struct qinst *last_thrsw;
913 bool last_thrsw_at_top_level;
914
915 bool emitted_tlb_load;
916 bool lock_scoreboard_on_first_thrsw;
917
918 enum v3d_compilation_result compilation_result;
919
920 bool tmu_dirty_rcl;
921 bool has_global_address;
922
923 /* If we have processed a discard/terminate instruction. This may
924 * cause some lanes to be inactive even during uniform control
925 * flow.
926 */
927 bool emitted_discard;
928 };
929
930 struct v3d_uniform_list {
931 enum quniform_contents *contents;
932 uint32_t *data;
933 uint32_t count;
934 };
935
936 struct v3d_prog_data {
937 struct v3d_uniform_list uniforms;
938
939 uint32_t spill_size;
940 uint32_t tmu_spills;
941 uint32_t tmu_fills;
942 uint32_t tmu_count;
943
944 uint32_t qpu_read_stalls;
945
946 uint8_t compile_strategy_idx;
947
948 uint8_t threads;
949
950 /* For threads > 1, whether the program should be dispatched in the
951 * after-final-THRSW state.
952 */
953 bool single_seg;
954
955 bool tmu_dirty_rcl;
956
957 bool has_control_barrier;
958
959 bool has_global_address;
960 };
961
962 struct v3d_vs_prog_data {
963 struct v3d_prog_data base;
964
965 bool uses_iid, uses_biid, uses_vid;
966
967 /* Number of components read from each vertex attribute. */
968 uint8_t vattr_sizes[V3D_MAX_VS_INPUTS / 4];
969
970 /* Total number of components read, for the shader state record. */
971 uint32_t vpm_input_size;
972
973 /* Total number of components written, for the shader state record. */
974 uint32_t vpm_output_size;
975
976 /* Set if there should be separate VPM segments for input and output.
977 * If unset, vpm_input_size will be 0.
978 */
979 bool separate_segments;
980
981 /* Value to be programmed in VCM_CACHE_SIZE. */
982 uint8_t vcm_cache_size;
983
984 /* Maps the nir->data.location to its
985 * nir->data.driver_location. In general we are using the
986 * driver location as index (like vattr_sizes above), so this
987 * map is useful when what we have is the location
988 *
989 * Returns -1 if the location is not used
990 */
991 int32_t driver_location_map[V3D_MAX_VS_INPUTS];
992 };
993
994 struct v3d_gs_prog_data {
995 struct v3d_prog_data base;
996
997 /* Whether the program reads gl_PrimitiveIDIn */
998 bool uses_pid;
999
1000 /* Number of components read from each input varying. */
1001 uint8_t input_sizes[V3D_MAX_GS_INPUTS / 4];
1002
1003 /* Number of inputs */
1004 uint8_t num_inputs;
1005 struct v3d_varying_slot input_slots[V3D_MAX_GS_INPUTS];
1006
1007 /* Total number of components written, for the shader state record. */
1008 uint32_t vpm_output_size;
1009
1010 /* Maximum SIMD dispatch width to not exceed VPM output size limits
1011 * in the geometry shader. Notice that the final dispatch width has to
1012 * be decided at draw time and could be lower based on the VPM pressure
1013 * added by other shader stages.
1014 */
1015 uint8_t simd_width;
1016
1017 /* Output primitive type */
1018 uint8_t out_prim_type;
1019
1020 /* Number of GS invocations */
1021 uint8_t num_invocations;
1022
1023 bool writes_psiz;
1024 };
1025
1026 struct v3d_fs_prog_data {
1027 struct v3d_prog_data base;
1028
1029 /* Whether the program reads gl_PrimitiveID */
1030 bool uses_pid;
1031
1032 struct v3d_varying_slot input_slots[V3D_MAX_FS_INPUTS];
1033
1034 /* Array of flat shade flags.
1035 *
1036 * Each entry is only 24 bits (high 8 bits 0), to match the hardware
1037 * packet layout.
1038 */
1039 uint32_t flat_shade_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
1040
1041 uint32_t noperspective_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
1042
1043 uint32_t centroid_flags[((V3D_MAX_FS_INPUTS - 1) / 24) + 1];
1044
1045 uint8_t num_inputs;
1046 bool writes_z;
1047 bool writes_z_from_fep;
1048 bool disable_ez;
1049 bool uses_center_w;
1050 bool uses_implicit_point_line_varyings;
1051 bool lock_scoreboard_on_first_thrsw;
1052
1053 /* If the fragment shader does anything that requires to force
1054 * per-sample MSAA, such as reading gl_SampleID.
1055 */
1056 bool force_per_sample_msaa;
1057 };
1058
1059 struct v3d_compute_prog_data {
1060 struct v3d_prog_data base;
1061 /* Size in bytes of the workgroup's shared space. */
1062 uint32_t shared_size;
1063 uint16_t local_size[3];
1064 /* If the shader uses subgroup functionality */
1065 bool has_subgroups;
1066 };
1067
1068 struct vpm_config {
1069 uint32_t As;
1070 uint32_t Vc;
1071 uint32_t Gs;
1072 uint32_t Gd;
1073 uint32_t Gv;
1074 uint32_t Ve;
1075 uint32_t gs_width;
1076 };
1077
1078 bool
1079 v3d_compute_vpm_config(struct v3d_device_info *devinfo,
1080 struct v3d_vs_prog_data *vs_bin,
1081 struct v3d_vs_prog_data *vs,
1082 struct v3d_gs_prog_data *gs_bin,
1083 struct v3d_gs_prog_data *gs,
1084 struct vpm_config *vpm_cfg_bin,
1085 struct vpm_config *vpm_cfg);
1086 void
1087 v3d_pack_unnormalized_coordinates(struct v3d_device_info *devinfo,
1088 uint32_t *p1_packed,
1089 bool unnormalized_coordinates);
1090
1091 static inline bool
vir_has_uniform(struct qinst * inst)1092 vir_has_uniform(struct qinst *inst)
1093 {
1094 return inst->uniform != ~0;
1095 }
1096
1097 const struct v3d_compiler *v3d_compiler_init(const struct v3d_device_info *devinfo,
1098 uint32_t max_inline_uniform_buffers);
1099 void v3d_compiler_free(const struct v3d_compiler *compiler);
1100 void v3d_optimize_nir(struct v3d_compile *c, struct nir_shader *s);
1101
1102 uint64_t *v3d_compile(const struct v3d_compiler *compiler,
1103 struct v3d_key *key,
1104 struct v3d_prog_data **prog_data,
1105 nir_shader *s,
1106 void (*debug_output)(const char *msg,
1107 void *debug_output_data),
1108 void *debug_output_data,
1109 int program_id, int variant_id,
1110 uint32_t *final_assembly_size);
1111
1112 uint32_t v3d_prog_data_size(gl_shader_stage stage);
1113 void v3d_nir_to_vir(struct v3d_compile *c);
1114
1115 void vir_compile_destroy(struct v3d_compile *c);
1116 const char *vir_get_stage_name(struct v3d_compile *c);
1117 struct qblock *vir_new_block(struct v3d_compile *c);
1118 void vir_set_emit_block(struct v3d_compile *c, struct qblock *block);
1119 void vir_link_blocks(struct qblock *predecessor, struct qblock *successor);
1120 struct qblock *vir_entry_block(struct v3d_compile *c);
1121 struct qblock *vir_exit_block(struct v3d_compile *c);
1122 struct qinst *vir_add_inst(enum v3d_qpu_add_op op, struct qreg dst,
1123 struct qreg src0, struct qreg src1);
1124 struct qinst *vir_mul_inst(enum v3d_qpu_mul_op op, struct qreg dst,
1125 struct qreg src0, struct qreg src1);
1126 struct qinst *vir_branch_inst(struct v3d_compile *c,
1127 enum v3d_qpu_branch_cond cond);
1128 void vir_remove_instruction(struct v3d_compile *c, struct qinst *qinst);
1129 uint32_t vir_get_uniform_index(struct v3d_compile *c,
1130 enum quniform_contents contents,
1131 uint32_t data);
1132 struct qreg vir_uniform(struct v3d_compile *c,
1133 enum quniform_contents contents,
1134 uint32_t data);
1135 void vir_schedule_instructions(struct v3d_compile *c);
1136 void v3d_setup_spill_base(struct v3d_compile *c);
1137 struct v3d_qpu_instr v3d_qpu_nop(void);
1138
1139 struct qreg vir_emit_def(struct v3d_compile *c, struct qinst *inst);
1140 struct qinst *vir_emit_nondef(struct v3d_compile *c, struct qinst *inst);
1141 void vir_set_cond(struct qinst *inst, enum v3d_qpu_cond cond);
1142 enum v3d_qpu_cond vir_get_cond(struct qinst *inst);
1143 void vir_set_pf(struct v3d_compile *c, struct qinst *inst, enum v3d_qpu_pf pf);
1144 void vir_set_uf(struct v3d_compile *c, struct qinst *inst, enum v3d_qpu_uf uf);
1145 void vir_set_unpack(struct qinst *inst, int src,
1146 enum v3d_qpu_input_unpack unpack);
1147 void vir_set_pack(struct qinst *inst, enum v3d_qpu_output_pack pack);
1148
1149 struct qreg vir_get_temp(struct v3d_compile *c);
1150 void vir_calculate_live_intervals(struct v3d_compile *c);
1151 int vir_get_nsrc(struct qinst *inst);
1152 bool vir_has_side_effects(struct v3d_compile *c, struct qinst *inst);
1153 bool vir_get_add_op(struct qinst *inst, enum v3d_qpu_add_op *op);
1154 bool vir_get_mul_op(struct qinst *inst, enum v3d_qpu_mul_op *op);
1155 bool vir_is_raw_mov(struct qinst *inst);
1156 bool vir_is_tex(const struct v3d_device_info *devinfo, struct qinst *inst);
1157 bool vir_is_add(struct qinst *inst);
1158 bool vir_is_mul(struct qinst *inst);
1159 bool vir_writes_r4_implicitly(const struct v3d_device_info *devinfo, struct qinst *inst);
1160 struct qreg vir_follow_movs(struct v3d_compile *c, struct qreg reg);
1161 uint8_t vir_channels_written(struct qinst *inst);
1162 struct qreg ntq_get_src(struct v3d_compile *c, nir_src src, int i);
1163 void ntq_store_def(struct v3d_compile *c, nir_def *def, int chan,
1164 struct qreg result);
1165 bool ntq_tmu_fifo_overflow(struct v3d_compile *c, uint32_t components);
1166 void ntq_add_pending_tmu_flush(struct v3d_compile *c, nir_def *def,
1167 uint32_t component_mask);
1168 void ntq_flush_tmu(struct v3d_compile *c);
1169 void vir_emit_thrsw(struct v3d_compile *c);
1170
1171 void vir_dump(struct v3d_compile *c);
1172 void vir_dump_inst(struct v3d_compile *c, struct qinst *inst);
1173 void vir_dump_uniform(enum quniform_contents contents, uint32_t data);
1174
1175 void vir_validate(struct v3d_compile *c);
1176
1177 void vir_optimize(struct v3d_compile *c);
1178 bool vir_opt_algebraic(struct v3d_compile *c);
1179 bool vir_opt_constant_folding(struct v3d_compile *c);
1180 bool vir_opt_copy_propagate(struct v3d_compile *c);
1181 bool vir_opt_dead_code(struct v3d_compile *c);
1182 bool vir_opt_peephole_sf(struct v3d_compile *c);
1183 bool vir_opt_redundant_flags(struct v3d_compile *c);
1184 bool vir_opt_small_immediates(struct v3d_compile *c);
1185 bool vir_opt_vpm(struct v3d_compile *c);
1186 bool vir_opt_constant_alu(struct v3d_compile *c);
1187 bool v3d_nir_lower_io(nir_shader *s, struct v3d_compile *c);
1188 bool v3d_nir_lower_line_smooth(nir_shader *shader);
1189 bool v3d_nir_lower_logic_ops(nir_shader *s, struct v3d_compile *c);
1190 bool v3d_nir_lower_scratch(nir_shader *s);
1191 bool v3d_nir_lower_txf_ms(nir_shader *s);
1192 bool v3d_nir_lower_image_load_store(nir_shader *s, struct v3d_compile *c);
1193 bool v3d_nir_lower_load_store_bitsize(nir_shader *s);
1194
1195 void v3d_vir_emit_tex(struct v3d_compile *c, nir_tex_instr *instr);
1196 void v3d_vir_emit_image_load_store(struct v3d_compile *c,
1197 nir_intrinsic_instr *instr);
1198
1199 void v3d_vir_to_qpu(struct v3d_compile *c, struct qpu_reg *temp_registers);
1200 uint32_t v3d_qpu_schedule_instructions(struct v3d_compile *c);
1201 void qpu_validate(struct v3d_compile *c);
1202 struct qpu_reg *v3d_register_allocate(struct v3d_compile *c);
1203 bool vir_init_reg_sets(struct v3d_compiler *compiler);
1204
1205 int v3d_shaderdb_dump(struct v3d_compile *c, char **shaderdb_str);
1206
1207 bool v3d_gl_format_is_return_32(enum pipe_format format);
1208
1209 uint32_t
1210 v3d_get_op_for_atomic_add(nir_intrinsic_instr *instr, unsigned src);
1211
1212 static inline bool
quniform_contents_is_texture_p0(enum quniform_contents contents)1213 quniform_contents_is_texture_p0(enum quniform_contents contents)
1214 {
1215 return (contents >= QUNIFORM_TEXTURE_CONFIG_P0_0 &&
1216 contents < (QUNIFORM_TEXTURE_CONFIG_P0_0 +
1217 V3D_MAX_TEXTURE_SAMPLERS));
1218 }
1219
1220 static inline bool
vir_in_nonuniform_control_flow(struct v3d_compile * c)1221 vir_in_nonuniform_control_flow(struct v3d_compile *c)
1222 {
1223 return c->execute.file != QFILE_NULL;
1224 }
1225
1226 static inline struct qreg
vir_uniform_ui(struct v3d_compile * c,uint32_t ui)1227 vir_uniform_ui(struct v3d_compile *c, uint32_t ui)
1228 {
1229 return vir_uniform(c, QUNIFORM_CONSTANT, ui);
1230 }
1231
1232 static inline struct qreg
vir_uniform_f(struct v3d_compile * c,float f)1233 vir_uniform_f(struct v3d_compile *c, float f)
1234 {
1235 return vir_uniform(c, QUNIFORM_CONSTANT, fui(f));
1236 }
1237
1238 #define VIR_ALU0(name, vir_inst, op) \
1239 static inline struct qreg \
1240 vir_##name(struct v3d_compile *c) \
1241 { \
1242 return vir_emit_def(c, vir_inst(op, c->undef, \
1243 c->undef, c->undef)); \
1244 } \
1245 static inline struct qinst * \
1246 vir_##name##_dest(struct v3d_compile *c, struct qreg dest) \
1247 { \
1248 return vir_emit_nondef(c, vir_inst(op, dest, \
1249 c->undef, c->undef)); \
1250 }
1251
1252 #define VIR_ALU1(name, vir_inst, op) \
1253 static inline struct qreg \
1254 vir_##name(struct v3d_compile *c, struct qreg a) \
1255 { \
1256 return vir_emit_def(c, vir_inst(op, c->undef, \
1257 a, c->undef)); \
1258 } \
1259 static inline struct qinst * \
1260 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
1261 struct qreg a) \
1262 { \
1263 return vir_emit_nondef(c, vir_inst(op, dest, a, \
1264 c->undef)); \
1265 }
1266
1267 #define VIR_ALU2(name, vir_inst, op) \
1268 static inline struct qreg \
1269 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b) \
1270 { \
1271 return vir_emit_def(c, vir_inst(op, c->undef, a, b)); \
1272 } \
1273 static inline struct qinst * \
1274 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
1275 struct qreg a, struct qreg b) \
1276 { \
1277 return vir_emit_nondef(c, vir_inst(op, dest, a, b)); \
1278 }
1279
1280 #define VIR_NODST_0(name, vir_inst, op) \
1281 static inline struct qinst * \
1282 vir_##name(struct v3d_compile *c) \
1283 { \
1284 return vir_emit_nondef(c, vir_inst(op, c->undef, \
1285 c->undef, c->undef)); \
1286 }
1287
1288 #define VIR_NODST_1(name, vir_inst, op) \
1289 static inline struct qinst * \
1290 vir_##name(struct v3d_compile *c, struct qreg a) \
1291 { \
1292 return vir_emit_nondef(c, vir_inst(op, c->undef, \
1293 a, c->undef)); \
1294 }
1295
1296 #define VIR_NODST_2(name, vir_inst, op) \
1297 static inline struct qinst * \
1298 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b) \
1299 { \
1300 return vir_emit_nondef(c, vir_inst(op, c->undef, \
1301 a, b)); \
1302 }
1303
1304 #define VIR_SFU(name) \
1305 static inline struct qreg \
1306 vir_##name(struct v3d_compile *c, struct qreg a) \
1307 { \
1308 return vir_emit_def(c, vir_add_inst(V3D_QPU_A_##name, \
1309 c->undef, \
1310 a, c->undef)); \
1311 } \
1312 static inline struct qinst * \
1313 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
1314 struct qreg a) \
1315 { \
1316 return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_##name, \
1317 dest, \
1318 a, c->undef)); \
1319 }
1320
1321 #define VIR_SFU2(name) \
1322 static inline struct qreg \
1323 vir_##name(struct v3d_compile *c, struct qreg a, struct qreg b) \
1324 { \
1325 return vir_emit_def(c, vir_add_inst(V3D_QPU_A_##name, \
1326 c->undef, \
1327 a, b)); \
1328 } \
1329 static inline struct qinst * \
1330 vir_##name##_dest(struct v3d_compile *c, struct qreg dest, \
1331 struct qreg a, struct qreg b) \
1332 { \
1333 return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_##name, \
1334 dest, \
1335 a, b)); \
1336 }
1337
1338 #define VIR_A_ALU2(name) VIR_ALU2(name, vir_add_inst, V3D_QPU_A_##name)
1339 #define VIR_M_ALU2(name) VIR_ALU2(name, vir_mul_inst, V3D_QPU_M_##name)
1340 #define VIR_A_ALU1(name) VIR_ALU1(name, vir_add_inst, V3D_QPU_A_##name)
1341 #define VIR_M_ALU1(name) VIR_ALU1(name, vir_mul_inst, V3D_QPU_M_##name)
1342 #define VIR_A_ALU0(name) VIR_ALU0(name, vir_add_inst, V3D_QPU_A_##name)
1343 #define VIR_M_ALU0(name) VIR_ALU0(name, vir_mul_inst, V3D_QPU_M_##name)
1344 #define VIR_A_NODST_2(name) VIR_NODST_2(name, vir_add_inst, V3D_QPU_A_##name)
1345 #define VIR_M_NODST_2(name) VIR_NODST_2(name, vir_mul_inst, V3D_QPU_M_##name)
1346 #define VIR_A_NODST_1(name) VIR_NODST_1(name, vir_add_inst, V3D_QPU_A_##name)
1347 #define VIR_M_NODST_1(name) VIR_NODST_1(name, vir_mul_inst, V3D_QPU_M_##name)
1348 #define VIR_A_NODST_0(name) VIR_NODST_0(name, vir_add_inst, V3D_QPU_A_##name)
1349
1350 VIR_A_ALU2(FADD)
VIR_A_ALU2(VFPACK)1351 VIR_A_ALU2(VFPACK)
1352 VIR_A_ALU2(FSUB)
1353 VIR_A_ALU2(FMIN)
1354 VIR_A_ALU2(FMAX)
1355
1356 VIR_A_ALU2(ADD)
1357 VIR_A_ALU2(SUB)
1358 VIR_A_ALU2(SHL)
1359 VIR_A_ALU2(SHR)
1360 VIR_A_ALU2(ASR)
1361 VIR_A_ALU2(ROR)
1362 VIR_A_ALU2(MIN)
1363 VIR_A_ALU2(MAX)
1364 VIR_A_ALU2(UMIN)
1365 VIR_A_ALU2(UMAX)
1366 VIR_A_ALU2(AND)
1367 VIR_A_ALU2(OR)
1368 VIR_A_ALU2(XOR)
1369 VIR_A_ALU2(VADD)
1370 VIR_A_ALU2(VSUB)
1371 VIR_A_NODST_2(STVPMV)
1372 VIR_A_NODST_2(STVPMD)
1373 VIR_A_ALU1(NOT)
1374 VIR_A_ALU1(NEG)
1375 VIR_A_ALU1(FLAPUSH)
1376 VIR_A_ALU1(FLBPUSH)
1377 VIR_A_ALU1(FLPOP)
1378 VIR_A_ALU0(FLAFIRST)
1379 VIR_A_ALU0(FLNAFIRST)
1380 VIR_A_ALU1(SETMSF)
1381 VIR_A_ALU1(SETREVF)
1382 VIR_A_ALU0(TIDX)
1383 VIR_A_ALU0(EIDX)
1384 VIR_A_ALU1(LDVPMV_IN)
1385 VIR_A_ALU1(LDVPMV_OUT)
1386 VIR_A_ALU1(LDVPMD_IN)
1387 VIR_A_ALU1(LDVPMD_OUT)
1388 VIR_A_ALU2(LDVPMG_IN)
1389 VIR_A_ALU2(LDVPMG_OUT)
1390 VIR_A_ALU0(TMUWT)
1391
1392 VIR_A_ALU0(IID)
1393 VIR_A_ALU0(FXCD)
1394 VIR_A_ALU0(XCD)
1395 VIR_A_ALU0(FYCD)
1396 VIR_A_ALU0(YCD)
1397 VIR_A_ALU0(MSF)
1398 VIR_A_ALU0(REVF)
1399 VIR_A_ALU0(BARRIERID)
1400 VIR_A_ALU0(SAMPID)
1401 VIR_A_NODST_1(VPMSETUP)
1402 VIR_A_NODST_0(VPMWT)
1403 VIR_A_ALU2(FCMP)
1404 VIR_A_ALU2(VFMAX)
1405
1406 VIR_A_ALU1(FROUND)
1407 VIR_A_ALU1(FTOIN)
1408 VIR_A_ALU1(FTRUNC)
1409 VIR_A_ALU1(FTOIZ)
1410 VIR_A_ALU1(FFLOOR)
1411 VIR_A_ALU1(FTOUZ)
1412 VIR_A_ALU1(FCEIL)
1413 VIR_A_ALU1(FTOC)
1414
1415 VIR_A_ALU1(FDX)
1416 VIR_A_ALU1(FDY)
1417
1418 VIR_A_ALU1(ITOF)
1419 VIR_A_ALU1(CLZ)
1420 VIR_A_ALU1(UTOF)
1421
1422 VIR_M_ALU2(UMUL24)
1423 VIR_M_ALU2(FMUL)
1424 VIR_M_ALU2(SMUL24)
1425 VIR_M_NODST_2(MULTOP)
1426
1427 VIR_M_ALU1(MOV)
1428 VIR_M_ALU1(FMOV)
1429
1430 VIR_SFU(RECIP)
1431 VIR_SFU(RSQRT)
1432 VIR_SFU(EXP)
1433 VIR_SFU(LOG)
1434 VIR_SFU(SIN)
1435 VIR_SFU(RSQRT2)
1436
1437 VIR_SFU(BALLOT)
1438 VIR_SFU(BCASTF)
1439 VIR_SFU(ALLEQ)
1440 VIR_SFU(ALLFEQ)
1441 VIR_SFU2(ROTQ)
1442 VIR_SFU2(ROT)
1443 VIR_SFU2(SHUFFLE)
1444
1445 VIR_A_ALU2(VPACK)
1446 VIR_A_ALU2(V8PACK)
1447 VIR_A_ALU2(V10PACK)
1448 VIR_A_ALU2(V11FPACK)
1449
1450 VIR_M_ALU1(FTOUNORM16)
1451 VIR_M_ALU1(FTOSNORM16)
1452
1453 VIR_M_ALU1(VFTOUNORM8)
1454 VIR_M_ALU1(VFTOSNORM8)
1455
1456 VIR_M_ALU1(VFTOUNORM10LO)
1457 VIR_M_ALU1(VFTOUNORM10HI)
1458
1459 static inline struct qinst *
1460 vir_MOV_cond(struct v3d_compile *c, enum v3d_qpu_cond cond,
1461 struct qreg dest, struct qreg src)
1462 {
1463 struct qinst *mov = vir_MOV_dest(c, dest, src);
1464 vir_set_cond(mov, cond);
1465 return mov;
1466 }
1467
1468 static inline struct qreg
vir_SEL(struct v3d_compile * c,enum v3d_qpu_cond cond,struct qreg src0,struct qreg src1)1469 vir_SEL(struct v3d_compile *c, enum v3d_qpu_cond cond,
1470 struct qreg src0, struct qreg src1)
1471 {
1472 struct qreg t = vir_get_temp(c);
1473 vir_MOV_dest(c, t, src1);
1474 vir_MOV_cond(c, cond, t, src0);
1475 return t;
1476 }
1477
1478 static inline struct qinst *
vir_NOP(struct v3d_compile * c)1479 vir_NOP(struct v3d_compile *c)
1480 {
1481 return vir_emit_nondef(c, vir_add_inst(V3D_QPU_A_NOP,
1482 c->undef, c->undef, c->undef));
1483 }
1484
1485 static inline struct qreg
vir_LDTMU(struct v3d_compile * c)1486 vir_LDTMU(struct v3d_compile *c)
1487 {
1488 struct qinst *ldtmu = vir_add_inst(V3D_QPU_A_NOP, c->undef,
1489 c->undef, c->undef);
1490 ldtmu->qpu.sig.ldtmu = true;
1491
1492 return vir_emit_def(c, ldtmu);
1493 }
1494
1495 static inline struct qreg
vir_UMUL(struct v3d_compile * c,struct qreg src0,struct qreg src1)1496 vir_UMUL(struct v3d_compile *c, struct qreg src0, struct qreg src1)
1497 {
1498 vir_MULTOP(c, src0, src1);
1499 return vir_UMUL24(c, src0, src1);
1500 }
1501
1502 static inline struct qreg
vir_TLBU_COLOR_READ(struct v3d_compile * c,uint32_t config)1503 vir_TLBU_COLOR_READ(struct v3d_compile *c, uint32_t config)
1504 {
1505 assert((config & 0xffffff00) == 0xffffff00);
1506
1507 struct qinst *ldtlb = vir_add_inst(V3D_QPU_A_NOP, c->undef,
1508 c->undef, c->undef);
1509 ldtlb->qpu.sig.ldtlbu = true;
1510 ldtlb->uniform = vir_get_uniform_index(c, QUNIFORM_CONSTANT, config);
1511 return vir_emit_def(c, ldtlb);
1512 }
1513
1514 static inline struct qreg
vir_TLB_COLOR_READ(struct v3d_compile * c)1515 vir_TLB_COLOR_READ(struct v3d_compile *c)
1516 {
1517 struct qinst *ldtlb = vir_add_inst(V3D_QPU_A_NOP, c->undef,
1518 c->undef, c->undef);
1519 ldtlb->qpu.sig.ldtlb = true;
1520 return vir_emit_def(c, ldtlb);
1521 }
1522
1523 static inline struct qinst *
vir_BRANCH(struct v3d_compile * c,enum v3d_qpu_branch_cond cond)1524 vir_BRANCH(struct v3d_compile *c, enum v3d_qpu_branch_cond cond)
1525 {
1526 /* The actual uniform_data value will be set at scheduling time */
1527 return vir_emit_nondef(c, vir_branch_inst(c, cond));
1528 }
1529
1530 #define vir_for_each_block(block, c) \
1531 list_for_each_entry(struct qblock, block, &c->blocks, link)
1532
1533 #define vir_for_each_block_rev(block, c) \
1534 list_for_each_entry_rev(struct qblock, block, &c->blocks, link)
1535
1536 /* Loop over the non-NULL members of the successors array. */
1537 #define vir_for_each_successor(succ, block) \
1538 for (struct qblock *succ = block->successors[0]; \
1539 succ != NULL; \
1540 succ = (succ == block->successors[1] ? NULL : \
1541 block->successors[1]))
1542
1543 #define vir_for_each_inst(inst, block) \
1544 list_for_each_entry(struct qinst, inst, &block->instructions, link)
1545
1546 #define vir_for_each_inst_rev(inst, block) \
1547 list_for_each_entry_rev(struct qinst, inst, &block->instructions, link)
1548
1549 #define vir_for_each_inst_safe(inst, block) \
1550 list_for_each_entry_safe(struct qinst, inst, &block->instructions, link)
1551
1552 #define vir_for_each_inst_inorder(inst, c) \
1553 vir_for_each_block(_block, c) \
1554 vir_for_each_inst(inst, _block)
1555
1556 #define vir_for_each_inst_inorder_safe(inst, c) \
1557 vir_for_each_block(_block, c) \
1558 vir_for_each_inst_safe(inst, _block)
1559
1560 #endif /* V3D_COMPILER_H */
1561