1 /*
2 * Copyright © 2011 Intel Corporation
3 * SPDX-License-Identifier: MIT
4 */
5
6 #include "brw_fs.h"
7 #include "brw_eu.h"
8 #include "brw_nir.h"
9 #include "brw_private.h"
10 #include "dev/intel_debug.h"
11
12 using namespace brw;
13
14 extern "C" const unsigned *
brw_compile_vs(const struct brw_compiler * compiler,struct brw_compile_vs_params * params)15 brw_compile_vs(const struct brw_compiler *compiler,
16 struct brw_compile_vs_params *params)
17 {
18 struct nir_shader *nir = params->base.nir;
19 const struct brw_vs_prog_key *key = params->key;
20 struct brw_vs_prog_data *prog_data = params->prog_data;
21 const bool debug_enabled =
22 brw_should_print_shader(nir, params->base.debug_flag ?
23 params->base.debug_flag : DEBUG_VS);
24
25 prog_data->base.base.stage = MESA_SHADER_VERTEX;
26 prog_data->base.base.ray_queries = nir->info.ray_queries;
27 prog_data->base.base.total_scratch = 0;
28
29 brw_nir_apply_key(nir, compiler, &key->base, 8);
30
31 prog_data->inputs_read = nir->info.inputs_read;
32 prog_data->double_inputs_read = nir->info.vs.double_inputs;
33
34 brw_nir_lower_vs_inputs(nir);
35 brw_nir_lower_vue_outputs(nir);
36 brw_postprocess_nir(nir, compiler, debug_enabled,
37 key->base.robust_flags);
38
39 prog_data->base.clip_distance_mask =
40 ((1 << nir->info.clip_distance_array_size) - 1);
41 prog_data->base.cull_distance_mask =
42 ((1 << nir->info.cull_distance_array_size) - 1) <<
43 nir->info.clip_distance_array_size;
44
45 unsigned nr_attribute_slots = util_bitcount64(prog_data->inputs_read);
46
47 /* gl_VertexID and gl_InstanceID are system values, but arrive via an
48 * incoming vertex attribute. So, add an extra slot.
49 */
50 if (BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FIRST_VERTEX) ||
51 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BASE_INSTANCE) ||
52 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE) ||
53 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_INSTANCE_ID)) {
54 nr_attribute_slots++;
55 }
56
57 /* gl_DrawID and IsIndexedDraw share its very own vec4 */
58 if (BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_DRAW_ID) ||
59 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_IS_INDEXED_DRAW)) {
60 nr_attribute_slots++;
61 }
62
63 if (BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_IS_INDEXED_DRAW))
64 prog_data->uses_is_indexed_draw = true;
65
66 if (BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FIRST_VERTEX))
67 prog_data->uses_firstvertex = true;
68
69 if (BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BASE_INSTANCE))
70 prog_data->uses_baseinstance = true;
71
72 if (BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE))
73 prog_data->uses_vertexid = true;
74
75 if (BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_INSTANCE_ID))
76 prog_data->uses_instanceid = true;
77
78 if (BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_DRAW_ID))
79 prog_data->uses_drawid = true;
80
81 prog_data->base.urb_read_length = DIV_ROUND_UP(nr_attribute_slots, 2);
82 prog_data->nr_attribute_slots = nr_attribute_slots;
83
84 /* Since vertex shaders reuse the same VUE entry for inputs and outputs
85 * (overwriting the original contents), we need to make sure the size is
86 * the larger of the two.
87 */
88 const unsigned vue_entries =
89 MAX2(nr_attribute_slots, (unsigned)prog_data->base.vue_map.num_slots);
90
91 prog_data->base.urb_entry_size = DIV_ROUND_UP(vue_entries, 4);
92
93 if (unlikely(debug_enabled)) {
94 fprintf(stderr, "VS Output ");
95 brw_print_vue_map(stderr, &prog_data->base.vue_map, MESA_SHADER_VERTEX);
96 }
97
98 const unsigned dispatch_width = compiler->devinfo->ver >= 20 ? 16 : 8;
99 prog_data->base.dispatch_mode = INTEL_DISPATCH_MODE_SIMD8;
100
101 fs_visitor v(compiler, ¶ms->base, &key->base,
102 &prog_data->base.base, nir, dispatch_width,
103 params->base.stats != NULL, debug_enabled);
104 if (!v.run_vs()) {
105 params->base.error_str =
106 ralloc_strdup(params->base.mem_ctx, v.fail_msg);
107 return NULL;
108 }
109
110 assert(v.payload().num_regs % reg_unit(compiler->devinfo) == 0);
111 prog_data->base.base.dispatch_grf_start_reg =
112 v.payload().num_regs / reg_unit(compiler->devinfo);
113
114 fs_generator g(compiler, ¶ms->base,
115 &prog_data->base.base,
116 MESA_SHADER_VERTEX);
117 if (unlikely(debug_enabled)) {
118 const char *debug_name =
119 ralloc_asprintf(params->base.mem_ctx, "%s vertex shader %s",
120 nir->info.label ? nir->info.label :
121 "unnamed",
122 nir->info.name);
123
124 g.enable_debug(debug_name);
125 }
126 g.generate_code(v.cfg, dispatch_width, v.shader_stats,
127 v.performance_analysis.require(), params->base.stats);
128 g.add_const_data(nir->constant_data, nir->constant_data_size);
129
130 return g.get_assembly();
131 }
132