1 /*
2 * Copyright © 2019 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "compiler/nir/nir_builder.h"
25 #include "brw_nir.h"
26
27 /**
28 * We need to compute alpha to coverage dithering manually in shader
29 * and replace sample mask store with the bitwise-AND of sample mask and
30 * alpha to coverage dithering.
31 *
32 * The following formula is used to compute final sample mask:
33 * m = int(16.0 * clamp(src0_alpha, 0.0, 1.0))
34 * dither_mask = 0x1111 * ((0xfea80 >> (m & ~3)) & 0xf) |
35 * 0x0808 * (m & 2) | 0x0100 * (m & 1)
36 * sample_mask = sample_mask & dither_mask
37 *
38 * It gives a number of ones proportional to the alpha for 2, 4, 8 or 16
39 * least significant bits of the result:
40 * 0.0000 0000000000000000
41 * 0.0625 0000000100000000
42 * 0.1250 0001000000010000
43 * 0.1875 0001000100010000
44 * 0.2500 1000100010001000
45 * 0.3125 1000100110001000
46 * 0.3750 1001100010011000
47 * 0.4375 1001100110011000
48 * 0.5000 1010101010101010
49 * 0.5625 1010101110101010
50 * 0.6250 1011101010111010
51 * 0.6875 1011101110111010
52 * 0.7500 1110111011101110
53 * 0.8125 1110111111101110
54 * 0.8750 1111111011111110
55 * 0.9375 1111111111111110
56 * 1.0000 1111111111111111
57 */
58 static nir_def *
build_dither_mask(nir_builder * b,nir_def * color)59 build_dither_mask(nir_builder *b, nir_def *color)
60 {
61 assert(color->num_components == 4);
62 nir_def *alpha = nir_channel(b, color, 3);
63
64 nir_def *m =
65 nir_f2i32(b, nir_fmul_imm(b, nir_fsat(b, alpha), 16.0));
66
67 nir_def *part_a =
68 nir_iand_imm(b, nir_ushr(b, nir_imm_int(b, 0xfea80),
69 nir_iand_imm(b, m, ~3)),
70 0xf);
71
72 nir_def *part_b = nir_iand_imm(b, m, 2);
73 nir_def *part_c = nir_iand_imm(b, m, 1);
74
75 return nir_ior(b, nir_imul_imm(b, part_a, 0x1111),
76 nir_ior(b, nir_imul_imm(b, part_b, 0x0808),
77 nir_imul_imm(b, part_c, 0x0100)));
78 }
79
80 bool
brw_nir_lower_alpha_to_coverage(nir_shader * shader,const struct brw_wm_prog_key * key,const struct brw_wm_prog_data * prog_data)81 brw_nir_lower_alpha_to_coverage(nir_shader *shader,
82 const struct brw_wm_prog_key *key,
83 const struct brw_wm_prog_data *prog_data)
84 {
85 assert(shader->info.stage == MESA_SHADER_FRAGMENT);
86 assert(key->alpha_to_coverage != BRW_NEVER);
87
88 nir_function_impl *impl = nir_shader_get_entrypoint(shader);
89
90 const uint64_t outputs_written = shader->info.outputs_written;
91 if (!(outputs_written & BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK)) ||
92 !(outputs_written & (BITFIELD64_BIT(FRAG_RESULT_COLOR) |
93 BITFIELD64_BIT(FRAG_RESULT_DATA0))))
94 goto skip;
95
96 nir_intrinsic_instr *sample_mask_write = NULL;
97 nir_intrinsic_instr *color0_write = NULL;
98 bool sample_mask_write_first = false;
99
100 nir_foreach_block(block, impl) {
101 nir_foreach_instr_safe(instr, block) {
102 if (instr->type != nir_instr_type_intrinsic)
103 continue;
104
105 nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
106 if (intrin->intrinsic != nir_intrinsic_store_output)
107 continue;
108
109 /* We call nir_lower_io_to_temporaries to lower FS outputs to
110 * temporaries with a copy at the end so this should be the last
111 * block in the shader.
112 */
113 assert(block->cf_node.parent == &impl->cf_node);
114 assert(nir_cf_node_is_last(&block->cf_node));
115
116 /* See store_output in fs_visitor::nir_emit_fs_intrinsic */
117 const unsigned store_offset = nir_src_as_uint(intrin->src[1]);
118 const unsigned driver_location = nir_intrinsic_base(intrin) +
119 SET_FIELD(store_offset, BRW_NIR_FRAG_OUTPUT_LOCATION);
120
121 /* Extract the FRAG_RESULT */
122 const unsigned location =
123 GET_FIELD(driver_location, BRW_NIR_FRAG_OUTPUT_LOCATION);
124
125 if (location == FRAG_RESULT_SAMPLE_MASK) {
126 assert(sample_mask_write == NULL);
127 sample_mask_write = intrin;
128 sample_mask_write_first = (color0_write == NULL);
129 }
130
131 if (location == FRAG_RESULT_COLOR ||
132 location == FRAG_RESULT_DATA0) {
133 assert(color0_write == NULL);
134 color0_write = intrin;
135 }
136 }
137 }
138
139 /* It's possible that shader_info may be out-of-date and the writes to
140 * either gl_SampleMask or the first color value may have been removed.
141 * This can happen if, for instance a nir_undef is written to the
142 * color value. In that case, just bail and don't do anything rather
143 * than crashing.
144 */
145 if (color0_write == NULL || sample_mask_write == NULL)
146 goto skip;
147
148 /* It's possible that the color value isn't actually a vec4. In this case,
149 * assuming an alpha of 1.0 and letting the sample mask pass through
150 * unaltered seems like the kindest thing to do to apps.
151 */
152 nir_def *color0 = color0_write->src[0].ssa;
153 if (color0->num_components < 4)
154 goto skip;
155
156 nir_def *sample_mask = sample_mask_write->src[0].ssa;
157
158 if (sample_mask_write_first) {
159 /* If the sample mask write comes before the write to color0, we need
160 * to move it because it's going to use the value from color0 to
161 * compute the sample mask.
162 */
163 nir_instr_remove(&sample_mask_write->instr);
164 nir_instr_insert(nir_after_instr(&color0_write->instr),
165 &sample_mask_write->instr);
166 }
167
168 nir_builder b = nir_builder_at(nir_before_instr(&sample_mask_write->instr));
169
170 /* Combine dither_mask and the gl_SampleMask value */
171 nir_def *dither_mask = build_dither_mask(&b, color0);
172 dither_mask = nir_iand(&b, sample_mask, dither_mask);
173
174 if (key->alpha_to_coverage == BRW_SOMETIMES) {
175 nir_def *push_flags =
176 nir_load_uniform(&b, 1, 32, nir_imm_int(&b, prog_data->msaa_flags_param * 4));
177 nir_def *alpha_to_coverage =
178 nir_test_mask(&b, push_flags, INTEL_MSAA_FLAG_ALPHA_TO_COVERAGE);
179 dither_mask = nir_bcsel(&b, alpha_to_coverage,
180 dither_mask, sample_mask_write->src[0].ssa);
181 }
182
183 nir_src_rewrite(&sample_mask_write->src[0], dither_mask);
184
185 nir_metadata_preserve(impl, nir_metadata_block_index |
186 nir_metadata_dominance);
187 return true;
188
189 skip:
190 nir_metadata_preserve(impl, nir_metadata_all);
191 return false;
192 }
193