1 /*
2 * Copyright (C) 2009 Nicolai Haehnle.
3 *
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sublicense, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial
16 * portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 */
27
28 #ifndef RADEON_OPCODES_H
29 #define RADEON_OPCODES_H
30
31 #include <assert.h>
32
33 /**
34 * Opcodes understood by the Radeon compiler.
35 */
36 typedef enum {
37 RC_OPCODE_NOP = 0,
38 RC_OPCODE_ILLEGAL_OPCODE,
39
40 /** vec4 instruction: dst.c = src0.c + src1.c; */
41 RC_OPCODE_ADD,
42
43 /** special instruction: load address register
44 * dst.x = floor(src.x), where dst must be an address register */
45 RC_OPCODE_ARL,
46
47 /** special instruction: load address register with round
48 * dst.x = round(src.x), where dst must be an address register */
49 RC_OPCODE_ARR,
50
51 /** vec4 instruction: dst.c = src0.c < 0.0 ? src1.c : src2.c */
52 RC_OPCODE_CMP,
53
54 /** vec4 instruction: dst.c = src2.c > 0.5 ? src0.c : src1.c */
55 RC_OPCODE_CND,
56
57 /** scalar instruction: dst = cos(src0.x) */
58 RC_OPCODE_COS,
59
60 /** special instruction: take vec4 partial derivative in X direction
61 * dst.c = d src0.c / dx */
62 RC_OPCODE_DDX,
63
64 /** special instruction: take vec4 partial derivative in Y direction
65 * dst.c = d src0.c / dy */
66 RC_OPCODE_DDY,
67
68 /** scalar instruction: dst = src0.x*src1.x + src0.y*src1.y */
69 RC_OPCODE_DP2,
70
71 /** scalar instruction: dst = src0.x*src1.x + src0.y*src1.y + src0.z*src1.z */
72 RC_OPCODE_DP3,
73
74 /** scalar instruction: dst = src0.x*src1.x + src0.y*src1.y + src0.z*src1.z + src0.w*src1.w */
75 RC_OPCODE_DP4,
76
77 /** special instruction, see ARB_fragment_program */
78 RC_OPCODE_DST,
79
80 /** scalar instruction: dst = 2**src0.x */
81 RC_OPCODE_EX2,
82
83 /** special instruction, see ARB_vertex_program */
84 RC_OPCODE_EXP,
85
86 /** vec4 instruction: dst.c = src0.c - floor(src0.c) */
87 RC_OPCODE_FRC,
88
89 /** special instruction: stop execution if any component of src0 is negative */
90 RC_OPCODE_KIL,
91
92 /** scalar instruction: dst = log_2(src0.x) */
93 RC_OPCODE_LG2,
94
95 /** special instruction, see ARB_vertex_program */
96 RC_OPCODE_LIT,
97
98 /** special instruction, see ARB_vertex_program */
99 RC_OPCODE_LOG,
100
101 /** vec4 instruction: dst.c = src0.c*src1.c + src2.c */
102 RC_OPCODE_MAD,
103
104 /** vec4 instruction: dst.c = max(src0.c, src1.c) */
105 RC_OPCODE_MAX,
106
107 /** vec4 instruction: dst.c = min(src0.c, src1.c) */
108 RC_OPCODE_MIN,
109
110 /** vec4 instruction: dst.c = src0.c */
111 RC_OPCODE_MOV,
112
113 /** vec4 instruction: dst.c = src0.c*src1.c */
114 RC_OPCODE_MUL,
115
116 /** scalar instruction: dst = src0.x ** src1.x */
117 RC_OPCODE_POW,
118
119 /** scalar instruction: dst = 1 / src0.x */
120 RC_OPCODE_RCP,
121
122 /** vec4 instruction: dst.c = floor(src0.c + 0.5) */
123 RC_OPCODE_ROUND,
124
125 /** scalar instruction: dst = 1 / sqrt(src0.x) */
126 RC_OPCODE_RSQ,
127
128 /** vec4 instruction: dst.c = (src0.c == src1.c) ? 1.0 : 0.0 */
129 RC_OPCODE_SEQ,
130
131 /** vec4 instruction: dst.c = (src0.c >= src1.c) ? 1.0 : 0.0 */
132 RC_OPCODE_SGE,
133
134 /** scalar instruction: dst = sin(src0.x) */
135 RC_OPCODE_SIN,
136
137 /** vec4 instruction: dst.c = (src0.c < src1.c) ? 1.0 : 0.0 */
138 RC_OPCODE_SLT,
139
140 /** vec4 instruction: dst.c = (src0.c != src1.c) ? 1.0 : 0.0 */
141 RC_OPCODE_SNE,
142
143 RC_OPCODE_TEX,
144 RC_OPCODE_TXB,
145 RC_OPCODE_TXD,
146 RC_OPCODE_TXL,
147 RC_OPCODE_TXP,
148
149 /** branch instruction:
150 * If src0.x != 0.0, continue with the next instruction;
151 * otherwise, jump to matching RC_OPCODE_ELSE or RC_OPCODE_ENDIF.
152 */
153 RC_OPCODE_IF,
154
155 /** branch instruction: jump to matching RC_OPCODE_ENDIF */
156 RC_OPCODE_ELSE,
157
158 /** branch instruction: has no effect */
159 RC_OPCODE_ENDIF,
160
161 RC_OPCODE_BGNLOOP,
162
163 RC_OPCODE_BRK,
164
165 RC_OPCODE_ENDLOOP,
166
167 RC_OPCODE_CONT,
168
169 /** special instruction, used in R300-R500 fragment program pair instructions
170 * indicates that the result of the alpha operation shall be replicated
171 * across all other channels */
172 RC_OPCODE_REPL_ALPHA,
173
174 /** special instruction, used in R300-R500 fragment programs
175 * to indicate the start of a block of texture instructions that
176 * can run simultaneously. */
177 RC_OPCODE_BEGIN_TEX,
178
179 /** Stop execution of the shader (GLSL discard) */
180 RC_OPCODE_KILP,
181
182 /* Vertex shader CF Instructions */
183 RC_ME_PRED_SEQ,
184 RC_ME_PRED_SGT,
185 RC_ME_PRED_SGE,
186 RC_ME_PRED_SNEQ,
187 RC_ME_PRED_SET_CLR,
188 RC_ME_PRED_SET_INV,
189 RC_ME_PRED_SET_POP,
190 RC_ME_PRED_SET_RESTORE,
191
192 RC_VE_PRED_SEQ_PUSH,
193 RC_VE_PRED_SGT_PUSH,
194 RC_VE_PRED_SGE_PUSH,
195 RC_VE_PRED_SNEQ_PUSH,
196
197 MAX_RC_OPCODE
198 } rc_opcode;
199
200
201 struct rc_opcode_info {
202 rc_opcode Opcode;
203 const char * Name;
204
205 /** true if the instruction reads from a texture.
206 *
207 * \note This is false for the KIL instruction, even though KIL is
208 * a texture instruction from a hardware point of view. */
209 unsigned int HasTexture:1;
210
211 unsigned int NumSrcRegs:2;
212 unsigned int HasDstReg:1;
213
214 /** true if this instruction affects control flow */
215 unsigned int IsFlowControl:1;
216
217 /** true if this is a vector instruction that operates on components in parallel
218 * without any cross-component interaction */
219 unsigned int IsComponentwise:1;
220
221 /** true if this instruction sources only its operands X components
222 * to compute one result which is smeared across all output channels */
223 unsigned int IsStandardScalar:1;
224 };
225
226 extern const struct rc_opcode_info rc_opcodes[MAX_RC_OPCODE];
227
rc_get_opcode_info(rc_opcode opcode)228 static inline const struct rc_opcode_info * rc_get_opcode_info(rc_opcode opcode)
229 {
230 assert((unsigned int)opcode < MAX_RC_OPCODE);
231 assert(rc_opcodes[opcode].Opcode == opcode);
232
233 return &rc_opcodes[opcode];
234 }
235
236 struct rc_instruction;
237
238 void rc_compute_sources_for_writemask(
239 const struct rc_instruction *inst,
240 unsigned int writemask,
241 unsigned int *srcmasks);
242
243 #endif /* RADEON_OPCODES_H */
244