1 /*
2 * Copyright © 2015-2016 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "elk_compiler.h"
25 #include "elk_shader.h"
26 #include "elk_eu.h"
27 #include "elk_nir.h"
28 #include "elk_nir_options.h"
29 #include "dev/intel_debug.h"
30 #include "compiler/nir/nir.h"
31 #include "util/u_debug.h"
32
33 struct elk_compiler *
elk_compiler_create(void * mem_ctx,const struct intel_device_info * devinfo)34 elk_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo)
35 {
36 assert(devinfo->ver <= 8);
37
38 struct elk_compiler *compiler = rzalloc(mem_ctx, struct elk_compiler);
39
40 compiler->devinfo = devinfo;
41
42 elk_init_isa_info(&compiler->isa, devinfo);
43
44 elk_fs_alloc_reg_sets(compiler);
45 if (devinfo->ver < 8)
46 elk_vec4_alloc_reg_set(compiler);
47
48 compiler->precise_trig = debug_get_bool_option("INTEL_PRECISE_TRIG", false);
49
50 compiler->use_tcs_multi_patch = devinfo->ver >= 12;
51
52 /* Default to the sampler since that's what we've done since forever */
53 compiler->indirect_ubos_use_sampler = true;
54
55 compiler->lower_dpas = devinfo->verx10 < 125 ||
56 intel_device_info_is_mtl(devinfo) ||
57 (intel_device_info_is_arl(devinfo) &&
58 devinfo->platform != INTEL_PLATFORM_ARL_H) ||
59 debug_get_bool_option("INTEL_LOWER_DPAS", false);
60
61 /* There is no vec4 mode on Gfx10+, and we don't use it at all on Gfx8+. */
62 for (int i = MESA_SHADER_VERTEX; i < MESA_ALL_SHADER_STAGES; i++) {
63 compiler->scalar_stage[i] = devinfo->ver >= 8 ||
64 i == MESA_SHADER_FRAGMENT || i == MESA_SHADER_COMPUTE;
65 }
66
67 nir_lower_int64_options int64_options =
68 nir_lower_imul64 |
69 nir_lower_isign64 |
70 nir_lower_divmod64 |
71 nir_lower_imul_high64 |
72 nir_lower_find_lsb64 |
73 nir_lower_ufind_msb64 |
74 nir_lower_bit_count64;
75 nir_lower_doubles_options fp64_options =
76 nir_lower_drcp |
77 nir_lower_dsqrt |
78 nir_lower_drsq |
79 nir_lower_dtrunc |
80 nir_lower_dfloor |
81 nir_lower_dceil |
82 nir_lower_dfract |
83 nir_lower_dround_even |
84 nir_lower_dmod |
85 nir_lower_dsub |
86 nir_lower_ddiv;
87
88 if (!devinfo->has_64bit_float || INTEL_DEBUG(DEBUG_SOFT64))
89 fp64_options |= nir_lower_fp64_full_software;
90 if (!devinfo->has_64bit_int)
91 int64_options |= (nir_lower_int64_options)~0;
92
93 /* The Bspec's section titled "Instruction_multiply[DevBDW+]" claims that
94 * destination type can be Quadword and source type Doubleword for Gfx8 and
95 * Gfx9. So, lower 64 bit multiply instruction on rest of the platforms.
96 */
97 if (devinfo->ver < 8 || devinfo->ver > 9)
98 int64_options |= nir_lower_imul_2x32_64;
99
100 /* We want the GLSL compiler to emit code that uses condition codes */
101 for (int i = 0; i < MESA_ALL_SHADER_STAGES; i++) {
102 struct nir_shader_compiler_options *nir_options =
103 rzalloc(compiler, struct nir_shader_compiler_options);
104 bool is_scalar = compiler->scalar_stage[i];
105 if (is_scalar) {
106 *nir_options = elk_scalar_nir_options;
107 int64_options |= nir_lower_usub_sat64;
108 } else {
109 *nir_options = elk_vector_nir_options;
110 }
111
112 /* Prior to Gfx6, there are no three source operations, and Gfx11 loses
113 * LRP.
114 */
115 nir_options->lower_ffma16 = devinfo->ver < 6;
116 nir_options->lower_ffma32 = devinfo->ver < 6;
117 nir_options->lower_ffma64 = devinfo->ver < 6;
118 nir_options->lower_flrp32 = devinfo->ver < 6 || devinfo->ver >= 11;
119 nir_options->lower_fpow = devinfo->ver >= 12;
120
121 nir_options->has_bfe = devinfo->ver >= 7;
122 nir_options->has_bfm = devinfo->ver >= 7;
123 nir_options->has_bfi = devinfo->ver >= 7;
124
125 nir_options->has_rotate16 = devinfo->ver >= 11;
126 nir_options->has_rotate32 = devinfo->ver >= 11;
127 nir_options->lower_bitfield_reverse = devinfo->ver < 7;
128 nir_options->lower_find_lsb = devinfo->ver < 7;
129 nir_options->lower_ifind_msb = devinfo->ver < 7;
130 nir_options->has_iadd3 = devinfo->verx10 >= 125;
131
132 nir_options->has_sdot_4x8 = devinfo->ver >= 12;
133 nir_options->has_udot_4x8 = devinfo->ver >= 12;
134 nir_options->has_sudot_4x8 = devinfo->ver >= 12;
135 nir_options->has_sdot_4x8_sat = devinfo->ver >= 12;
136 nir_options->has_udot_4x8_sat = devinfo->ver >= 12;
137 nir_options->has_sudot_4x8_sat = devinfo->ver >= 12;
138
139 nir_options->lower_int64_options = int64_options;
140 nir_options->lower_doubles_options = fp64_options;
141
142 nir_options->unify_interfaces = i < MESA_SHADER_FRAGMENT;
143
144 nir_options->force_indirect_unrolling |=
145 elk_nir_no_indirect_mask(compiler, i);
146 nir_options->force_indirect_unrolling_sampler = devinfo->ver < 7;
147
148 if (compiler->use_tcs_multi_patch) {
149 /* TCS MULTI_PATCH mode has multiple patches per subgroup */
150 nir_options->divergence_analysis_options &=
151 ~nir_divergence_single_patch_per_tcs_subgroup;
152 }
153
154 if (devinfo->ver < 12)
155 nir_options->divergence_analysis_options |=
156 nir_divergence_single_prim_per_subgroup;
157
158 compiler->nir_options[i] = nir_options;
159 }
160
161 return compiler;
162 }
163
164 static void
insert_u64_bit(uint64_t * val,bool add)165 insert_u64_bit(uint64_t *val, bool add)
166 {
167 *val = (*val << 1) | !!add;
168 }
169
170 uint64_t
elk_get_compiler_config_value(const struct elk_compiler * compiler)171 elk_get_compiler_config_value(const struct elk_compiler *compiler)
172 {
173 uint64_t config = 0;
174 unsigned bits = 0;
175
176 insert_u64_bit(&config, compiler->precise_trig);
177 bits++;
178 insert_u64_bit(&config, compiler->lower_dpas);
179 bits++;
180
181 uint64_t mask = DEBUG_DISK_CACHE_MASK;
182 bits += util_bitcount64(mask);
183
184 u_foreach_bit64(bit, mask)
185 insert_u64_bit(&config, INTEL_DEBUG(1ULL << bit));
186
187 mask = SIMD_DISK_CACHE_MASK;
188 bits += util_bitcount64(mask);
189
190 u_foreach_bit64(bit, mask)
191 insert_u64_bit(&config, (intel_simd & (1ULL << bit)) != 0);
192
193 mask = 3;
194 bits += util_bitcount64(mask);
195
196 assert(bits <= util_bitcount64(UINT64_MAX));
197
198 return config;
199 }
200
201 unsigned
elk_prog_data_size(gl_shader_stage stage)202 elk_prog_data_size(gl_shader_stage stage)
203 {
204 static const size_t stage_sizes[] = {
205 [MESA_SHADER_VERTEX] = sizeof(struct elk_vs_prog_data),
206 [MESA_SHADER_TESS_CTRL] = sizeof(struct elk_tcs_prog_data),
207 [MESA_SHADER_TESS_EVAL] = sizeof(struct elk_tes_prog_data),
208 [MESA_SHADER_GEOMETRY] = sizeof(struct elk_gs_prog_data),
209 [MESA_SHADER_FRAGMENT] = sizeof(struct elk_wm_prog_data),
210 [MESA_SHADER_COMPUTE] = sizeof(struct elk_cs_prog_data),
211 };
212 assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes));
213 return stage_sizes[stage];
214 }
215
216 unsigned
elk_prog_key_size(gl_shader_stage stage)217 elk_prog_key_size(gl_shader_stage stage)
218 {
219 static const size_t stage_sizes[] = {
220 [MESA_SHADER_VERTEX] = sizeof(struct elk_vs_prog_key),
221 [MESA_SHADER_TESS_CTRL] = sizeof(struct elk_tcs_prog_key),
222 [MESA_SHADER_TESS_EVAL] = sizeof(struct elk_tes_prog_key),
223 [MESA_SHADER_GEOMETRY] = sizeof(struct elk_gs_prog_key),
224 [MESA_SHADER_FRAGMENT] = sizeof(struct elk_wm_prog_key),
225 [MESA_SHADER_COMPUTE] = sizeof(struct elk_cs_prog_key),
226 };
227 assert((int)stage >= 0 && stage < ARRAY_SIZE(stage_sizes));
228 return stage_sizes[stage];
229 }
230
231 void
elk_write_shader_relocs(const struct elk_isa_info * isa,void * program,const struct elk_stage_prog_data * prog_data,struct elk_shader_reloc_value * values,unsigned num_values)232 elk_write_shader_relocs(const struct elk_isa_info *isa,
233 void *program,
234 const struct elk_stage_prog_data *prog_data,
235 struct elk_shader_reloc_value *values,
236 unsigned num_values)
237 {
238 for (unsigned i = 0; i < prog_data->num_relocs; i++) {
239 assert(prog_data->relocs[i].offset % 8 == 0);
240 void *dst = program + prog_data->relocs[i].offset;
241 for (unsigned j = 0; j < num_values; j++) {
242 if (prog_data->relocs[i].id == values[j].id) {
243 uint32_t value = values[j].value + prog_data->relocs[i].delta;
244 switch (prog_data->relocs[i].type) {
245 case ELK_SHADER_RELOC_TYPE_U32:
246 *(uint32_t *)dst = value;
247 break;
248 case ELK_SHADER_RELOC_TYPE_MOV_IMM:
249 elk_update_reloc_imm(isa, dst, value);
250 break;
251 default:
252 unreachable("Invalid relocation type");
253 }
254 break;
255 }
256 }
257 }
258 }
259