1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file elk_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 #include "elk_eu.h"
31 #include "elk_disasm_info.h"
32 #include "elk_fs.h"
33 #include "elk_cfg.h"
34 #include "dev/intel_debug.h"
35 #include "util/mesa-sha1.h"
36 #include "util/half_float.h"
37
38 static enum elk_reg_file
elk_file_from_reg(elk_fs_reg * reg)39 elk_file_from_reg(elk_fs_reg *reg)
40 {
41 switch (reg->file) {
42 case ARF:
43 return ELK_ARCHITECTURE_REGISTER_FILE;
44 case FIXED_GRF:
45 case VGRF:
46 return ELK_GENERAL_REGISTER_FILE;
47 case MRF:
48 return ELK_MESSAGE_REGISTER_FILE;
49 case IMM:
50 return ELK_IMMEDIATE_VALUE;
51 case BAD_FILE:
52 case ATTR:
53 case UNIFORM:
54 unreachable("not reached");
55 }
56 return ELK_ARCHITECTURE_REGISTER_FILE;
57 }
58
59 static struct elk_reg
elk_reg_from_fs_reg(const struct intel_device_info * devinfo,elk_fs_inst * inst,elk_fs_reg * reg,bool compressed)60 elk_reg_from_fs_reg(const struct intel_device_info *devinfo, elk_fs_inst *inst,
61 elk_fs_reg *reg, bool compressed)
62 {
63 struct elk_reg elk_reg;
64
65 switch (reg->file) {
66 case MRF:
67 assert((reg->nr & ~ELK_MRF_COMPR4) < ELK_MAX_MRF(devinfo->ver));
68 FALLTHROUGH;
69 case VGRF:
70 if (reg->stride == 0) {
71 elk_reg = elk_vec1_reg(elk_file_from_reg(reg), reg->nr, 0);
72 } else {
73 /* From the Haswell PRM:
74 *
75 * "VertStride must be used to cross GRF register boundaries. This
76 * rule implies that elements within a 'Width' cannot cross GRF
77 * boundaries."
78 *
79 * The maximum width value that could satisfy this restriction is:
80 */
81 const unsigned reg_width = REG_SIZE / (reg->stride * type_sz(reg->type));
82
83 /* Because the hardware can only split source regions at a whole
84 * multiple of width during decompression (i.e. vertically), clamp
85 * the value obtained above to the physical execution size of a
86 * single decompressed chunk of the instruction:
87 */
88 const unsigned phys_width = compressed ? inst->exec_size / 2 :
89 inst->exec_size;
90
91 const unsigned max_hw_width = 16;
92
93 /* XXX - The equation above is strictly speaking not correct on
94 * hardware that supports unbalanced GRF writes -- On Gfx9+
95 * each decompressed chunk of the instruction may have a
96 * different execution size when the number of components
97 * written to each destination GRF is not the same.
98 */
99 if (reg->stride > 4) {
100 assert(reg != &inst->dst);
101 assert(reg->stride * type_sz(reg->type) <= REG_SIZE);
102 elk_reg = elk_vecn_reg(1, elk_file_from_reg(reg), reg->nr, 0);
103 elk_reg = stride(elk_reg, reg->stride, 1, 0);
104 } else {
105 const unsigned width = MIN3(reg_width, phys_width, max_hw_width);
106 elk_reg = elk_vecn_reg(width, elk_file_from_reg(reg), reg->nr, 0);
107 elk_reg = stride(elk_reg, width * reg->stride, width, reg->stride);
108 }
109
110 if (devinfo->verx10 == 70) {
111 /* From the IvyBridge PRM (EU Changes by Processor Generation, page 13):
112 * "Each DF (Double Float) operand uses an element size of 4 rather
113 * than 8 and all regioning parameters are twice what the values
114 * would be based on the true element size: ExecSize, Width,
115 * HorzStride, and VertStride. Each DF operand uses a pair of
116 * channels and all masking and swizzing should be adjusted
117 * appropriately."
118 *
119 * From the IvyBridge PRM (Special Requirements for Handling Double
120 * Precision Data Types, page 71):
121 * "In Align1 mode, all regioning parameters like stride, execution
122 * size, and width must use the syntax of a pair of packed
123 * floats. The offsets for these data types must be 64-bit
124 * aligned. The execution size and regioning parameters are in terms
125 * of floats."
126 *
127 * Summarized: when handling DF-typed arguments, ExecSize,
128 * VertStride, and Width must be doubled.
129 *
130 * It applies to BayTrail too.
131 */
132 if (type_sz(reg->type) == 8) {
133 elk_reg.width++;
134 if (elk_reg.vstride > 0)
135 elk_reg.vstride++;
136 assert(elk_reg.hstride == ELK_HORIZONTAL_STRIDE_1);
137 }
138
139 /* When converting from DF->F, we set the destination stride to 2
140 * because each d2f conversion implicitly writes 2 floats, being
141 * the first one the converted value. IVB/BYT actually writes two
142 * F components per SIMD channel, and every other component is
143 * filled with garbage.
144 */
145 if (reg == &inst->dst && get_exec_type_size(inst) == 8 &&
146 type_sz(inst->dst.type) < 8) {
147 assert(elk_reg.hstride > ELK_HORIZONTAL_STRIDE_1);
148 elk_reg.hstride--;
149 }
150 }
151 }
152
153 elk_reg = retype(elk_reg, reg->type);
154 elk_reg = byte_offset(elk_reg, reg->offset);
155 elk_reg.abs = reg->abs;
156 elk_reg.negate = reg->negate;
157 break;
158 case ARF:
159 case FIXED_GRF:
160 case IMM:
161 assert(reg->offset == 0);
162 elk_reg = reg->as_elk_reg();
163 break;
164 case BAD_FILE:
165 /* Probably unused. */
166 elk_reg = elk_null_reg();
167 break;
168 case ATTR:
169 case UNIFORM:
170 unreachable("not reached");
171 }
172
173 /* On HSW+, scalar DF sources can be accessed using the normal <0,1,0>
174 * region, but on IVB and BYT DF regions must be programmed in terms of
175 * floats. A <0,2,1> region accomplishes this.
176 */
177 if (devinfo->verx10 == 70 &&
178 type_sz(reg->type) == 8 &&
179 elk_reg.vstride == ELK_VERTICAL_STRIDE_0 &&
180 elk_reg.width == ELK_WIDTH_1 &&
181 elk_reg.hstride == ELK_HORIZONTAL_STRIDE_0) {
182 elk_reg.width = ELK_WIDTH_2;
183 elk_reg.hstride = ELK_HORIZONTAL_STRIDE_1;
184 }
185
186 return elk_reg;
187 }
188
elk_fs_generator(const struct elk_compiler * compiler,const struct elk_compile_params * params,struct elk_stage_prog_data * prog_data,bool runtime_check_aads_emit,gl_shader_stage stage)189 elk_fs_generator::elk_fs_generator(const struct elk_compiler *compiler,
190 const struct elk_compile_params *params,
191 struct elk_stage_prog_data *prog_data,
192 bool runtime_check_aads_emit,
193 gl_shader_stage stage)
194
195 : compiler(compiler), params(params),
196 devinfo(compiler->devinfo),
197 prog_data(prog_data), dispatch_width(0),
198 runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false),
199 shader_name(NULL), stage(stage), mem_ctx(params->mem_ctx)
200 {
201 p = rzalloc(mem_ctx, struct elk_codegen);
202 elk_init_codegen(&compiler->isa, p, mem_ctx);
203
204 /* In the FS code generator, we are very careful to ensure that we always
205 * set the right execution size so we don't need the EU code to "help" us
206 * by trying to infer it. Sometimes, it infers the wrong thing.
207 */
208 p->automatic_exec_sizes = false;
209 }
210
~elk_fs_generator()211 elk_fs_generator::~elk_fs_generator()
212 {
213 }
214
215 class ip_record : public exec_node {
216 public:
217 DECLARE_RALLOC_CXX_OPERATORS(ip_record)
218
ip_record(int ip)219 ip_record(int ip)
220 {
221 this->ip = ip;
222 }
223
224 int ip;
225 };
226
227 bool
patch_halt_jumps()228 elk_fs_generator::patch_halt_jumps()
229 {
230 if (this->discard_halt_patches.is_empty())
231 return false;
232
233 int scale = elk_jump_scale(p->devinfo);
234
235 if (devinfo->ver >= 6) {
236 /* There is a somewhat strange undocumented requirement of using
237 * HALT, according to the simulator. If some channel has HALTed to
238 * a particular UIP, then by the end of the program, every channel
239 * must have HALTed to that UIP. Furthermore, the tracking is a
240 * stack, so you can't do the final halt of a UIP after starting
241 * halting to a new UIP.
242 *
243 * Symptoms of not emitting this instruction on actual hardware
244 * included GPU hangs and sparkly rendering on the piglit discard
245 * tests.
246 */
247 elk_inst *last_halt = elk_HALT(p);
248 elk_inst_set_uip(p->devinfo, last_halt, 1 * scale);
249 elk_inst_set_jip(p->devinfo, last_halt, 1 * scale);
250 }
251
252 int ip = p->nr_insn;
253
254 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
255 elk_inst *patch = &p->store[patch_ip->ip];
256
257 assert(elk_inst_opcode(p->isa, patch) == ELK_OPCODE_HALT);
258 if (devinfo->ver >= 6) {
259 /* HALT takes a half-instruction distance from the pre-incremented IP. */
260 elk_inst_set_uip(p->devinfo, patch, (ip - patch_ip->ip) * scale);
261 } else {
262 elk_set_src1(p, patch, elk_imm_d((ip - patch_ip->ip) * scale));
263 }
264 }
265
266 this->discard_halt_patches.make_empty();
267
268 if (devinfo->ver < 6) {
269 /* From the g965 PRM:
270 *
271 * "As DMask is not automatically reloaded into AMask upon completion
272 * of this instruction, software has to manually restore AMask upon
273 * completion."
274 *
275 * DMask lives in the bottom 16 bits of sr0.1.
276 */
277 elk_inst *reset = elk_MOV(p, elk_mask_reg(ELK_AMASK),
278 retype(elk_sr0_reg(1), ELK_REGISTER_TYPE_UW));
279 elk_inst_set_exec_size(devinfo, reset, ELK_EXECUTE_1);
280 elk_inst_set_mask_control(devinfo, reset, ELK_MASK_DISABLE);
281 elk_inst_set_qtr_control(devinfo, reset, ELK_COMPRESSION_NONE);
282 elk_inst_set_thread_control(devinfo, reset, ELK_THREAD_SWITCH);
283 }
284
285 if (devinfo->ver == 4 && devinfo->platform != INTEL_PLATFORM_G4X) {
286 /* From the g965 PRM:
287 *
288 * "[DevBW, DevCL] Erratum: The subfields in mask stack register are
289 * reset to zero during graphics reset, however, they are not
290 * initialized at thread dispatch. These subfields will retain the
291 * values from the previous thread. Software should make sure the
292 * mask stack is empty (reset to zero) before terminating the thread.
293 * In case that this is not practical, software may have to reset the
294 * mask stack at the beginning of each kernel, which will impact the
295 * performance."
296 *
297 * Luckily we can rely on:
298 *
299 * "[DevBW, DevCL] This register access restriction is not
300 * applicable, hardware does ensure execution pipeline coherency,
301 * when a mask stack register is used as an explicit source and/or
302 * destination."
303 */
304 elk_push_insn_state(p);
305 elk_set_default_mask_control(p, ELK_MASK_DISABLE);
306 elk_set_default_compression_control(p, ELK_COMPRESSION_NONE);
307
308 elk_set_default_exec_size(p, ELK_EXECUTE_2);
309 elk_MOV(p, vec2(elk_mask_stack_depth_reg(0)), elk_imm_uw(0));
310
311 elk_set_default_exec_size(p, ELK_EXECUTE_16);
312 /* Reset the if stack. */
313 elk_MOV(p, retype(elk_mask_stack_reg(0), ELK_REGISTER_TYPE_UW),
314 elk_imm_uw(0));
315
316 elk_pop_insn_state(p);
317 }
318
319 return true;
320 }
321
322 void
generate_send(elk_fs_inst * inst,struct elk_reg dst,struct elk_reg desc,struct elk_reg ex_desc,struct elk_reg payload,struct elk_reg payload2)323 elk_fs_generator::generate_send(elk_fs_inst *inst,
324 struct elk_reg dst,
325 struct elk_reg desc,
326 struct elk_reg ex_desc,
327 struct elk_reg payload,
328 struct elk_reg payload2)
329 {
330 const bool dst_is_null = dst.file == ELK_ARCHITECTURE_REGISTER_FILE &&
331 dst.nr == ELK_ARF_NULL;
332 const unsigned rlen = dst_is_null ? 0 : inst->size_written / REG_SIZE;
333
334 uint32_t desc_imm = inst->desc |
335 elk_message_desc(devinfo, inst->mlen, rlen, inst->header_size);
336
337 uint32_t ex_desc_imm = inst->ex_desc |
338 elk_message_ex_desc(devinfo, inst->ex_mlen);
339
340 if (ex_desc.file != ELK_IMMEDIATE_VALUE || ex_desc.ud || ex_desc_imm ||
341 inst->send_ex_desc_scratch) {
342 /* If we have any sort of extended descriptor, then we need SENDS. This
343 * also covers the dual-payload case because ex_mlen goes in ex_desc.
344 */
345 elk_send_indirect_split_message(p, inst->sfid, dst, payload, payload2,
346 desc, desc_imm, ex_desc, ex_desc_imm,
347 inst->send_ex_desc_scratch,
348 inst->send_ex_bso, inst->eot);
349 if (inst->check_tdr)
350 elk_inst_set_opcode(p->isa, elk_last_inst,
351 devinfo->ver >= 12 ? ELK_OPCODE_SENDC : ELK_OPCODE_SENDSC);
352 } else {
353 elk_send_indirect_message(p, inst->sfid, dst, payload, desc, desc_imm,
354 inst->eot);
355 if (inst->check_tdr)
356 elk_inst_set_opcode(p->isa, elk_last_inst, ELK_OPCODE_SENDC);
357 }
358 }
359
360 void
fire_fb_write(elk_fs_inst * inst,struct elk_reg payload,struct elk_reg implied_header,GLuint nr)361 elk_fs_generator::fire_fb_write(elk_fs_inst *inst,
362 struct elk_reg payload,
363 struct elk_reg implied_header,
364 GLuint nr)
365 {
366 struct elk_wm_prog_data *prog_data = elk_wm_prog_data(this->prog_data);
367
368 if (devinfo->ver < 6) {
369 elk_push_insn_state(p);
370 elk_set_default_exec_size(p, ELK_EXECUTE_8);
371 elk_set_default_mask_control(p, ELK_MASK_DISABLE);
372 elk_set_default_predicate_control(p, ELK_PREDICATE_NONE);
373 elk_set_default_flag_reg(p, 0, 0);
374 elk_set_default_compression_control(p, ELK_COMPRESSION_NONE);
375 elk_MOV(p, offset(retype(payload, ELK_REGISTER_TYPE_UD), 1),
376 offset(retype(implied_header, ELK_REGISTER_TYPE_UD), 1));
377 elk_pop_insn_state(p);
378 }
379
380 uint32_t msg_control = elk_fb_write_msg_control(inst, prog_data);
381
382 /* We assume render targets start at 0, because headerless FB write
383 * messages set "Render Target Index" to 0. Using a different binding
384 * table index would make it impossible to use headerless messages.
385 */
386 const uint32_t surf_index = inst->target;
387
388 elk_inst *insn = elk_fb_WRITE(p,
389 payload,
390 retype(implied_header, ELK_REGISTER_TYPE_UW),
391 msg_control,
392 surf_index,
393 nr,
394 0,
395 inst->eot,
396 inst->last_rt,
397 inst->header_size != 0);
398
399 if (devinfo->ver >= 6)
400 elk_inst_set_rt_slot_group(devinfo, insn, inst->group / 16);
401 }
402
403 void
generate_fb_write(elk_fs_inst * inst,struct elk_reg payload)404 elk_fs_generator::generate_fb_write(elk_fs_inst *inst, struct elk_reg payload)
405 {
406 assert(devinfo->ver < 7);
407
408 elk_set_default_predicate_control(p, ELK_PREDICATE_NONE);
409 elk_set_default_flag_reg(p, 0, 0);
410
411 const struct elk_reg implied_header =
412 devinfo->ver < 6 ? payload : elk_null_reg();
413
414 if (inst->base_mrf >= 0)
415 payload = elk_message_reg(inst->base_mrf);
416
417 if (!runtime_check_aads_emit) {
418 fire_fb_write(inst, payload, implied_header, inst->mlen);
419 } else {
420 /* This can only happen in gen < 6 */
421 assert(devinfo->ver < 6);
422
423 struct elk_reg v1_null_ud = vec1(retype(elk_null_reg(), ELK_REGISTER_TYPE_UD));
424
425 /* Check runtime bit to detect if we have to send AA data or not */
426 elk_push_insn_state(p);
427 elk_set_default_compression_control(p, ELK_COMPRESSION_NONE);
428 elk_set_default_exec_size(p, ELK_EXECUTE_1);
429 elk_AND(p,
430 v1_null_ud,
431 retype(elk_vec1_grf(1, 6), ELK_REGISTER_TYPE_UD),
432 elk_imm_ud(1<<26));
433 elk_inst_set_cond_modifier(p->devinfo, elk_last_inst, ELK_CONDITIONAL_NZ);
434
435 int jmp = elk_JMPI(p, elk_imm_ud(0), ELK_PREDICATE_NORMAL) - p->store;
436 elk_pop_insn_state(p);
437 {
438 /* Don't send AA data */
439 fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
440 }
441 elk_land_fwd_jump(p, jmp);
442 fire_fb_write(inst, payload, implied_header, inst->mlen);
443 }
444 }
445
446 void
generate_fb_read(elk_fs_inst * inst,struct elk_reg dst,struct elk_reg payload)447 elk_fs_generator::generate_fb_read(elk_fs_inst *inst, struct elk_reg dst,
448 struct elk_reg payload)
449 {
450 assert(inst->size_written % REG_SIZE == 0);
451 struct elk_wm_prog_data *prog_data = elk_wm_prog_data(this->prog_data);
452 /* We assume that render targets start at binding table index 0. */
453 const unsigned surf_index = inst->target;
454
455 elk_gfx9_fb_READ(p, dst, payload, surf_index,
456 inst->header_size, inst->size_written / REG_SIZE,
457 prog_data->persample_dispatch);
458 }
459
460 void
generate_mov_indirect(elk_fs_inst * inst,struct elk_reg dst,struct elk_reg reg,struct elk_reg indirect_byte_offset)461 elk_fs_generator::generate_mov_indirect(elk_fs_inst *inst,
462 struct elk_reg dst,
463 struct elk_reg reg,
464 struct elk_reg indirect_byte_offset)
465 {
466 assert(indirect_byte_offset.type == ELK_REGISTER_TYPE_UD);
467 assert(indirect_byte_offset.file == ELK_GENERAL_REGISTER_FILE);
468 assert(!reg.abs && !reg.negate);
469
470 /* Gen12.5 adds the following region restriction:
471 *
472 * "Vx1 and VxH indirect addressing for Float, Half-Float, Double-Float
473 * and Quad-Word data must not be used."
474 *
475 * We require the source and destination types to match so stomp to an
476 * unsigned integer type.
477 */
478 assert(reg.type == dst.type);
479 reg.type = dst.type = elk_reg_type_from_bit_size(type_sz(reg.type) * 8,
480 ELK_REGISTER_TYPE_UD);
481
482 unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr;
483
484 if (indirect_byte_offset.file == ELK_IMMEDIATE_VALUE) {
485 imm_byte_offset += indirect_byte_offset.ud;
486
487 reg.nr = imm_byte_offset / REG_SIZE;
488 reg.subnr = imm_byte_offset % REG_SIZE;
489 if (type_sz(reg.type) > 4 && !devinfo->has_64bit_float) {
490 elk_MOV(p, subscript(dst, ELK_REGISTER_TYPE_D, 0),
491 subscript(reg, ELK_REGISTER_TYPE_D, 0));
492 elk_set_default_swsb(p, tgl_swsb_null());
493 elk_MOV(p, subscript(dst, ELK_REGISTER_TYPE_D, 1),
494 subscript(reg, ELK_REGISTER_TYPE_D, 1));
495 } else {
496 elk_MOV(p, dst, reg);
497 }
498 } else {
499 /* Prior to Broadwell, there are only 8 address registers. */
500 assert(inst->exec_size <= 8 || devinfo->ver >= 8);
501
502 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
503 struct elk_reg addr = vec8(elk_address_reg(0));
504
505 /* Whether we can use destination dependency control without running the
506 * risk of a hang if an instruction gets shot down.
507 */
508 const bool use_dep_ctrl = !inst->predicate &&
509 inst->exec_size == dispatch_width;
510 elk_inst *insn;
511
512 /* The destination stride of an instruction (in bytes) must be greater
513 * than or equal to the size of the rest of the instruction. Since the
514 * address register is of type UW, we can't use a D-type instruction.
515 * In order to get around this, re retype to UW and use a stride.
516 */
517 indirect_byte_offset =
518 retype(spread(indirect_byte_offset, 2), ELK_REGISTER_TYPE_UW);
519
520 /* There are a number of reasons why we don't use the base offset here.
521 * One reason is that the field is only 9 bits which means we can only
522 * use it to access the first 16 GRFs. Also, from the Haswell PRM
523 * section "Register Region Restrictions":
524 *
525 * "The lower bits of the AddressImmediate must not overflow to
526 * change the register address. The lower 5 bits of Address
527 * Immediate when added to lower 5 bits of address register gives
528 * the sub-register offset. The upper bits of Address Immediate
529 * when added to upper bits of address register gives the register
530 * address. Any overflow from sub-register offset is dropped."
531 *
532 * Since the indirect may cause us to cross a register boundary, this
533 * makes the base offset almost useless. We could try and do something
534 * clever where we use a actual base offset if base_offset % 32 == 0 but
535 * that would mean we were generating different code depending on the
536 * base offset. Instead, for the sake of consistency, we'll just do the
537 * add ourselves. This restriction is only listed in the Haswell PRM
538 * but empirical testing indicates that it applies on all older
539 * generations and is lifted on Broadwell.
540 *
541 * In the end, while base_offset is nice to look at in the generated
542 * code, using it saves us 0 instructions and would require quite a bit
543 * of case-by-case work. It's just not worth it.
544 *
545 * Due to a hardware bug some platforms (particularly Gfx11+) seem to
546 * require the address components of all channels to be valid whether or
547 * not they're active, which causes issues if we use VxH addressing
548 * under non-uniform control-flow. We can easily work around that by
549 * initializing the whole address register with a pipelined NoMask MOV
550 * instruction.
551 */
552 if (devinfo->ver >= 7) {
553 insn = elk_MOV(p, addr, elk_imm_uw(imm_byte_offset));
554 elk_inst_set_mask_control(devinfo, insn, ELK_MASK_DISABLE);
555 elk_inst_set_pred_control(devinfo, insn, ELK_PREDICATE_NONE);
556 if (devinfo->ver >= 12)
557 elk_set_default_swsb(p, tgl_swsb_null());
558 else
559 elk_inst_set_no_dd_clear(devinfo, insn, use_dep_ctrl);
560 }
561
562 insn = elk_ADD(p, addr, indirect_byte_offset, elk_imm_uw(imm_byte_offset));
563 if (devinfo->ver >= 12)
564 elk_set_default_swsb(p, tgl_swsb_regdist(1));
565 else if (devinfo->ver >= 7)
566 elk_inst_set_no_dd_check(devinfo, insn, use_dep_ctrl);
567
568 if (type_sz(reg.type) > 4 &&
569 ((devinfo->verx10 == 70) ||
570 devinfo->platform == INTEL_PLATFORM_CHV || intel_device_info_is_9lp(devinfo) ||
571 !devinfo->has_64bit_float || devinfo->verx10 >= 125)) {
572 /* IVB has an issue (which we found empirically) where it reads two
573 * address register components per channel for indirectly addressed
574 * 64-bit sources.
575 *
576 * From the Cherryview PRM Vol 7. "Register Region Restrictions":
577 *
578 * "When source or destination datatype is 64b or operation is
579 * integer DWord multiply, indirect addressing must not be used."
580 *
581 * To work around both of these, we do two integer MOVs insead of one
582 * 64-bit MOV. Because no double value should ever cross a register
583 * boundary, it's safe to use the immediate offset in the indirect
584 * here to handle adding 4 bytes to the offset and avoid the extra
585 * ADD to the register file.
586 */
587 elk_MOV(p, subscript(dst, ELK_REGISTER_TYPE_D, 0),
588 retype(elk_VxH_indirect(0, 0), ELK_REGISTER_TYPE_D));
589 elk_set_default_swsb(p, tgl_swsb_null());
590 elk_MOV(p, subscript(dst, ELK_REGISTER_TYPE_D, 1),
591 retype(elk_VxH_indirect(0, 4), ELK_REGISTER_TYPE_D));
592 } else {
593 struct elk_reg ind_src = elk_VxH_indirect(0, 0);
594
595 elk_inst *mov = elk_MOV(p, dst, retype(ind_src, reg.type));
596
597 if (devinfo->ver == 6 && dst.file == ELK_MESSAGE_REGISTER_FILE &&
598 !inst->get_next()->is_tail_sentinel() &&
599 ((elk_fs_inst *)inst->get_next())->mlen > 0) {
600 /* From the Sandybridge PRM:
601 *
602 * "[Errata: DevSNB(SNB)] If MRF register is updated by any
603 * instruction that “indexed/indirect” source AND is followed
604 * by a send, the instruction requires a “Switch”. This is to
605 * avoid race condition where send may dispatch before MRF is
606 * updated."
607 */
608 elk_inst_set_thread_control(devinfo, mov, ELK_THREAD_SWITCH);
609 }
610 }
611 }
612 }
613
614 void
generate_shuffle(elk_fs_inst * inst,struct elk_reg dst,struct elk_reg src,struct elk_reg idx)615 elk_fs_generator::generate_shuffle(elk_fs_inst *inst,
616 struct elk_reg dst,
617 struct elk_reg src,
618 struct elk_reg idx)
619 {
620 assert(src.file == ELK_GENERAL_REGISTER_FILE);
621 assert(!src.abs && !src.negate);
622
623 /* Ivy bridge has some strange behavior that makes this a real pain to
624 * implement for 64-bit values so we just don't bother.
625 */
626 assert((devinfo->verx10 >= 75 && devinfo->has_64bit_float) ||
627 type_sz(src.type) <= 4);
628
629 /* Gen12.5 adds the following region restriction:
630 *
631 * "Vx1 and VxH indirect addressing for Float, Half-Float, Double-Float
632 * and Quad-Word data must not be used."
633 *
634 * We require the source and destination types to match so stomp to an
635 * unsigned integer type.
636 */
637 assert(src.type == dst.type);
638 src.type = dst.type = elk_reg_type_from_bit_size(type_sz(src.type) * 8,
639 ELK_REGISTER_TYPE_UD);
640
641 /* Because we're using the address register, we're limited to 8-wide
642 * execution on gfx7. On gfx8, we're limited to 16-wide by the address
643 * register file and 8-wide for 64-bit types. We could try and make this
644 * instruction splittable higher up in the compiler but that gets weird
645 * because it reads all of the channels regardless of execution size. It's
646 * easier just to split it here.
647 */
648 const unsigned lower_width =
649 devinfo->ver <= 7 || element_sz(src) > 4 || element_sz(dst) > 4 ? 8 :
650 MIN2(16, inst->exec_size);
651
652 elk_set_default_exec_size(p, cvt(lower_width) - 1);
653 for (unsigned group = 0; group < inst->exec_size; group += lower_width) {
654 elk_set_default_group(p, group);
655
656 if ((src.vstride == 0 && src.hstride == 0) ||
657 idx.file == ELK_IMMEDIATE_VALUE) {
658 /* Trivial, the source is already uniform or the index is a constant.
659 * We will typically not get here if the optimizer is doing its job,
660 * but asserting would be mean.
661 */
662 const unsigned i = idx.file == ELK_IMMEDIATE_VALUE ? idx.ud : 0;
663 struct elk_reg group_src = stride(suboffset(src, i), 0, 1, 0);
664 struct elk_reg group_dst = suboffset(dst, group << (dst.hstride - 1));
665 elk_MOV(p, group_dst, group_src);
666 } else {
667 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
668 struct elk_reg addr = vec8(elk_address_reg(0));
669
670 struct elk_reg group_idx = suboffset(idx, group);
671
672 if (lower_width == 8 && group_idx.width == ELK_WIDTH_16) {
673 /* Things get grumpy if the register is too wide. */
674 group_idx.width--;
675 group_idx.vstride--;
676 }
677
678 assert(type_sz(group_idx.type) <= 4);
679 if (type_sz(group_idx.type) == 4) {
680 /* The destination stride of an instruction (in bytes) must be
681 * greater than or equal to the size of the rest of the
682 * instruction. Since the address register is of type UW, we
683 * can't use a D-type instruction. In order to get around this,
684 * re retype to UW and use a stride.
685 */
686 group_idx = retype(spread(group_idx, 2), ELK_REGISTER_TYPE_W);
687 }
688
689 uint32_t src_start_offset = src.nr * REG_SIZE + src.subnr;
690
691 /* From the Haswell PRM:
692 *
693 * "When a sequence of NoDDChk and NoDDClr are used, the last
694 * instruction that completes the scoreboard clear must have a
695 * non-zero execution mask. This means, if any kind of predication
696 * can change the execution mask or channel enable of the last
697 * instruction, the optimization must be avoided. This is to
698 * avoid instructions being shot down the pipeline when no writes
699 * are required."
700 *
701 * Whenever predication is enabled or the instructions being emitted
702 * aren't the full width, it's possible that it will be run with zero
703 * channels enabled so we can't use dependency control without
704 * running the risk of a hang if an instruction gets shot down.
705 */
706 const bool use_dep_ctrl = !inst->predicate &&
707 lower_width == dispatch_width;
708 elk_inst *insn;
709
710 /* Due to a hardware bug some platforms (particularly Gfx11+) seem
711 * to require the address components of all channels to be valid
712 * whether or not they're active, which causes issues if we use VxH
713 * addressing under non-uniform control-flow. We can easily work
714 * around that by initializing the whole address register with a
715 * pipelined NoMask MOV instruction.
716 */
717 insn = elk_MOV(p, addr, elk_imm_uw(src_start_offset));
718 elk_inst_set_mask_control(devinfo, insn, ELK_MASK_DISABLE);
719 elk_inst_set_pred_control(devinfo, insn, ELK_PREDICATE_NONE);
720 if (devinfo->ver >= 12)
721 elk_set_default_swsb(p, tgl_swsb_null());
722 else
723 elk_inst_set_no_dd_clear(devinfo, insn, use_dep_ctrl);
724
725 /* Take into account the component size and horizontal stride. */
726 assert(src.vstride == src.hstride + src.width);
727 insn = elk_SHL(p, addr, group_idx,
728 elk_imm_uw(util_logbase2(type_sz(src.type)) +
729 src.hstride - 1));
730 if (devinfo->ver >= 12)
731 elk_set_default_swsb(p, tgl_swsb_regdist(1));
732 else
733 elk_inst_set_no_dd_check(devinfo, insn, use_dep_ctrl);
734
735 /* Add on the register start offset */
736 elk_ADD(p, addr, addr, elk_imm_uw(src_start_offset));
737 elk_MOV(p, suboffset(dst, group << (dst.hstride - 1)),
738 retype(elk_VxH_indirect(0, 0), src.type));
739 }
740
741 elk_set_default_swsb(p, tgl_swsb_null());
742 }
743 }
744
745 void
generate_quad_swizzle(const elk_fs_inst * inst,struct elk_reg dst,struct elk_reg src,unsigned swiz)746 elk_fs_generator::generate_quad_swizzle(const elk_fs_inst *inst,
747 struct elk_reg dst, struct elk_reg src,
748 unsigned swiz)
749 {
750 /* Requires a quad. */
751 assert(inst->exec_size >= 4);
752
753 if (src.file == ELK_IMMEDIATE_VALUE ||
754 has_scalar_region(src)) {
755 /* The value is uniform across all channels */
756 elk_MOV(p, dst, src);
757
758 } else if (devinfo->ver < 11 && type_sz(src.type) == 4) {
759 /* This only works on 8-wide 32-bit values */
760 assert(inst->exec_size == 8);
761 assert(src.hstride == ELK_HORIZONTAL_STRIDE_1);
762 assert(src.vstride == src.width + 1);
763 elk_set_default_access_mode(p, ELK_ALIGN_16);
764 struct elk_reg swiz_src = stride(src, 4, 4, 1);
765 swiz_src.swizzle = swiz;
766 elk_MOV(p, dst, swiz_src);
767
768 } else {
769 assert(src.hstride == ELK_HORIZONTAL_STRIDE_1);
770 assert(src.vstride == src.width + 1);
771 const struct elk_reg src_0 = suboffset(src, ELK_GET_SWZ(swiz, 0));
772
773 switch (swiz) {
774 case ELK_SWIZZLE_XXXX:
775 case ELK_SWIZZLE_YYYY:
776 case ELK_SWIZZLE_ZZZZ:
777 case ELK_SWIZZLE_WWWW:
778 elk_MOV(p, dst, stride(src_0, 4, 4, 0));
779 break;
780
781 case ELK_SWIZZLE_XXZZ:
782 case ELK_SWIZZLE_YYWW:
783 elk_MOV(p, dst, stride(src_0, 2, 2, 0));
784 break;
785
786 case ELK_SWIZZLE_XYXY:
787 case ELK_SWIZZLE_ZWZW:
788 assert(inst->exec_size == 4);
789 elk_MOV(p, dst, stride(src_0, 0, 2, 1));
790 break;
791
792 default:
793 assert(inst->force_writemask_all);
794 elk_set_default_exec_size(p, cvt(inst->exec_size / 4) - 1);
795
796 for (unsigned c = 0; c < 4; c++) {
797 elk_inst *insn = elk_MOV(
798 p, stride(suboffset(dst, c),
799 4 * inst->dst.stride, 1, 4 * inst->dst.stride),
800 stride(suboffset(src, ELK_GET_SWZ(swiz, c)), 4, 1, 0));
801
802 if (devinfo->ver < 12) {
803 elk_inst_set_no_dd_clear(devinfo, insn, c < 3);
804 elk_inst_set_no_dd_check(devinfo, insn, c > 0);
805 }
806
807 elk_set_default_swsb(p, tgl_swsb_null());
808 }
809
810 break;
811 }
812 }
813 }
814
815 void
generate_cs_terminate(elk_fs_inst * inst,struct elk_reg payload)816 elk_fs_generator::generate_cs_terminate(elk_fs_inst *inst, struct elk_reg payload)
817 {
818 struct elk_inst *insn;
819
820 insn = elk_next_insn(p, ELK_OPCODE_SEND);
821
822 elk_set_dest(p, insn, retype(elk_null_reg(), ELK_REGISTER_TYPE_UW));
823 elk_set_src0(p, insn, retype(payload, ELK_REGISTER_TYPE_UW));
824 if (devinfo->ver < 12)
825 elk_set_src1(p, insn, elk_imm_ud(0u));
826
827 /* For XeHP and newer send a message to the message gateway to terminate a
828 * compute shader. For older devices, a message is sent to the thread
829 * spawner.
830 */
831 if (devinfo->verx10 >= 125)
832 elk_inst_set_sfid(devinfo, insn, ELK_SFID_MESSAGE_GATEWAY);
833 else
834 elk_inst_set_sfid(devinfo, insn, ELK_SFID_THREAD_SPAWNER);
835 elk_inst_set_mlen(devinfo, insn, 1);
836 elk_inst_set_rlen(devinfo, insn, 0);
837 elk_inst_set_eot(devinfo, insn, inst->eot);
838 elk_inst_set_header_present(devinfo, insn, false);
839
840 elk_inst_set_ts_opcode(devinfo, insn, 0); /* Dereference resource */
841
842 if (devinfo->ver < 11) {
843 elk_inst_set_ts_request_type(devinfo, insn, 0); /* Root thread */
844
845 /* Note that even though the thread has a URB resource associated with it,
846 * we set the "do not dereference URB" bit, because the URB resource is
847 * managed by the fixed-function unit, so it will free it automatically.
848 */
849 elk_inst_set_ts_resource_select(devinfo, insn, 1); /* Do not dereference URB */
850 }
851
852 elk_inst_set_mask_control(devinfo, insn, ELK_MASK_DISABLE);
853 }
854
855 void
generate_barrier(elk_fs_inst *,struct elk_reg src)856 elk_fs_generator::generate_barrier(elk_fs_inst *, struct elk_reg src)
857 {
858 elk_barrier(p, src);
859 if (devinfo->ver >= 12) {
860 elk_set_default_swsb(p, tgl_swsb_null());
861 elk_SYNC(p, TGL_SYNC_BAR);
862 } else {
863 elk_WAIT(p);
864 }
865 }
866
867 bool
generate_linterp(elk_fs_inst * inst,struct elk_reg dst,struct elk_reg * src)868 elk_fs_generator::generate_linterp(elk_fs_inst *inst,
869 struct elk_reg dst, struct elk_reg *src)
870 {
871 /* PLN reads:
872 * / in SIMD16 \
873 * -----------------------------------
874 * | src1+0 | src1+1 | src1+2 | src1+3 |
875 * |-----------------------------------|
876 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
877 * -----------------------------------
878 *
879 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
880 *
881 * -----------------------------------
882 * | src1+0 | src1+1 | src1+2 | src1+3 |
883 * |-----------------------------------|
884 * |(x0, x1)|(y0, y1)| | | in SIMD8
885 * |-----------------------------------|
886 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
887 * -----------------------------------
888 *
889 * See also: emit_interpolation_setup_gfx4().
890 */
891 struct elk_reg delta_x = src[0];
892 struct elk_reg delta_y = offset(src[0], inst->exec_size / 8);
893 struct elk_reg interp = src[1];
894 elk_inst *i[2];
895
896 /* nir_lower_interpolation() will do the lowering to MAD instructions for
897 * us on gfx11+
898 */
899 assert(devinfo->ver < 11);
900
901 if (devinfo->has_pln) {
902 if (devinfo->ver <= 6 && (delta_x.nr & 1) != 0) {
903 /* From the Sandy Bridge PRM Vol. 4, Pt. 2, Section 8.3.53, "Plane":
904 *
905 * "[DevSNB]:<src1> must be even register aligned.
906 *
907 * This restriction is lifted on Ivy Bridge.
908 *
909 * This means that we need to split PLN into LINE+MAC on-the-fly.
910 * Unfortunately, the inputs are laid out for PLN and not LINE+MAC so
911 * we have to split into SIMD8 pieces. For gfx4 (!has_pln), the
912 * coordinate registers are laid out differently so we leave it as a
913 * SIMD16 instruction.
914 */
915 assert(inst->exec_size == 8 || inst->exec_size == 16);
916 assert(inst->group % 16 == 0);
917
918 elk_push_insn_state(p);
919 elk_set_default_exec_size(p, ELK_EXECUTE_8);
920
921 /* Thanks to two accumulators, we can emit all the LINEs and then all
922 * the MACs. This improves parallelism a bit.
923 */
924 for (unsigned g = 0; g < inst->exec_size / 8; g++) {
925 elk_inst *line = elk_LINE(p, elk_null_reg(), interp,
926 offset(delta_x, g * 2));
927 elk_inst_set_group(devinfo, line, inst->group + g * 8);
928
929 /* LINE writes the accumulator automatically on gfx4-5. On Sandy
930 * Bridge and later, we have to explicitly enable it.
931 */
932 if (devinfo->ver >= 6)
933 elk_inst_set_acc_wr_control(p->devinfo, line, true);
934
935 /* elk_set_default_saturate() is called before emitting
936 * instructions, so the saturate bit is set in each instruction,
937 * so we need to unset it on the LINE instructions.
938 */
939 elk_inst_set_saturate(p->devinfo, line, false);
940 }
941
942 for (unsigned g = 0; g < inst->exec_size / 8; g++) {
943 elk_inst *mac = elk_MAC(p, offset(dst, g), suboffset(interp, 1),
944 offset(delta_x, g * 2 + 1));
945 elk_inst_set_group(devinfo, mac, inst->group + g * 8);
946 elk_inst_set_cond_modifier(p->devinfo, mac, inst->conditional_mod);
947 }
948
949 elk_pop_insn_state(p);
950
951 return true;
952 } else {
953 elk_PLN(p, dst, interp, delta_x);
954
955 return false;
956 }
957 } else {
958 i[0] = elk_LINE(p, elk_null_reg(), interp, delta_x);
959 i[1] = elk_MAC(p, dst, suboffset(interp, 1), delta_y);
960
961 elk_inst_set_cond_modifier(p->devinfo, i[1], inst->conditional_mod);
962
963 /* elk_set_default_saturate() is called before emitting instructions, so
964 * the saturate bit is set in each instruction, so we need to unset it on
965 * the first instruction.
966 */
967 elk_inst_set_saturate(p->devinfo, i[0], false);
968
969 return true;
970 }
971 }
972
973 void
generate_tex(elk_fs_inst * inst,struct elk_reg dst,struct elk_reg surface_index,struct elk_reg sampler_index)974 elk_fs_generator::generate_tex(elk_fs_inst *inst, struct elk_reg dst,
975 struct elk_reg surface_index,
976 struct elk_reg sampler_index)
977 {
978 assert(devinfo->ver < 7);
979 assert(inst->size_written % REG_SIZE == 0);
980 int msg_type = -1;
981 uint32_t simd_mode;
982 uint32_t return_format;
983
984 /* Sampler EOT message of less than the dispatch width would kill the
985 * thread prematurely.
986 */
987 assert(!inst->eot || inst->exec_size == dispatch_width);
988
989 switch (dst.type) {
990 case ELK_REGISTER_TYPE_D:
991 return_format = ELK_SAMPLER_RETURN_FORMAT_SINT32;
992 break;
993 case ELK_REGISTER_TYPE_UD:
994 return_format = ELK_SAMPLER_RETURN_FORMAT_UINT32;
995 break;
996 default:
997 return_format = ELK_SAMPLER_RETURN_FORMAT_FLOAT32;
998 break;
999 }
1000
1001 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
1002 * is set as part of the message descriptor. On gfx4, the PRM seems to
1003 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
1004 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
1005 * gone from the message descriptor entirely and you just get UINT32 all
1006 * the time regasrdless. Since we can really only do non-UINT32 on gfx4,
1007 * just stomp it to UINT32 all the time.
1008 */
1009 if (inst->opcode == ELK_SHADER_OPCODE_TXS)
1010 return_format = ELK_SAMPLER_RETURN_FORMAT_UINT32;
1011
1012 switch (inst->exec_size) {
1013 case 8:
1014 simd_mode = ELK_SAMPLER_SIMD_MODE_SIMD8;
1015 break;
1016 case 16:
1017 simd_mode = ELK_SAMPLER_SIMD_MODE_SIMD16;
1018 break;
1019 default:
1020 unreachable("Invalid width for texture instruction");
1021 }
1022
1023 if (devinfo->ver >= 5) {
1024 switch (inst->opcode) {
1025 case ELK_SHADER_OPCODE_TEX:
1026 if (inst->shadow_compare) {
1027 msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
1028 } else {
1029 msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE;
1030 }
1031 break;
1032 case ELK_FS_OPCODE_TXB:
1033 if (inst->shadow_compare) {
1034 msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
1035 } else {
1036 msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_BIAS;
1037 }
1038 break;
1039 case ELK_SHADER_OPCODE_TXL:
1040 if (inst->shadow_compare) {
1041 msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
1042 } else {
1043 msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_LOD;
1044 }
1045 break;
1046 case ELK_SHADER_OPCODE_TXS:
1047 msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
1048 break;
1049 case ELK_SHADER_OPCODE_TXD:
1050 assert(!inst->shadow_compare);
1051 msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
1052 break;
1053 case ELK_SHADER_OPCODE_TXF:
1054 msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_LD;
1055 break;
1056 case ELK_SHADER_OPCODE_TXF_CMS:
1057 msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_LD;
1058 break;
1059 case ELK_SHADER_OPCODE_LOD:
1060 msg_type = GFX5_SAMPLER_MESSAGE_LOD;
1061 break;
1062 case ELK_SHADER_OPCODE_TG4:
1063 assert(devinfo->ver == 6);
1064 assert(!inst->shadow_compare);
1065 msg_type = GFX7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
1066 break;
1067 case ELK_SHADER_OPCODE_SAMPLEINFO:
1068 msg_type = GFX6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
1069 break;
1070 default:
1071 unreachable("not reached");
1072 }
1073 } else {
1074 switch (inst->opcode) {
1075 case ELK_SHADER_OPCODE_TEX:
1076 /* Note that G45 and older determines shadow compare and dispatch width
1077 * from message length for most messages.
1078 */
1079 if (inst->exec_size == 8) {
1080 msg_type = ELK_SAMPLER_MESSAGE_SIMD8_SAMPLE;
1081 if (inst->shadow_compare) {
1082 assert(inst->mlen == 6);
1083 } else {
1084 assert(inst->mlen <= 4);
1085 }
1086 } else {
1087 if (inst->shadow_compare) {
1088 msg_type = ELK_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE;
1089 assert(inst->mlen == 9);
1090 } else {
1091 msg_type = ELK_SAMPLER_MESSAGE_SIMD16_SAMPLE;
1092 assert(inst->mlen <= 7 && inst->mlen % 2 == 1);
1093 }
1094 }
1095 break;
1096 case ELK_FS_OPCODE_TXB:
1097 if (inst->shadow_compare) {
1098 assert(inst->exec_size == 8);
1099 assert(inst->mlen == 6);
1100 msg_type = ELK_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
1101 } else {
1102 assert(inst->mlen == 9);
1103 msg_type = ELK_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
1104 simd_mode = ELK_SAMPLER_SIMD_MODE_SIMD16;
1105 }
1106 break;
1107 case ELK_SHADER_OPCODE_TXL:
1108 if (inst->shadow_compare) {
1109 assert(inst->exec_size == 8);
1110 assert(inst->mlen == 6);
1111 msg_type = ELK_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
1112 } else {
1113 assert(inst->mlen == 9);
1114 msg_type = ELK_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
1115 simd_mode = ELK_SAMPLER_SIMD_MODE_SIMD16;
1116 }
1117 break;
1118 case ELK_SHADER_OPCODE_TXD:
1119 /* There is no sample_d_c message; comparisons are done manually */
1120 assert(inst->exec_size == 8);
1121 assert(inst->mlen == 7 || inst->mlen == 10);
1122 msg_type = ELK_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
1123 break;
1124 case ELK_SHADER_OPCODE_TXF:
1125 assert(inst->mlen <= 9 && inst->mlen % 2 == 1);
1126 msg_type = ELK_SAMPLER_MESSAGE_SIMD16_LD;
1127 simd_mode = ELK_SAMPLER_SIMD_MODE_SIMD16;
1128 break;
1129 case ELK_SHADER_OPCODE_TXS:
1130 assert(inst->mlen == 3);
1131 msg_type = ELK_SAMPLER_MESSAGE_SIMD16_RESINFO;
1132 simd_mode = ELK_SAMPLER_SIMD_MODE_SIMD16;
1133 break;
1134 default:
1135 unreachable("not reached");
1136 }
1137 }
1138 assert(msg_type != -1);
1139
1140 if (simd_mode == ELK_SAMPLER_SIMD_MODE_SIMD16) {
1141 dst = vec16(dst);
1142 }
1143
1144 assert(sampler_index.type == ELK_REGISTER_TYPE_UD);
1145
1146 /* Load the message header if present. If there's a texture offset,
1147 * we need to set it up explicitly and load the offset bitfield.
1148 * Otherwise, we can use an implied move from g0 to the first message reg.
1149 */
1150 struct elk_reg src = elk_null_reg();
1151 if (inst->header_size != 0) {
1152 if (devinfo->ver < 6 && !inst->offset) {
1153 /* Set up an implied move from g0 to the MRF. */
1154 src = retype(elk_vec8_grf(0, 0), ELK_REGISTER_TYPE_UW);
1155 } else {
1156 const tgl_swsb swsb = elk_get_default_swsb(p);
1157 assert(inst->base_mrf != -1);
1158 struct elk_reg header_reg = elk_message_reg(inst->base_mrf);
1159
1160 elk_push_insn_state(p);
1161 elk_set_default_swsb(p, tgl_swsb_src_dep(swsb));
1162 elk_set_default_exec_size(p, ELK_EXECUTE_8);
1163 elk_set_default_mask_control(p, ELK_MASK_DISABLE);
1164 elk_set_default_compression_control(p, ELK_COMPRESSION_NONE);
1165 /* Explicitly set up the message header by copying g0 to the MRF. */
1166 elk_MOV(p, header_reg, elk_vec8_grf(0, 0));
1167 elk_set_default_swsb(p, tgl_swsb_regdist(1));
1168
1169 elk_set_default_exec_size(p, ELK_EXECUTE_1);
1170 if (inst->offset) {
1171 /* Set the offset bits in DWord 2. */
1172 elk_MOV(p, get_element_ud(header_reg, 2),
1173 elk_imm_ud(inst->offset));
1174 }
1175
1176 elk_pop_insn_state(p);
1177 elk_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1));
1178 }
1179 }
1180
1181 assert(surface_index.file == ELK_IMMEDIATE_VALUE);
1182 assert(sampler_index.file == ELK_IMMEDIATE_VALUE);
1183
1184 elk_SAMPLE(p,
1185 retype(dst, ELK_REGISTER_TYPE_UW),
1186 inst->base_mrf,
1187 src,
1188 surface_index.ud,
1189 sampler_index.ud % 16,
1190 msg_type,
1191 inst->size_written / REG_SIZE,
1192 inst->mlen,
1193 inst->header_size != 0,
1194 simd_mode,
1195 return_format);
1196 }
1197
1198
1199 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
1200 * looking like:
1201 *
1202 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
1203 *
1204 * Ideally, we want to produce:
1205 *
1206 * DDX DDY
1207 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
1208 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
1209 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
1210 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
1211 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
1212 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
1213 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
1214 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
1215 *
1216 * and add another set of two more subspans if in 16-pixel dispatch mode.
1217 *
1218 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
1219 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
1220 * pair. But the ideal approximation may impose a huge performance cost on
1221 * sample_d. On at least Haswell, sample_d instruction does some
1222 * optimizations if the same LOD is used for all pixels in the subspan.
1223 *
1224 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
1225 * appropriate swizzling.
1226 */
1227 void
generate_ddx(const elk_fs_inst * inst,struct elk_reg dst,struct elk_reg src)1228 elk_fs_generator::generate_ddx(const elk_fs_inst *inst,
1229 struct elk_reg dst, struct elk_reg src)
1230 {
1231 unsigned vstride, width;
1232
1233 if (devinfo->ver >= 8) {
1234 if (inst->opcode == ELK_FS_OPCODE_DDX_FINE) {
1235 /* produce accurate derivatives */
1236 vstride = ELK_VERTICAL_STRIDE_2;
1237 width = ELK_WIDTH_2;
1238 } else {
1239 /* replicate the derivative at the top-left pixel to other pixels */
1240 vstride = ELK_VERTICAL_STRIDE_4;
1241 width = ELK_WIDTH_4;
1242 }
1243
1244 struct elk_reg src0 = byte_offset(src, type_sz(src.type));;
1245 struct elk_reg src1 = src;
1246
1247 src0.vstride = vstride;
1248 src0.width = width;
1249 src0.hstride = ELK_HORIZONTAL_STRIDE_0;
1250 src1.vstride = vstride;
1251 src1.width = width;
1252 src1.hstride = ELK_HORIZONTAL_STRIDE_0;
1253
1254 elk_ADD(p, dst, src0, negate(src1));
1255 } else {
1256 /* On Haswell and earlier, the region used above appears to not work
1257 * correctly for compressed instructions. At least on Haswell and
1258 * Iron Lake, compressed ALIGN16 instructions do work. Since we
1259 * would have to split to SIMD8 no matter which method we choose, we
1260 * may as well use ALIGN16 on all platforms gfx7 and earlier.
1261 */
1262 struct elk_reg src0 = stride(src, 4, 4, 1);
1263 struct elk_reg src1 = stride(src, 4, 4, 1);
1264 if (inst->opcode == ELK_FS_OPCODE_DDX_FINE) {
1265 src0.swizzle = ELK_SWIZZLE_XXZZ;
1266 src1.swizzle = ELK_SWIZZLE_YYWW;
1267 } else {
1268 src0.swizzle = ELK_SWIZZLE_XXXX;
1269 src1.swizzle = ELK_SWIZZLE_YYYY;
1270 }
1271
1272 elk_push_insn_state(p);
1273 elk_set_default_access_mode(p, ELK_ALIGN_16);
1274 elk_ADD(p, dst, negate(src0), src1);
1275 elk_pop_insn_state(p);
1276 }
1277 }
1278
1279 /* The negate_value boolean is used to negate the derivative computation for
1280 * FBOs, since they place the origin at the upper left instead of the lower
1281 * left.
1282 */
1283 void
generate_ddy(const elk_fs_inst * inst,struct elk_reg dst,struct elk_reg src)1284 elk_fs_generator::generate_ddy(const elk_fs_inst *inst,
1285 struct elk_reg dst, struct elk_reg src)
1286 {
1287 const uint32_t type_size = type_sz(src.type);
1288
1289 if (inst->opcode == ELK_FS_OPCODE_DDY_FINE) {
1290 /* produce accurate derivatives.
1291 *
1292 * From the Broadwell PRM, Volume 7 (3D-Media-GPGPU)
1293 * "Register Region Restrictions", Section "1. Special Restrictions":
1294 *
1295 * "In Align16 mode, the channel selects and channel enables apply to
1296 * a pair of half-floats, because these parameters are defined for
1297 * DWord elements ONLY. This is applicable when both source and
1298 * destination are half-floats."
1299 *
1300 * So for half-float operations we use the Gfx11+ Align1 path. CHV
1301 * inherits its FP16 hardware from SKL, so it is not affected.
1302 */
1303 if (devinfo->ver >= 11 ||
1304 (devinfo->platform == INTEL_PLATFORM_BDW && src.type == ELK_REGISTER_TYPE_HF)) {
1305 src = stride(src, 0, 2, 1);
1306
1307 elk_push_insn_state(p);
1308 elk_set_default_exec_size(p, ELK_EXECUTE_4);
1309 for (uint32_t g = 0; g < inst->exec_size; g += 4) {
1310 elk_set_default_group(p, inst->group + g);
1311 elk_ADD(p, byte_offset(dst, g * type_size),
1312 negate(byte_offset(src, g * type_size)),
1313 byte_offset(src, (g + 2) * type_size));
1314 elk_set_default_swsb(p, tgl_swsb_null());
1315 }
1316 elk_pop_insn_state(p);
1317 } else {
1318 struct elk_reg src0 = stride(src, 4, 4, 1);
1319 struct elk_reg src1 = stride(src, 4, 4, 1);
1320 src0.swizzle = ELK_SWIZZLE_XYXY;
1321 src1.swizzle = ELK_SWIZZLE_ZWZW;
1322
1323 elk_push_insn_state(p);
1324 elk_set_default_access_mode(p, ELK_ALIGN_16);
1325 elk_ADD(p, dst, negate(src0), src1);
1326 elk_pop_insn_state(p);
1327 }
1328 } else {
1329 /* replicate the derivative at the top-left pixel to other pixels */
1330 if (devinfo->ver >= 8) {
1331 struct elk_reg src0 = byte_offset(stride(src, 4, 4, 0), 0 * type_size);
1332 struct elk_reg src1 = byte_offset(stride(src, 4, 4, 0), 2 * type_size);
1333
1334 elk_ADD(p, dst, negate(src0), src1);
1335 } else {
1336 /* On Haswell and earlier, the region used above appears to not work
1337 * correctly for compressed instructions. At least on Haswell and
1338 * Iron Lake, compressed ALIGN16 instructions do work. Since we
1339 * would have to split to SIMD8 no matter which method we choose, we
1340 * may as well use ALIGN16 on all platforms gfx7 and earlier.
1341 */
1342 struct elk_reg src0 = stride(src, 4, 4, 1);
1343 struct elk_reg src1 = stride(src, 4, 4, 1);
1344 src0.swizzle = ELK_SWIZZLE_XXXX;
1345 src1.swizzle = ELK_SWIZZLE_ZZZZ;
1346
1347 elk_push_insn_state(p);
1348 elk_set_default_access_mode(p, ELK_ALIGN_16);
1349 elk_ADD(p, dst, negate(src0), src1);
1350 elk_pop_insn_state(p);
1351 }
1352 }
1353 }
1354
1355 void
generate_halt(elk_fs_inst *)1356 elk_fs_generator::generate_halt(elk_fs_inst *)
1357 {
1358 /* This HALT will be patched up at FB write time to point UIP at the end of
1359 * the program, and at elk_uip_jip() JIP will be set to the end of the
1360 * current block (or the program).
1361 */
1362 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
1363 elk_HALT(p);
1364 }
1365
1366 void
generate_scratch_write(elk_fs_inst * inst,struct elk_reg src)1367 elk_fs_generator::generate_scratch_write(elk_fs_inst *inst, struct elk_reg src)
1368 {
1369 /* The 32-wide messages only respect the first 16-wide half of the channel
1370 * enable signals which are replicated identically for the second group of
1371 * 16 channels, so we cannot use them unless the write is marked
1372 * force_writemask_all.
1373 */
1374 const unsigned lower_size = inst->force_writemask_all ? inst->exec_size :
1375 MIN2(16, inst->exec_size);
1376 const unsigned block_size = 4 * lower_size / REG_SIZE;
1377 const tgl_swsb swsb = elk_get_default_swsb(p);
1378 assert(inst->mlen != 0);
1379
1380 elk_push_insn_state(p);
1381 elk_set_default_exec_size(p, cvt(lower_size) - 1);
1382 elk_set_default_compression(p, lower_size > 8);
1383
1384 for (unsigned i = 0; i < inst->exec_size / lower_size; i++) {
1385 elk_set_default_group(p, inst->group + lower_size * i);
1386
1387 if (i > 0) {
1388 assert(swsb.mode & TGL_SBID_SET);
1389 elk_set_default_swsb(p, tgl_swsb_sbid(TGL_SBID_SRC, swsb.sbid));
1390 } else {
1391 elk_set_default_swsb(p, tgl_swsb_src_dep(swsb));
1392 }
1393
1394 elk_MOV(p, elk_uvec_mrf(lower_size, inst->base_mrf + 1, 0),
1395 retype(offset(src, block_size * i), ELK_REGISTER_TYPE_UD));
1396
1397 elk_set_default_swsb(p, tgl_swsb_dst_dep(swsb, 1));
1398 elk_oword_block_write_scratch(p, elk_message_reg(inst->base_mrf),
1399 block_size,
1400 inst->offset + block_size * REG_SIZE * i);
1401 }
1402
1403 elk_pop_insn_state(p);
1404 }
1405
1406 void
generate_scratch_read(elk_fs_inst * inst,struct elk_reg dst)1407 elk_fs_generator::generate_scratch_read(elk_fs_inst *inst, struct elk_reg dst)
1408 {
1409 assert(inst->exec_size <= 16 || inst->force_writemask_all);
1410 assert(inst->mlen != 0);
1411
1412 elk_oword_block_read_scratch(p, dst, elk_message_reg(inst->base_mrf),
1413 inst->exec_size / 8, inst->offset);
1414 }
1415
1416 void
generate_scratch_read_gfx7(elk_fs_inst * inst,struct elk_reg dst)1417 elk_fs_generator::generate_scratch_read_gfx7(elk_fs_inst *inst, struct elk_reg dst)
1418 {
1419 assert(inst->exec_size <= 16 || inst->force_writemask_all);
1420
1421 elk_gfx7_block_read_scratch(p, dst, inst->exec_size / 8, inst->offset);
1422 }
1423
1424 /* The A32 messages take a buffer base address in header.5:[31:0] (See
1425 * MH1_A32_PSM for typed messages or MH_A32_GO for byte/dword scattered
1426 * and OWord block messages in the SKL PRM Vol. 2d for more details.)
1427 * Unfortunately, there are a number of subtle differences:
1428 *
1429 * For the block read/write messages:
1430 *
1431 * - We always stomp header.2 to fill in the actual scratch address (in
1432 * units of OWORDs) so we don't care what's in there.
1433 *
1434 * - They rely on per-thread scratch space value in header.3[3:0] to do
1435 * bounds checking so that needs to be valid. The upper bits of
1436 * header.3 are ignored, though, so we can copy all of g0.3.
1437 *
1438 * - They ignore header.5[9:0] and assumes the address is 1KB aligned.
1439 *
1440 *
1441 * For the byte/dword scattered read/write messages:
1442 *
1443 * - We want header.2 to be zero because that gets added to the per-channel
1444 * offset in the non-header portion of the message.
1445 *
1446 * - Contrary to what the docs claim, they don't do any bounds checking so
1447 * the value of header.3[3:0] doesn't matter.
1448 *
1449 * - They consider all of header.5 for the base address and header.5[9:0]
1450 * are not ignored. This means that we can't copy g0.5 verbatim because
1451 * g0.5[9:0] contains the FFTID on most platforms. Instead, we have to
1452 * use an AND to mask off the bottom 10 bits.
1453 *
1454 *
1455 * For block messages, just copying g0 gives a valid header because all the
1456 * garbage gets ignored except for header.2 which we stomp as part of message
1457 * setup. For byte/dword scattered messages, we can just zero out the header
1458 * and copy over the bits we need from g0.5. This opcode, however, tries to
1459 * satisfy the requirements of both by starting with 0 and filling out the
1460 * information required by either set of opcodes.
1461 */
1462 void
generate_scratch_header(elk_fs_inst * inst,struct elk_reg dst)1463 elk_fs_generator::generate_scratch_header(elk_fs_inst *inst, struct elk_reg dst)
1464 {
1465 assert(inst->exec_size == 8 && inst->force_writemask_all);
1466 assert(dst.file == ELK_GENERAL_REGISTER_FILE);
1467
1468 dst.type = ELK_REGISTER_TYPE_UD;
1469
1470 elk_inst *insn = elk_MOV(p, dst, elk_imm_ud(0));
1471 if (devinfo->ver >= 12)
1472 elk_set_default_swsb(p, tgl_swsb_null());
1473 else
1474 elk_inst_set_no_dd_clear(p->devinfo, insn, true);
1475
1476 /* Copy the per-thread scratch space size from g0.3[3:0] */
1477 elk_set_default_exec_size(p, ELK_EXECUTE_1);
1478 insn = elk_AND(p, suboffset(dst, 3),
1479 retype(elk_vec1_grf(0, 3), ELK_REGISTER_TYPE_UD),
1480 elk_imm_ud(INTEL_MASK(3, 0)));
1481 if (devinfo->ver < 12) {
1482 elk_inst_set_no_dd_clear(p->devinfo, insn, true);
1483 elk_inst_set_no_dd_check(p->devinfo, insn, true);
1484 }
1485
1486 /* Copy the scratch base address from g0.5[31:10] */
1487 insn = elk_AND(p, suboffset(dst, 5),
1488 retype(elk_vec1_grf(0, 5), ELK_REGISTER_TYPE_UD),
1489 elk_imm_ud(INTEL_MASK(31, 10)));
1490 if (devinfo->ver < 12)
1491 elk_inst_set_no_dd_check(p->devinfo, insn, true);
1492 }
1493
1494 void
generate_uniform_pull_constant_load(elk_fs_inst * inst,struct elk_reg dst,struct elk_reg index,struct elk_reg offset)1495 elk_fs_generator::generate_uniform_pull_constant_load(elk_fs_inst *inst,
1496 struct elk_reg dst,
1497 struct elk_reg index,
1498 struct elk_reg offset)
1499 {
1500 assert(type_sz(dst.type) == 4);
1501 assert(inst->mlen != 0);
1502
1503 assert(index.file == ELK_IMMEDIATE_VALUE &&
1504 index.type == ELK_REGISTER_TYPE_UD);
1505 uint32_t surf_index = index.ud;
1506
1507 assert(offset.file == ELK_IMMEDIATE_VALUE &&
1508 offset.type == ELK_REGISTER_TYPE_UD);
1509 uint32_t read_offset = offset.ud;
1510
1511 elk_oword_block_read(p, dst, elk_message_reg(inst->base_mrf),
1512 read_offset, surf_index);
1513 }
1514
1515 void
generate_varying_pull_constant_load_gfx4(elk_fs_inst * inst,struct elk_reg dst,struct elk_reg index)1516 elk_fs_generator::generate_varying_pull_constant_load_gfx4(elk_fs_inst *inst,
1517 struct elk_reg dst,
1518 struct elk_reg index)
1519 {
1520 assert(devinfo->ver < 7); /* Should use the gfx7 variant. */
1521 assert(inst->header_size != 0);
1522 assert(inst->mlen);
1523
1524 assert(index.file == ELK_IMMEDIATE_VALUE &&
1525 index.type == ELK_REGISTER_TYPE_UD);
1526 uint32_t surf_index = index.ud;
1527
1528 uint32_t simd_mode, rlen, msg_type;
1529 if (inst->exec_size == 16) {
1530 simd_mode = ELK_SAMPLER_SIMD_MODE_SIMD16;
1531 rlen = 8;
1532 } else {
1533 assert(inst->exec_size == 8);
1534 simd_mode = ELK_SAMPLER_SIMD_MODE_SIMD8;
1535 rlen = 4;
1536 }
1537
1538 if (devinfo->ver >= 5)
1539 msg_type = GFX5_SAMPLER_MESSAGE_SAMPLE_LD;
1540 else {
1541 /* We always use the SIMD16 message so that we only have to load U, and
1542 * not V or R.
1543 */
1544 msg_type = ELK_SAMPLER_MESSAGE_SIMD16_LD;
1545 assert(inst->mlen == 3);
1546 assert(inst->size_written == 8 * REG_SIZE);
1547 rlen = 8;
1548 simd_mode = ELK_SAMPLER_SIMD_MODE_SIMD16;
1549 }
1550
1551 struct elk_reg header = elk_vec8_grf(0, 0);
1552 elk_gfx6_resolve_implied_move(p, &header, inst->base_mrf);
1553
1554 elk_inst *send = elk_next_insn(p, ELK_OPCODE_SEND);
1555 elk_inst_set_compression(devinfo, send, false);
1556 elk_inst_set_sfid(devinfo, send, ELK_SFID_SAMPLER);
1557 elk_set_dest(p, send, retype(dst, ELK_REGISTER_TYPE_UW));
1558 elk_set_src0(p, send, header);
1559 if (devinfo->ver < 6)
1560 elk_inst_set_base_mrf(p->devinfo, send, inst->base_mrf);
1561
1562 /* Our surface is set up as floats, regardless of what actual data is
1563 * stored in it.
1564 */
1565 uint32_t return_format = ELK_SAMPLER_RETURN_FORMAT_FLOAT32;
1566 elk_set_desc(p, send,
1567 elk_message_desc(devinfo, inst->mlen, rlen, inst->header_size) |
1568 elk_sampler_desc(devinfo, surf_index,
1569 0, /* sampler (unused) */
1570 msg_type, simd_mode, return_format));
1571 }
1572
1573 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1574 * the ADD instruction.
1575 */
1576 void
generate_set_sample_id(elk_fs_inst * inst,struct elk_reg dst,struct elk_reg src0,struct elk_reg src1)1577 elk_fs_generator::generate_set_sample_id(elk_fs_inst *inst,
1578 struct elk_reg dst,
1579 struct elk_reg src0,
1580 struct elk_reg src1)
1581 {
1582 assert(dst.type == ELK_REGISTER_TYPE_D ||
1583 dst.type == ELK_REGISTER_TYPE_UD);
1584 assert(src0.type == ELK_REGISTER_TYPE_D ||
1585 src0.type == ELK_REGISTER_TYPE_UD);
1586
1587 const struct elk_reg reg = stride(src1, 1, 4, 0);
1588 const unsigned lower_size = MIN2(inst->exec_size,
1589 devinfo->ver >= 8 ? 16 : 8);
1590
1591 for (unsigned i = 0; i < inst->exec_size / lower_size; i++) {
1592 elk_inst *insn = elk_ADD(p, offset(dst, i * lower_size / 8),
1593 offset(src0, (src0.vstride == 0 ? 0 : (1 << (src0.vstride - 1)) *
1594 (i * lower_size / (1 << src0.width))) *
1595 type_sz(src0.type) / REG_SIZE),
1596 suboffset(reg, i * lower_size / 4));
1597 elk_inst_set_exec_size(devinfo, insn, cvt(lower_size) - 1);
1598 elk_inst_set_group(devinfo, insn, inst->group + lower_size * i);
1599 elk_inst_set_compression(devinfo, insn, lower_size > 8);
1600 elk_set_default_swsb(p, tgl_swsb_null());
1601 }
1602 }
1603
1604 void
enable_debug(const char * shader_name)1605 elk_fs_generator::enable_debug(const char *shader_name)
1606 {
1607 debug_flag = true;
1608 this->shader_name = shader_name;
1609 }
1610
1611 static elk_gfx12_systolic_depth
translate_systolic_depth(unsigned d)1612 translate_systolic_depth(unsigned d)
1613 {
1614 /* Could also return (ffs(d) - 1) & 3. */
1615 switch (d) {
1616 case 2: return ELK_SYSTOLIC_DEPTH_2;
1617 case 4: return ELK_SYSTOLIC_DEPTH_4;
1618 case 8: return ELK_SYSTOLIC_DEPTH_8;
1619 case 16: return ELK_SYSTOLIC_DEPTH_16;
1620 default: unreachable("Invalid systolic depth.");
1621 }
1622 }
1623
1624 int
generate_code(const elk_cfg_t * cfg,int dispatch_width,struct shader_stats shader_stats,const elk::performance & perf,struct elk_compile_stats * stats,unsigned max_polygons)1625 elk_fs_generator::generate_code(const elk_cfg_t *cfg, int dispatch_width,
1626 struct shader_stats shader_stats,
1627 const elk::performance &perf,
1628 struct elk_compile_stats *stats,
1629 unsigned max_polygons)
1630 {
1631 /* align to 64 byte boundary. */
1632 elk_realign(p, 64);
1633
1634 this->dispatch_width = dispatch_width;
1635
1636 int start_offset = p->next_insn_offset;
1637
1638 int loop_count = 0, send_count = 0, nop_count = 0, sync_nop_count = 0;
1639 bool is_accum_used = false;
1640
1641 struct elk_disasm_info *elk_disasm_info = elk_disasm_initialize(p->isa, cfg);
1642
1643 foreach_block_and_inst (block, elk_fs_inst, inst, cfg) {
1644 if (inst->opcode == ELK_SHADER_OPCODE_UNDEF)
1645 continue;
1646
1647 struct elk_reg src[4], dst;
1648 unsigned int last_insn_offset = p->next_insn_offset;
1649 bool multiple_instructions_emitted = false;
1650 tgl_swsb swsb = inst->sched;
1651
1652 /* From the Broadwell PRM, Volume 7, "3D-Media-GPGPU", in the
1653 * "Register Region Restrictions" section: for BDW, SKL:
1654 *
1655 * "A POW/FDIV operation must not be followed by an instruction
1656 * that requires two destination registers."
1657 *
1658 * The documentation is often lacking annotations for Atom parts,
1659 * and empirically this affects CHV as well.
1660 */
1661 if (devinfo->ver >= 8 &&
1662 devinfo->ver <= 9 &&
1663 p->nr_insn > 1 &&
1664 elk_inst_opcode(p->isa, elk_last_inst) == ELK_OPCODE_MATH &&
1665 elk_inst_math_function(devinfo, elk_last_inst) == ELK_MATH_FUNCTION_POW &&
1666 inst->dst.component_size(inst->exec_size) > REG_SIZE) {
1667 elk_NOP(p);
1668 last_insn_offset = p->next_insn_offset;
1669
1670 /* In order to avoid spurious instruction count differences when the
1671 * instruction schedule changes, keep track of the number of inserted
1672 * NOPs.
1673 */
1674 nop_count++;
1675 }
1676
1677 /* Wa_14010017096:
1678 *
1679 * Clear accumulator register before end of thread.
1680 */
1681 if (inst->eot && is_accum_used &&
1682 intel_needs_workaround(devinfo, 14010017096)) {
1683 elk_set_default_exec_size(p, ELK_EXECUTE_16);
1684 elk_set_default_group(p, 0);
1685 elk_set_default_mask_control(p, ELK_MASK_DISABLE);
1686 elk_set_default_predicate_control(p, ELK_PREDICATE_NONE);
1687 elk_set_default_flag_reg(p, 0, 0);
1688 elk_set_default_swsb(p, tgl_swsb_src_dep(swsb));
1689 elk_MOV(p, elk_acc_reg(8), elk_imm_f(0.0f));
1690 last_insn_offset = p->next_insn_offset;
1691 swsb = tgl_swsb_dst_dep(swsb, 1);
1692 }
1693
1694 if (!is_accum_used && !inst->eot) {
1695 is_accum_used = inst->writes_accumulator_implicitly(devinfo) ||
1696 inst->dst.is_accumulator();
1697 }
1698
1699 /* Wa_14013672992:
1700 *
1701 * Always use @1 SWSB for EOT.
1702 */
1703 if (inst->eot && intel_needs_workaround(devinfo, 14013672992)) {
1704 if (tgl_swsb_src_dep(swsb).mode) {
1705 elk_set_default_exec_size(p, ELK_EXECUTE_1);
1706 elk_set_default_mask_control(p, ELK_MASK_DISABLE);
1707 elk_set_default_predicate_control(p, ELK_PREDICATE_NONE);
1708 elk_set_default_flag_reg(p, 0, 0);
1709 elk_set_default_swsb(p, tgl_swsb_src_dep(swsb));
1710 elk_SYNC(p, TGL_SYNC_NOP);
1711 last_insn_offset = p->next_insn_offset;
1712 }
1713
1714 swsb = tgl_swsb_dst_dep(swsb, 1);
1715 }
1716
1717 if (unlikely(debug_flag))
1718 elk_disasm_annotate(elk_disasm_info, inst, p->next_insn_offset);
1719
1720 /* If the instruction writes to more than one register, it needs to be
1721 * explicitly marked as compressed on Gen <= 5. On Gen >= 6 the
1722 * hardware figures out by itself what the right compression mode is,
1723 * but we still need to know whether the instruction is compressed to
1724 * set up the source register regions appropriately.
1725 *
1726 * XXX - This is wrong for instructions that write a single register but
1727 * read more than one which should strictly speaking be treated as
1728 * compressed. For instructions that don't write any registers it
1729 * relies on the destination being a null register of the correct
1730 * type and regioning so the instruction is considered compressed
1731 * or not accordingly.
1732 */
1733 const bool compressed =
1734 inst->dst.component_size(inst->exec_size) > REG_SIZE;
1735 elk_set_default_compression(p, compressed);
1736
1737 if ((devinfo->ver >= 20 || devinfo->ver < 7) && inst->group % 8 != 0) {
1738 assert(inst->force_writemask_all);
1739 assert(!inst->predicate && !inst->conditional_mod);
1740 assert(!inst->writes_accumulator_implicitly(devinfo) &&
1741 !inst->reads_accumulator_implicitly());
1742 assert(inst->opcode != ELK_SHADER_OPCODE_SEL_EXEC);
1743 elk_set_default_group(p, 0);
1744 } else {
1745 elk_set_default_group(p, inst->group);
1746 }
1747
1748 for (unsigned int i = 0; i < inst->sources; i++) {
1749 src[i] = elk_reg_from_fs_reg(devinfo, inst,
1750 &inst->src[i], compressed);
1751 /* The accumulator result appears to get used for the
1752 * conditional modifier generation. When negating a UD
1753 * value, there is a 33rd bit generated for the sign in the
1754 * accumulator value, so now you can't check, for example,
1755 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1756 */
1757 assert(!inst->conditional_mod ||
1758 inst->src[i].type != ELK_REGISTER_TYPE_UD ||
1759 !inst->src[i].negate);
1760 }
1761 dst = elk_reg_from_fs_reg(devinfo, inst,
1762 &inst->dst, compressed);
1763
1764 elk_set_default_access_mode(p, ELK_ALIGN_1);
1765 elk_set_default_predicate_control(p, inst->predicate);
1766 elk_set_default_predicate_inverse(p, inst->predicate_inverse);
1767 /* On gfx7 and above, hardware automatically adds the group onto the
1768 * flag subregister number. On Sandy Bridge and older, we have to do it
1769 * ourselves.
1770 */
1771 const unsigned flag_subreg = inst->flag_subreg +
1772 (devinfo->ver >= 7 ? 0 : inst->group / 16);
1773 elk_set_default_flag_reg(p, flag_subreg / 2, flag_subreg % 2);
1774 elk_set_default_saturate(p, inst->saturate);
1775 elk_set_default_mask_control(p, inst->force_writemask_all);
1776 if (devinfo->ver >= 20 && inst->writes_accumulator) {
1777 assert(inst->dst.is_accumulator() ||
1778 inst->opcode == ELK_OPCODE_ADDC ||
1779 inst->opcode == ELK_OPCODE_MACH ||
1780 inst->opcode == ELK_OPCODE_SUBB);
1781 } else {
1782 elk_set_default_acc_write_control(p, inst->writes_accumulator);
1783 }
1784 elk_set_default_swsb(p, swsb);
1785
1786 unsigned exec_size = inst->exec_size;
1787 if (devinfo->verx10 == 70 &&
1788 (get_exec_type_size(inst) == 8 || type_sz(inst->dst.type) == 8)) {
1789 exec_size *= 2;
1790 }
1791
1792 elk_set_default_exec_size(p, cvt(exec_size) - 1);
1793
1794 assert(inst->force_writemask_all || inst->exec_size >= 4);
1795 assert(inst->force_writemask_all || inst->group % inst->exec_size == 0);
1796 assert(inst->base_mrf + inst->mlen <= ELK_MAX_MRF(devinfo->ver));
1797 assert(inst->mlen <= ELK_MAX_MSG_LENGTH * reg_unit(devinfo));
1798
1799 switch (inst->opcode) {
1800 case ELK_OPCODE_SYNC:
1801 assert(src[0].file == ELK_IMMEDIATE_VALUE);
1802 elk_SYNC(p, tgl_sync_function(src[0].ud));
1803
1804 if (tgl_sync_function(src[0].ud) == TGL_SYNC_NOP)
1805 ++sync_nop_count;
1806 break;
1807 case ELK_OPCODE_MOV:
1808 elk_MOV(p, dst, src[0]);
1809 break;
1810 case ELK_OPCODE_ADD:
1811 elk_ADD(p, dst, src[0], src[1]);
1812 break;
1813 case ELK_OPCODE_MUL:
1814 elk_MUL(p, dst, src[0], src[1]);
1815 break;
1816 case ELK_OPCODE_AVG:
1817 elk_AVG(p, dst, src[0], src[1]);
1818 break;
1819 case ELK_OPCODE_MACH:
1820 elk_MACH(p, dst, src[0], src[1]);
1821 break;
1822
1823 case ELK_OPCODE_DP4A:
1824 assert(devinfo->ver >= 12);
1825 elk_DP4A(p, dst, src[0], src[1], src[2]);
1826 break;
1827
1828 case ELK_OPCODE_LINE:
1829 elk_LINE(p, dst, src[0], src[1]);
1830 break;
1831
1832 case ELK_OPCODE_DPAS:
1833 assert(devinfo->verx10 >= 125);
1834 elk_DPAS(p, translate_systolic_depth(inst->sdepth), inst->rcount,
1835 dst, src[0], src[1], src[2]);
1836 break;
1837
1838 case ELK_OPCODE_MAD:
1839 assert(devinfo->ver >= 6);
1840 if (devinfo->ver < 10)
1841 elk_set_default_access_mode(p, ELK_ALIGN_16);
1842 elk_MAD(p, dst, src[0], src[1], src[2]);
1843 break;
1844
1845 case ELK_OPCODE_LRP:
1846 assert(devinfo->ver >= 6 && devinfo->ver <= 10);
1847 if (devinfo->ver < 10)
1848 elk_set_default_access_mode(p, ELK_ALIGN_16);
1849 elk_LRP(p, dst, src[0], src[1], src[2]);
1850 break;
1851
1852 case ELK_OPCODE_ADD3:
1853 assert(devinfo->verx10 >= 125);
1854 elk_ADD3(p, dst, src[0], src[1], src[2]);
1855 break;
1856
1857 case ELK_OPCODE_FRC:
1858 elk_FRC(p, dst, src[0]);
1859 break;
1860 case ELK_OPCODE_RNDD:
1861 elk_RNDD(p, dst, src[0]);
1862 break;
1863 case ELK_OPCODE_RNDE:
1864 elk_RNDE(p, dst, src[0]);
1865 break;
1866 case ELK_OPCODE_RNDZ:
1867 elk_RNDZ(p, dst, src[0]);
1868 break;
1869
1870 case ELK_OPCODE_AND:
1871 elk_AND(p, dst, src[0], src[1]);
1872 break;
1873 case ELK_OPCODE_OR:
1874 elk_OR(p, dst, src[0], src[1]);
1875 break;
1876 case ELK_OPCODE_XOR:
1877 elk_XOR(p, dst, src[0], src[1]);
1878 break;
1879 case ELK_OPCODE_NOT:
1880 elk_NOT(p, dst, src[0]);
1881 break;
1882 case ELK_OPCODE_ASR:
1883 elk_ASR(p, dst, src[0], src[1]);
1884 break;
1885 case ELK_OPCODE_SHR:
1886 elk_SHR(p, dst, src[0], src[1]);
1887 break;
1888 case ELK_OPCODE_SHL:
1889 elk_SHL(p, dst, src[0], src[1]);
1890 break;
1891 case ELK_OPCODE_ROL:
1892 assert(devinfo->ver >= 11);
1893 assert(src[0].type == dst.type);
1894 elk_ROL(p, dst, src[0], src[1]);
1895 break;
1896 case ELK_OPCODE_ROR:
1897 assert(devinfo->ver >= 11);
1898 assert(src[0].type == dst.type);
1899 elk_ROR(p, dst, src[0], src[1]);
1900 break;
1901 case ELK_OPCODE_F32TO16:
1902 elk_F32TO16(p, dst, src[0]);
1903 break;
1904 case ELK_OPCODE_F16TO32:
1905 elk_F16TO32(p, dst, src[0]);
1906 break;
1907 case ELK_OPCODE_CMP:
1908 if (inst->exec_size >= 16 && devinfo->verx10 == 70 &&
1909 dst.file == ELK_ARCHITECTURE_REGISTER_FILE) {
1910 /* For unknown reasons the WaCMPInstFlagDepClearedEarly workaround
1911 * implemented in the compiler is not sufficient. Overriding the
1912 * type when the destination is the null register is necessary but
1913 * not sufficient by itself.
1914 */
1915 dst.type = ELK_REGISTER_TYPE_D;
1916 }
1917 elk_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1918 break;
1919 case ELK_OPCODE_CMPN:
1920 if (inst->exec_size >= 16 && devinfo->verx10 == 70 &&
1921 dst.file == ELK_ARCHITECTURE_REGISTER_FILE) {
1922 /* For unknown reasons the WaCMPInstFlagDepClearedEarly workaround
1923 * implemented in the compiler is not sufficient. Overriding the
1924 * type when the destination is the null register is necessary but
1925 * not sufficient by itself.
1926 */
1927 dst.type = ELK_REGISTER_TYPE_D;
1928 }
1929 elk_CMPN(p, dst, inst->conditional_mod, src[0], src[1]);
1930 break;
1931 case ELK_OPCODE_SEL:
1932 elk_SEL(p, dst, src[0], src[1]);
1933 break;
1934 case ELK_OPCODE_CSEL:
1935 assert(devinfo->ver >= 8);
1936 if (devinfo->ver < 10)
1937 elk_set_default_access_mode(p, ELK_ALIGN_16);
1938 elk_CSEL(p, dst, src[0], src[1], src[2]);
1939 break;
1940 case ELK_OPCODE_BFREV:
1941 assert(devinfo->ver >= 7);
1942 elk_BFREV(p, retype(dst, ELK_REGISTER_TYPE_UD),
1943 retype(src[0], ELK_REGISTER_TYPE_UD));
1944 break;
1945 case ELK_OPCODE_FBH:
1946 assert(devinfo->ver >= 7);
1947 elk_FBH(p, retype(dst, src[0].type), src[0]);
1948 break;
1949 case ELK_OPCODE_FBL:
1950 assert(devinfo->ver >= 7);
1951 elk_FBL(p, retype(dst, ELK_REGISTER_TYPE_UD),
1952 retype(src[0], ELK_REGISTER_TYPE_UD));
1953 break;
1954 case ELK_OPCODE_LZD:
1955 elk_LZD(p, dst, src[0]);
1956 break;
1957 case ELK_OPCODE_CBIT:
1958 assert(devinfo->ver >= 7);
1959 elk_CBIT(p, retype(dst, ELK_REGISTER_TYPE_UD),
1960 retype(src[0], ELK_REGISTER_TYPE_UD));
1961 break;
1962 case ELK_OPCODE_ADDC:
1963 assert(devinfo->ver >= 7);
1964 elk_ADDC(p, dst, src[0], src[1]);
1965 break;
1966 case ELK_OPCODE_SUBB:
1967 assert(devinfo->ver >= 7);
1968 elk_SUBB(p, dst, src[0], src[1]);
1969 break;
1970 case ELK_OPCODE_MAC:
1971 elk_MAC(p, dst, src[0], src[1]);
1972 break;
1973
1974 case ELK_OPCODE_BFE:
1975 assert(devinfo->ver >= 7);
1976 if (devinfo->ver < 10)
1977 elk_set_default_access_mode(p, ELK_ALIGN_16);
1978 elk_BFE(p, dst, src[0], src[1], src[2]);
1979 break;
1980
1981 case ELK_OPCODE_BFI1:
1982 assert(devinfo->ver >= 7);
1983 elk_BFI1(p, dst, src[0], src[1]);
1984 break;
1985 case ELK_OPCODE_BFI2:
1986 assert(devinfo->ver >= 7);
1987 if (devinfo->ver < 10)
1988 elk_set_default_access_mode(p, ELK_ALIGN_16);
1989 elk_BFI2(p, dst, src[0], src[1], src[2]);
1990 break;
1991
1992 case ELK_OPCODE_IF:
1993 if (inst->src[0].file != BAD_FILE) {
1994 /* The instruction has an embedded compare (only allowed on gfx6) */
1995 assert(devinfo->ver == 6);
1996 elk_gfx6_IF(p, inst->conditional_mod, src[0], src[1]);
1997 } else {
1998 elk_IF(p, elk_get_default_exec_size(p));
1999 }
2000 break;
2001
2002 case ELK_OPCODE_ELSE:
2003 elk_ELSE(p);
2004 break;
2005 case ELK_OPCODE_ENDIF:
2006 elk_ENDIF(p);
2007 break;
2008
2009 case ELK_OPCODE_DO:
2010 elk_DO(p, elk_get_default_exec_size(p));
2011 break;
2012
2013 case ELK_OPCODE_BREAK:
2014 elk_BREAK(p);
2015 break;
2016 case ELK_OPCODE_CONTINUE:
2017 elk_CONT(p);
2018 break;
2019
2020 case ELK_OPCODE_WHILE:
2021 elk_WHILE(p);
2022 loop_count++;
2023 break;
2024
2025 case ELK_SHADER_OPCODE_RCP:
2026 case ELK_SHADER_OPCODE_RSQ:
2027 case ELK_SHADER_OPCODE_SQRT:
2028 case ELK_SHADER_OPCODE_EXP2:
2029 case ELK_SHADER_OPCODE_LOG2:
2030 case ELK_SHADER_OPCODE_SIN:
2031 case ELK_SHADER_OPCODE_COS:
2032 assert(inst->conditional_mod == ELK_CONDITIONAL_NONE);
2033 if (devinfo->ver >= 6) {
2034 assert(inst->mlen == 0);
2035 assert(devinfo->ver >= 7 || inst->exec_size == 8);
2036 elk_gfx6_math(p, dst, elk_math_function(inst->opcode),
2037 src[0], elk_null_reg());
2038 } else {
2039 assert(inst->mlen >= 1);
2040 assert(devinfo->ver == 5 || devinfo->platform == INTEL_PLATFORM_G4X || inst->exec_size == 8);
2041 elk_gfx4_math(p, dst,
2042 elk_math_function(inst->opcode),
2043 inst->base_mrf, src[0],
2044 ELK_MATH_PRECISION_FULL);
2045 send_count++;
2046 }
2047 break;
2048 case ELK_SHADER_OPCODE_INT_QUOTIENT:
2049 case ELK_SHADER_OPCODE_INT_REMAINDER:
2050 case ELK_SHADER_OPCODE_POW:
2051 assert(devinfo->verx10 < 125);
2052 assert(inst->conditional_mod == ELK_CONDITIONAL_NONE);
2053 if (devinfo->ver >= 6) {
2054 assert(inst->mlen == 0);
2055 assert((devinfo->ver >= 7 && inst->opcode == ELK_SHADER_OPCODE_POW) ||
2056 inst->exec_size == 8);
2057 elk_gfx6_math(p, dst, elk_math_function(inst->opcode), src[0], src[1]);
2058 } else {
2059 assert(inst->mlen >= 1);
2060 assert(inst->exec_size == 8);
2061 elk_gfx4_math(p, dst, elk_math_function(inst->opcode),
2062 inst->base_mrf, src[0],
2063 ELK_MATH_PRECISION_FULL);
2064 send_count++;
2065 }
2066 break;
2067 case ELK_FS_OPCODE_LINTERP:
2068 multiple_instructions_emitted = generate_linterp(inst, dst, src);
2069 break;
2070 case ELK_FS_OPCODE_PIXEL_X:
2071 assert(src[0].type == ELK_REGISTER_TYPE_UW);
2072 assert(src[1].type == ELK_REGISTER_TYPE_UW);
2073 src[0].subnr = 0 * type_sz(src[0].type);
2074 if (src[1].file == ELK_IMMEDIATE_VALUE) {
2075 assert(src[1].ud == 0);
2076 elk_MOV(p, dst, stride(src[0], 8, 4, 1));
2077 } else {
2078 /* Coarse pixel case */
2079 elk_ADD(p, dst, stride(src[0], 8, 4, 1), src[1]);
2080 }
2081 break;
2082 case ELK_FS_OPCODE_PIXEL_Y:
2083 assert(src[0].type == ELK_REGISTER_TYPE_UW);
2084 assert(src[1].type == ELK_REGISTER_TYPE_UW);
2085 src[0].subnr = 4 * type_sz(src[0].type);
2086 if (src[1].file == ELK_IMMEDIATE_VALUE) {
2087 assert(src[1].ud == 0);
2088 elk_MOV(p, dst, stride(src[0], 8, 4, 1));
2089 } else {
2090 /* Coarse pixel case */
2091 elk_ADD(p, dst, stride(src[0], 8, 4, 1), src[1]);
2092 }
2093 break;
2094
2095 case ELK_SHADER_OPCODE_SEND:
2096 generate_send(inst, dst, src[0], src[1], src[2],
2097 inst->ex_mlen > 0 ? src[3] : elk_null_reg());
2098 send_count++;
2099 break;
2100
2101 case ELK_SHADER_OPCODE_TEX:
2102 case ELK_FS_OPCODE_TXB:
2103 case ELK_SHADER_OPCODE_TXD:
2104 case ELK_SHADER_OPCODE_TXF:
2105 case ELK_SHADER_OPCODE_TXF_CMS:
2106 case ELK_SHADER_OPCODE_TXL:
2107 case ELK_SHADER_OPCODE_TXS:
2108 case ELK_SHADER_OPCODE_LOD:
2109 case ELK_SHADER_OPCODE_TG4:
2110 case ELK_SHADER_OPCODE_SAMPLEINFO:
2111 assert(inst->src[0].file == BAD_FILE);
2112 generate_tex(inst, dst, src[1], src[2]);
2113 send_count++;
2114 break;
2115
2116 case ELK_FS_OPCODE_DDX_COARSE:
2117 case ELK_FS_OPCODE_DDX_FINE:
2118 generate_ddx(inst, dst, src[0]);
2119 break;
2120 case ELK_FS_OPCODE_DDY_COARSE:
2121 case ELK_FS_OPCODE_DDY_FINE:
2122 generate_ddy(inst, dst, src[0]);
2123 break;
2124
2125 case ELK_SHADER_OPCODE_GFX4_SCRATCH_WRITE:
2126 generate_scratch_write(inst, src[0]);
2127 send_count++;
2128 break;
2129
2130 case ELK_SHADER_OPCODE_GFX4_SCRATCH_READ:
2131 generate_scratch_read(inst, dst);
2132 send_count++;
2133 break;
2134
2135 case ELK_SHADER_OPCODE_GFX7_SCRATCH_READ:
2136 generate_scratch_read_gfx7(inst, dst);
2137 send_count++;
2138 break;
2139
2140 case ELK_SHADER_OPCODE_SCRATCH_HEADER:
2141 generate_scratch_header(inst, dst);
2142 break;
2143
2144 case ELK_SHADER_OPCODE_MOV_INDIRECT:
2145 generate_mov_indirect(inst, dst, src[0], src[1]);
2146 break;
2147
2148 case ELK_SHADER_OPCODE_MOV_RELOC_IMM:
2149 assert(src[0].file == ELK_IMMEDIATE_VALUE);
2150 elk_MOV_reloc_imm(p, dst, dst.type, src[0].ud);
2151 break;
2152
2153 case ELK_FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
2154 assert(inst->force_writemask_all);
2155 generate_uniform_pull_constant_load(inst, dst,
2156 src[PULL_UNIFORM_CONSTANT_SRC_SURFACE],
2157 src[PULL_UNIFORM_CONSTANT_SRC_OFFSET]);
2158 send_count++;
2159 break;
2160
2161 case ELK_FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4:
2162 generate_varying_pull_constant_load_gfx4(inst, dst, src[0]);
2163 send_count++;
2164 break;
2165
2166 case ELK_FS_OPCODE_REP_FB_WRITE:
2167 case ELK_FS_OPCODE_FB_WRITE:
2168 generate_fb_write(inst, src[0]);
2169 send_count++;
2170 break;
2171
2172 case ELK_FS_OPCODE_FB_READ:
2173 generate_fb_read(inst, dst, src[0]);
2174 send_count++;
2175 break;
2176
2177 case ELK_OPCODE_HALT:
2178 generate_halt(inst);
2179 break;
2180
2181 case ELK_SHADER_OPCODE_INTERLOCK:
2182 case ELK_SHADER_OPCODE_MEMORY_FENCE: {
2183 assert(src[1].file == ELK_IMMEDIATE_VALUE);
2184 assert(src[2].file == ELK_IMMEDIATE_VALUE);
2185
2186 const enum elk_opcode send_op = inst->opcode == ELK_SHADER_OPCODE_INTERLOCK ?
2187 ELK_OPCODE_SENDC : ELK_OPCODE_SEND;
2188
2189 elk_memory_fence(p, dst, src[0], send_op,
2190 elk_message_target(inst->sfid),
2191 inst->desc,
2192 /* commit_enable */ src[1].ud,
2193 /* bti */ src[2].ud);
2194 send_count++;
2195 break;
2196 }
2197
2198 case ELK_FS_OPCODE_SCHEDULING_FENCE:
2199 if (inst->sources == 0 && swsb.regdist == 0 &&
2200 swsb.mode == TGL_SBID_NULL) {
2201 if (unlikely(debug_flag))
2202 elk_disasm_info->use_tail = true;
2203 break;
2204 }
2205
2206 if (devinfo->ver >= 12) {
2207 /* Use the available SWSB information to stall. A single SYNC is
2208 * sufficient since if there were multiple dependencies, the
2209 * scoreboard algorithm already injected other SYNCs before this
2210 * instruction.
2211 */
2212 elk_SYNC(p, TGL_SYNC_NOP);
2213 } else {
2214 for (unsigned i = 0; i < inst->sources; i++) {
2215 /* Emit a MOV to force a stall until the instruction producing the
2216 * registers finishes.
2217 */
2218 elk_MOV(p, retype(elk_null_reg(), ELK_REGISTER_TYPE_UW),
2219 retype(src[i], ELK_REGISTER_TYPE_UW));
2220 }
2221
2222 if (inst->sources > 1)
2223 multiple_instructions_emitted = true;
2224 }
2225
2226 break;
2227
2228 case ELK_SHADER_OPCODE_FIND_LIVE_CHANNEL:
2229 elk_find_live_channel(p, dst, false);
2230 break;
2231 case ELK_SHADER_OPCODE_FIND_LAST_LIVE_CHANNEL:
2232 elk_find_live_channel(p, dst, true);
2233 break;
2234
2235 case ELK_FS_OPCODE_LOAD_LIVE_CHANNELS: {
2236 assert(devinfo->ver >= 8);
2237 assert(inst->force_writemask_all && inst->group == 0);
2238 assert(inst->dst.file == BAD_FILE);
2239 elk_set_default_exec_size(p, ELK_EXECUTE_1);
2240 elk_MOV(p, retype(elk_flag_subreg(inst->flag_subreg),
2241 ELK_REGISTER_TYPE_UD),
2242 retype(elk_mask_reg(0), ELK_REGISTER_TYPE_UD));
2243 break;
2244 }
2245 case ELK_SHADER_OPCODE_BROADCAST:
2246 assert(inst->force_writemask_all);
2247 elk_broadcast(p, dst, src[0], src[1]);
2248 break;
2249
2250 case ELK_SHADER_OPCODE_SHUFFLE:
2251 generate_shuffle(inst, dst, src[0], src[1]);
2252 break;
2253
2254 case ELK_SHADER_OPCODE_SEL_EXEC:
2255 assert(inst->force_writemask_all);
2256 assert(devinfo->has_64bit_float || type_sz(dst.type) <= 4);
2257 elk_set_default_mask_control(p, ELK_MASK_DISABLE);
2258 elk_MOV(p, dst, src[1]);
2259 elk_set_default_mask_control(p, ELK_MASK_ENABLE);
2260 elk_set_default_swsb(p, tgl_swsb_null());
2261 elk_MOV(p, dst, src[0]);
2262 break;
2263
2264 case ELK_SHADER_OPCODE_QUAD_SWIZZLE:
2265 assert(src[1].file == ELK_IMMEDIATE_VALUE);
2266 assert(src[1].type == ELK_REGISTER_TYPE_UD);
2267 generate_quad_swizzle(inst, dst, src[0], src[1].ud);
2268 break;
2269
2270 case ELK_SHADER_OPCODE_CLUSTER_BROADCAST: {
2271 assert((devinfo->platform != INTEL_PLATFORM_CHV &&
2272 !intel_device_info_is_9lp(devinfo) &&
2273 devinfo->has_64bit_float) || type_sz(src[0].type) <= 4);
2274 assert(!src[0].negate && !src[0].abs);
2275 assert(src[1].file == ELK_IMMEDIATE_VALUE);
2276 assert(src[1].type == ELK_REGISTER_TYPE_UD);
2277 assert(src[2].file == ELK_IMMEDIATE_VALUE);
2278 assert(src[2].type == ELK_REGISTER_TYPE_UD);
2279 const unsigned component = src[1].ud;
2280 const unsigned cluster_size = src[2].ud;
2281 assert(inst->src[0].file != ARF && inst->src[0].file != FIXED_GRF);
2282 const unsigned s = inst->src[0].stride;
2283 unsigned vstride = cluster_size * s;
2284 unsigned width = cluster_size;
2285
2286 /* The maximum exec_size is 32, but the maximum width is only 16. */
2287 if (inst->exec_size == width) {
2288 vstride = 0;
2289 width = 1;
2290 }
2291
2292 struct elk_reg strided = stride(suboffset(src[0], component * s),
2293 vstride, width, 0);
2294 elk_MOV(p, dst, strided);
2295 break;
2296 }
2297
2298 case ELK_FS_OPCODE_SET_SAMPLE_ID:
2299 generate_set_sample_id(inst, dst, src[0], src[1]);
2300 break;
2301
2302 case ELK_SHADER_OPCODE_HALT_TARGET:
2303 /* This is the place where the final HALT needs to be inserted if
2304 * we've emitted any discards. If not, this will emit no code.
2305 */
2306 if (!patch_halt_jumps()) {
2307 if (unlikely(debug_flag)) {
2308 elk_disasm_info->use_tail = true;
2309 }
2310 }
2311 break;
2312
2313 case ELK_CS_OPCODE_CS_TERMINATE:
2314 generate_cs_terminate(inst, src[0]);
2315 send_count++;
2316 break;
2317
2318 case ELK_SHADER_OPCODE_BARRIER:
2319 generate_barrier(inst, src[0]);
2320 send_count++;
2321 break;
2322
2323 case ELK_OPCODE_DIM:
2324 assert(devinfo->platform == INTEL_PLATFORM_HSW);
2325 assert(src[0].type == ELK_REGISTER_TYPE_DF);
2326 assert(dst.type == ELK_REGISTER_TYPE_DF);
2327 elk_DIM(p, dst, retype(src[0], ELK_REGISTER_TYPE_F));
2328 break;
2329
2330 case ELK_SHADER_OPCODE_RND_MODE: {
2331 assert(src[0].file == ELK_IMMEDIATE_VALUE);
2332 /*
2333 * Changes the floating point rounding mode updating the control
2334 * register field defined at cr0.0[5-6] bits.
2335 */
2336 enum elk_rnd_mode mode =
2337 (enum elk_rnd_mode) (src[0].d << ELK_CR0_RND_MODE_SHIFT);
2338 elk_float_controls_mode(p, mode, ELK_CR0_RND_MODE_MASK);
2339 }
2340 break;
2341
2342 case ELK_SHADER_OPCODE_FLOAT_CONTROL_MODE:
2343 assert(src[0].file == ELK_IMMEDIATE_VALUE);
2344 assert(src[1].file == ELK_IMMEDIATE_VALUE);
2345 elk_float_controls_mode(p, src[0].d, src[1].d);
2346 break;
2347
2348 case ELK_SHADER_OPCODE_READ_SR_REG:
2349 if (devinfo->ver >= 12) {
2350 /* There is a SWSB restriction that requires that any time sr0 is
2351 * accessed both the instruction doing the access and the next one
2352 * have SWSB set to RegDist(1).
2353 */
2354 if (elk_get_default_swsb(p).mode != TGL_SBID_NULL)
2355 elk_SYNC(p, TGL_SYNC_NOP);
2356 assert(src[0].file == ELK_IMMEDIATE_VALUE);
2357 elk_set_default_swsb(p, tgl_swsb_regdist(1));
2358 elk_MOV(p, dst, elk_sr0_reg(src[0].ud));
2359 elk_set_default_swsb(p, tgl_swsb_regdist(1));
2360 elk_AND(p, dst, dst, elk_imm_ud(0xffffffff));
2361 } else {
2362 elk_MOV(p, dst, elk_sr0_reg(src[0].ud));
2363 }
2364 break;
2365
2366 default:
2367 unreachable("Unsupported opcode");
2368
2369 case ELK_SHADER_OPCODE_LOAD_PAYLOAD:
2370 unreachable("Should be lowered by lower_load_payload()");
2371 }
2372
2373 if (multiple_instructions_emitted)
2374 continue;
2375
2376 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
2377 assert(p->next_insn_offset == last_insn_offset + 16 ||
2378 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2379 "emitting more than 1 instruction");
2380
2381 elk_inst *last = &p->store[last_insn_offset / 16];
2382
2383 if (inst->conditional_mod)
2384 elk_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
2385 if (devinfo->ver < 12) {
2386 elk_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
2387 elk_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
2388 }
2389 }
2390
2391 /* When enabled, insert sync NOP after every instruction and make sure
2392 * that current instruction depends on the previous instruction.
2393 */
2394 if (INTEL_DEBUG(DEBUG_SWSB_STALL) && devinfo->ver >= 12) {
2395 elk_set_default_swsb(p, tgl_swsb_regdist(1));
2396 elk_SYNC(p, TGL_SYNC_NOP);
2397 }
2398 }
2399
2400 elk_set_uip_jip(p, start_offset);
2401
2402 /* end of program sentinel */
2403 elk_disasm_new_inst_group(elk_disasm_info, p->next_insn_offset);
2404
2405 /* `send_count` explicitly does not include spills or fills, as we'd
2406 * like to use it as a metric for intentional memory access or other
2407 * shared function use. Otherwise, subtle changes to scheduling or
2408 * register allocation could cause it to fluctuate wildly - and that
2409 * effect is already counted in spill/fill counts.
2410 */
2411 send_count -= shader_stats.spill_count;
2412 send_count -= shader_stats.fill_count;
2413
2414 #ifndef NDEBUG
2415 bool validated =
2416 #else
2417 if (unlikely(debug_flag))
2418 #endif
2419 elk_validate_instructions(&compiler->isa, p->store,
2420 start_offset,
2421 p->next_insn_offset,
2422 elk_disasm_info);
2423
2424 int before_size = p->next_insn_offset - start_offset;
2425 elk_compact_instructions(p, start_offset, elk_disasm_info);
2426 int after_size = p->next_insn_offset - start_offset;
2427
2428 bool dump_shader_bin = elk_should_dump_shader_bin();
2429 unsigned char sha1[21];
2430 char sha1buf[41];
2431
2432 if (unlikely(debug_flag || dump_shader_bin)) {
2433 _mesa_sha1_compute(p->store + start_offset / sizeof(elk_inst),
2434 after_size, sha1);
2435 _mesa_sha1_format(sha1buf, sha1);
2436 }
2437
2438 if (unlikely(dump_shader_bin))
2439 elk_dump_shader_bin(p->store, start_offset, p->next_insn_offset,
2440 sha1buf);
2441
2442 if (unlikely(debug_flag)) {
2443 fprintf(stderr, "Native code for %s (src_hash 0x%08x) (sha1 %s)\n"
2444 "SIMD%d shader: %d instructions. %d loops. %u cycles. "
2445 "%d:%d spills:fills, %u sends, "
2446 "scheduled with mode %s. "
2447 "Promoted %u constants. "
2448 "Compacted %d to %d bytes (%.0f%%)\n",
2449 shader_name, params->source_hash, sha1buf,
2450 dispatch_width, before_size / 16,
2451 loop_count, perf.latency,
2452 shader_stats.spill_count,
2453 shader_stats.fill_count,
2454 send_count,
2455 shader_stats.scheduler_mode,
2456 shader_stats.promoted_constants,
2457 before_size, after_size,
2458 100.0f * (before_size - after_size) / before_size);
2459
2460 /* overriding the shader makes elk_disasm_info invalid */
2461 if (!elk_try_override_assembly(p, start_offset, sha1buf)) {
2462 elk_dump_assembly(p->store, start_offset, p->next_insn_offset,
2463 elk_disasm_info, perf.block_latency);
2464 } else {
2465 fprintf(stderr, "Successfully overrode shader with sha1 %s\n\n", sha1buf);
2466 }
2467 }
2468 ralloc_free(elk_disasm_info);
2469 #ifndef NDEBUG
2470 if (!validated && !debug_flag) {
2471 fprintf(stderr,
2472 "Validation failed. Rerun with INTEL_DEBUG=shaders to get more information.\n");
2473 }
2474 #endif
2475 assert(validated);
2476
2477 elk_shader_debug_log(compiler, params->log_data,
2478 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2479 "%d:%d spills:fills, %u sends, "
2480 "scheduled with mode %s, "
2481 "Promoted %u constants, "
2482 "compacted %d to %d bytes.\n",
2483 _mesa_shader_stage_to_abbrev(stage),
2484 dispatch_width,
2485 before_size / 16 - nop_count - sync_nop_count,
2486 loop_count, perf.latency,
2487 shader_stats.spill_count,
2488 shader_stats.fill_count,
2489 send_count,
2490 shader_stats.scheduler_mode,
2491 shader_stats.promoted_constants,
2492 before_size, after_size);
2493 if (stats) {
2494 stats->dispatch_width = dispatch_width;
2495 stats->max_polygons = max_polygons;
2496 stats->max_dispatch_width = dispatch_width;
2497 stats->instructions = before_size / 16 - nop_count - sync_nop_count;
2498 stats->sends = send_count;
2499 stats->loops = loop_count;
2500 stats->cycles = perf.latency;
2501 stats->spills = shader_stats.spill_count;
2502 stats->fills = shader_stats.fill_count;
2503 stats->max_live_registers = shader_stats.max_register_pressure;
2504 }
2505
2506 return start_offset;
2507 }
2508
2509 void
add_const_data(void * data,unsigned size)2510 elk_fs_generator::add_const_data(void *data, unsigned size)
2511 {
2512 assert(prog_data->const_data_size == 0);
2513 if (size > 0) {
2514 prog_data->const_data_size = size;
2515 prog_data->const_data_offset = elk_append_data(p, data, size, 32);
2516 }
2517 }
2518
2519 const unsigned *
get_assembly()2520 elk_fs_generator::get_assembly()
2521 {
2522 prog_data->relocs = elk_get_shader_relocs(p, &prog_data->num_relocs);
2523
2524 return elk_get_program(p, &prog_data->program_size);
2525 }
2526