1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "elk_cfg.h"
25 #include "elk_eu.h"
26 #include "elk_fs.h"
27 #include "elk_nir.h"
28 #include "elk_private.h"
29 #include "elk_vec4_tes.h"
30 #include "dev/intel_debug.h"
31 #include "util/macros.h"
32 #include "util/u_debug.h"
33
34 enum elk_reg_type
elk_type_for_base_type(const struct glsl_type * type)35 elk_type_for_base_type(const struct glsl_type *type)
36 {
37 switch (type->base_type) {
38 case GLSL_TYPE_FLOAT16:
39 return ELK_REGISTER_TYPE_HF;
40 case GLSL_TYPE_FLOAT:
41 return ELK_REGISTER_TYPE_F;
42 case GLSL_TYPE_INT:
43 case GLSL_TYPE_BOOL:
44 case GLSL_TYPE_SUBROUTINE:
45 return ELK_REGISTER_TYPE_D;
46 case GLSL_TYPE_INT16:
47 return ELK_REGISTER_TYPE_W;
48 case GLSL_TYPE_INT8:
49 return ELK_REGISTER_TYPE_B;
50 case GLSL_TYPE_UINT:
51 return ELK_REGISTER_TYPE_UD;
52 case GLSL_TYPE_UINT16:
53 return ELK_REGISTER_TYPE_UW;
54 case GLSL_TYPE_UINT8:
55 return ELK_REGISTER_TYPE_UB;
56 case GLSL_TYPE_ARRAY:
57 return elk_type_for_base_type(type->fields.array);
58 case GLSL_TYPE_STRUCT:
59 case GLSL_TYPE_INTERFACE:
60 case GLSL_TYPE_SAMPLER:
61 case GLSL_TYPE_TEXTURE:
62 case GLSL_TYPE_ATOMIC_UINT:
63 /* These should be overridden with the type of the member when
64 * dereferenced into. ELK_REGISTER_TYPE_UD seems like a likely
65 * way to trip up if we don't.
66 */
67 return ELK_REGISTER_TYPE_UD;
68 case GLSL_TYPE_IMAGE:
69 return ELK_REGISTER_TYPE_UD;
70 case GLSL_TYPE_DOUBLE:
71 return ELK_REGISTER_TYPE_DF;
72 case GLSL_TYPE_UINT64:
73 return ELK_REGISTER_TYPE_UQ;
74 case GLSL_TYPE_INT64:
75 return ELK_REGISTER_TYPE_Q;
76 case GLSL_TYPE_VOID:
77 case GLSL_TYPE_ERROR:
78 case GLSL_TYPE_COOPERATIVE_MATRIX:
79 unreachable("not reached");
80 }
81
82 return ELK_REGISTER_TYPE_F;
83 }
84
85 uint32_t
elk_math_function(enum elk_opcode op)86 elk_math_function(enum elk_opcode op)
87 {
88 switch (op) {
89 case ELK_SHADER_OPCODE_RCP:
90 return ELK_MATH_FUNCTION_INV;
91 case ELK_SHADER_OPCODE_RSQ:
92 return ELK_MATH_FUNCTION_RSQ;
93 case ELK_SHADER_OPCODE_SQRT:
94 return ELK_MATH_FUNCTION_SQRT;
95 case ELK_SHADER_OPCODE_EXP2:
96 return ELK_MATH_FUNCTION_EXP;
97 case ELK_SHADER_OPCODE_LOG2:
98 return ELK_MATH_FUNCTION_LOG;
99 case ELK_SHADER_OPCODE_POW:
100 return ELK_MATH_FUNCTION_POW;
101 case ELK_SHADER_OPCODE_SIN:
102 return ELK_MATH_FUNCTION_SIN;
103 case ELK_SHADER_OPCODE_COS:
104 return ELK_MATH_FUNCTION_COS;
105 case ELK_SHADER_OPCODE_INT_QUOTIENT:
106 return ELK_MATH_FUNCTION_INT_DIV_QUOTIENT;
107 case ELK_SHADER_OPCODE_INT_REMAINDER:
108 return ELK_MATH_FUNCTION_INT_DIV_REMAINDER;
109 default:
110 unreachable("not reached: unknown math function");
111 }
112 }
113
114 bool
elk_texture_offset(const nir_tex_instr * tex,unsigned src,uint32_t * offset_bits_out)115 elk_texture_offset(const nir_tex_instr *tex, unsigned src,
116 uint32_t *offset_bits_out)
117 {
118 if (!nir_src_is_const(tex->src[src].src))
119 return false;
120
121 const unsigned num_components = nir_tex_instr_src_size(tex, src);
122
123 /* Combine all three offsets into a single unsigned dword:
124 *
125 * bits 11:8 - U Offset (X component)
126 * bits 7:4 - V Offset (Y component)
127 * bits 3:0 - R Offset (Z component)
128 */
129 uint32_t offset_bits = 0;
130 for (unsigned i = 0; i < num_components; i++) {
131 int offset = nir_src_comp_as_int(tex->src[src].src, i);
132
133 /* offset out of bounds; caller will handle it. */
134 if (offset > 7 || offset < -8)
135 return false;
136
137 const unsigned shift = 4 * (2 - i);
138 offset_bits |= (offset << shift) & (0xF << shift);
139 }
140
141 *offset_bits_out = offset_bits;
142
143 return true;
144 }
145
146 const char *
elk_instruction_name(const struct elk_isa_info * isa,enum elk_opcode op)147 elk_instruction_name(const struct elk_isa_info *isa, enum elk_opcode op)
148 {
149 const struct intel_device_info *devinfo = isa->devinfo;
150
151 switch (op) {
152 case 0 ... NUM_ELK_OPCODES - 1:
153 /* The DO instruction doesn't exist on Gfx6+, but we use it to mark the
154 * start of a loop in the IR.
155 */
156 if (devinfo->ver >= 6 && op == ELK_OPCODE_DO)
157 return "do";
158
159 /* The following conversion opcodes doesn't exist on Gfx8+, but we use
160 * then to mark that we want to do the conversion.
161 */
162 if (devinfo->ver > 7 && op == ELK_OPCODE_F32TO16)
163 return "f32to16";
164
165 if (devinfo->ver > 7 && op == ELK_OPCODE_F16TO32)
166 return "f16to32";
167
168 /* DPAS instructions may transiently exist on platforms that do not
169 * support DPAS. They will eventually be lowered, but in the meantime it
170 * must be possible to query the instruction name.
171 */
172 if (devinfo->verx10 < 125 && op == ELK_OPCODE_DPAS)
173 return "dpas";
174
175 assert(elk_opcode_desc(isa, op)->name);
176 return elk_opcode_desc(isa, op)->name;
177 case ELK_FS_OPCODE_FB_WRITE:
178 return "fb_write";
179 case ELK_FS_OPCODE_FB_WRITE_LOGICAL:
180 return "fb_write_logical";
181 case ELK_FS_OPCODE_REP_FB_WRITE:
182 return "rep_fb_write";
183 case ELK_FS_OPCODE_FB_READ:
184 return "fb_read";
185 case ELK_FS_OPCODE_FB_READ_LOGICAL:
186 return "fb_read_logical";
187
188 case ELK_SHADER_OPCODE_RCP:
189 return "rcp";
190 case ELK_SHADER_OPCODE_RSQ:
191 return "rsq";
192 case ELK_SHADER_OPCODE_SQRT:
193 return "sqrt";
194 case ELK_SHADER_OPCODE_EXP2:
195 return "exp2";
196 case ELK_SHADER_OPCODE_LOG2:
197 return "log2";
198 case ELK_SHADER_OPCODE_POW:
199 return "pow";
200 case ELK_SHADER_OPCODE_INT_QUOTIENT:
201 return "int_quot";
202 case ELK_SHADER_OPCODE_INT_REMAINDER:
203 return "int_rem";
204 case ELK_SHADER_OPCODE_SIN:
205 return "sin";
206 case ELK_SHADER_OPCODE_COS:
207 return "cos";
208
209 case ELK_SHADER_OPCODE_SEND:
210 return "send";
211
212 case ELK_SHADER_OPCODE_UNDEF:
213 return "undef";
214
215 case ELK_SHADER_OPCODE_TEX:
216 return "tex";
217 case ELK_SHADER_OPCODE_TEX_LOGICAL:
218 return "tex_logical";
219 case ELK_SHADER_OPCODE_TXD:
220 return "txd";
221 case ELK_SHADER_OPCODE_TXD_LOGICAL:
222 return "txd_logical";
223 case ELK_SHADER_OPCODE_TXF:
224 return "txf";
225 case ELK_SHADER_OPCODE_TXF_LOGICAL:
226 return "txf_logical";
227 case ELK_SHADER_OPCODE_TXF_LZ:
228 return "txf_lz";
229 case ELK_SHADER_OPCODE_TXL:
230 return "txl";
231 case ELK_SHADER_OPCODE_TXL_LOGICAL:
232 return "txl_logical";
233 case ELK_SHADER_OPCODE_TXL_LZ:
234 return "txl_lz";
235 case ELK_SHADER_OPCODE_TXS:
236 return "txs";
237 case ELK_SHADER_OPCODE_TXS_LOGICAL:
238 return "txs_logical";
239 case ELK_FS_OPCODE_TXB:
240 return "txb";
241 case ELK_FS_OPCODE_TXB_LOGICAL:
242 return "txb_logical";
243 case ELK_SHADER_OPCODE_TXF_CMS:
244 return "txf_cms";
245 case ELK_SHADER_OPCODE_TXF_CMS_LOGICAL:
246 return "txf_cms_logical";
247 case ELK_SHADER_OPCODE_TXF_CMS_W:
248 return "txf_cms_w";
249 case ELK_SHADER_OPCODE_TXF_CMS_W_LOGICAL:
250 return "txf_cms_w_logical";
251 case ELK_SHADER_OPCODE_TXF_CMS_W_GFX12_LOGICAL:
252 return "txf_cms_w_gfx12_logical";
253 case ELK_SHADER_OPCODE_TXF_UMS:
254 return "txf_ums";
255 case ELK_SHADER_OPCODE_TXF_UMS_LOGICAL:
256 return "txf_ums_logical";
257 case ELK_SHADER_OPCODE_TXF_MCS:
258 return "txf_mcs";
259 case ELK_SHADER_OPCODE_TXF_MCS_LOGICAL:
260 return "txf_mcs_logical";
261 case ELK_SHADER_OPCODE_LOD:
262 return "lod";
263 case ELK_SHADER_OPCODE_LOD_LOGICAL:
264 return "lod_logical";
265 case ELK_SHADER_OPCODE_TG4:
266 return "tg4";
267 case ELK_SHADER_OPCODE_TG4_LOGICAL:
268 return "tg4_logical";
269 case ELK_SHADER_OPCODE_TG4_OFFSET:
270 return "tg4_offset";
271 case ELK_SHADER_OPCODE_TG4_OFFSET_LOGICAL:
272 return "tg4_offset_logical";
273 case ELK_SHADER_OPCODE_SAMPLEINFO:
274 return "sampleinfo";
275 case ELK_SHADER_OPCODE_SAMPLEINFO_LOGICAL:
276 return "sampleinfo_logical";
277
278 case ELK_SHADER_OPCODE_IMAGE_SIZE_LOGICAL:
279 return "image_size_logical";
280
281 case ELK_VEC4_OPCODE_UNTYPED_ATOMIC:
282 return "untyped_atomic";
283 case ELK_SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
284 return "untyped_atomic_logical";
285 case ELK_VEC4_OPCODE_UNTYPED_SURFACE_READ:
286 return "untyped_surface_read";
287 case ELK_SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
288 return "untyped_surface_read_logical";
289 case ELK_VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
290 return "untyped_surface_write";
291 case ELK_SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
292 return "untyped_surface_write_logical";
293 case ELK_SHADER_OPCODE_UNALIGNED_OWORD_BLOCK_READ_LOGICAL:
294 return "unaligned_oword_block_read_logical";
295 case ELK_SHADER_OPCODE_OWORD_BLOCK_WRITE_LOGICAL:
296 return "oword_block_write_logical";
297 case ELK_SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL:
298 return "a64_untyped_read_logical";
299 case ELK_SHADER_OPCODE_A64_OWORD_BLOCK_READ_LOGICAL:
300 return "a64_oword_block_read_logical";
301 case ELK_SHADER_OPCODE_A64_UNALIGNED_OWORD_BLOCK_READ_LOGICAL:
302 return "a64_unaligned_oword_block_read_logical";
303 case ELK_SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL:
304 return "a64_oword_block_write_logical";
305 case ELK_SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL:
306 return "a64_untyped_write_logical";
307 case ELK_SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL:
308 return "a64_byte_scattered_read_logical";
309 case ELK_SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL:
310 return "a64_byte_scattered_write_logical";
311 case ELK_SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL:
312 return "a64_untyped_atomic_logical";
313 case ELK_SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
314 return "typed_atomic_logical";
315 case ELK_SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
316 return "typed_surface_read_logical";
317 case ELK_SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
318 return "typed_surface_write_logical";
319 case ELK_SHADER_OPCODE_MEMORY_FENCE:
320 return "memory_fence";
321 case ELK_FS_OPCODE_SCHEDULING_FENCE:
322 return "scheduling_fence";
323 case ELK_SHADER_OPCODE_INTERLOCK:
324 /* For an interlock we actually issue a memory fence via sendc. */
325 return "interlock";
326
327 case ELK_SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
328 return "byte_scattered_read_logical";
329 case ELK_SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
330 return "byte_scattered_write_logical";
331 case ELK_SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL:
332 return "dword_scattered_read_logical";
333 case ELK_SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL:
334 return "dword_scattered_write_logical";
335
336 case ELK_SHADER_OPCODE_LOAD_PAYLOAD:
337 return "load_payload";
338 case ELK_FS_OPCODE_PACK:
339 return "pack";
340
341 case ELK_SHADER_OPCODE_GFX4_SCRATCH_READ:
342 return "gfx4_scratch_read";
343 case ELK_SHADER_OPCODE_GFX4_SCRATCH_WRITE:
344 return "gfx4_scratch_write";
345 case ELK_SHADER_OPCODE_GFX7_SCRATCH_READ:
346 return "gfx7_scratch_read";
347 case ELK_SHADER_OPCODE_SCRATCH_HEADER:
348 return "scratch_header";
349
350 case ELK_SHADER_OPCODE_URB_WRITE_LOGICAL:
351 return "urb_write_logical";
352 case ELK_SHADER_OPCODE_URB_READ_LOGICAL:
353 return "urb_read_logical";
354
355 case ELK_SHADER_OPCODE_FIND_LIVE_CHANNEL:
356 return "find_live_channel";
357 case ELK_SHADER_OPCODE_FIND_LAST_LIVE_CHANNEL:
358 return "find_last_live_channel";
359 case ELK_FS_OPCODE_LOAD_LIVE_CHANNELS:
360 return "load_live_channels";
361
362 case ELK_SHADER_OPCODE_BROADCAST:
363 return "broadcast";
364 case ELK_SHADER_OPCODE_SHUFFLE:
365 return "shuffle";
366 case ELK_SHADER_OPCODE_SEL_EXEC:
367 return "sel_exec";
368 case ELK_SHADER_OPCODE_QUAD_SWIZZLE:
369 return "quad_swizzle";
370 case ELK_SHADER_OPCODE_CLUSTER_BROADCAST:
371 return "cluster_broadcast";
372
373 case ELK_SHADER_OPCODE_GET_BUFFER_SIZE:
374 return "get_buffer_size";
375
376 case ELK_VEC4_OPCODE_MOV_BYTES:
377 return "mov_bytes";
378 case ELK_VEC4_OPCODE_PACK_BYTES:
379 return "pack_bytes";
380 case ELK_VEC4_OPCODE_UNPACK_UNIFORM:
381 return "unpack_uniform";
382 case ELK_VEC4_OPCODE_DOUBLE_TO_F32:
383 return "double_to_f32";
384 case ELK_VEC4_OPCODE_DOUBLE_TO_D32:
385 return "double_to_d32";
386 case ELK_VEC4_OPCODE_DOUBLE_TO_U32:
387 return "double_to_u32";
388 case ELK_VEC4_OPCODE_TO_DOUBLE:
389 return "single_to_double";
390 case ELK_VEC4_OPCODE_PICK_LOW_32BIT:
391 return "pick_low_32bit";
392 case ELK_VEC4_OPCODE_PICK_HIGH_32BIT:
393 return "pick_high_32bit";
394 case ELK_VEC4_OPCODE_SET_LOW_32BIT:
395 return "set_low_32bit";
396 case ELK_VEC4_OPCODE_SET_HIGH_32BIT:
397 return "set_high_32bit";
398 case ELK_VEC4_OPCODE_MOV_FOR_SCRATCH:
399 return "mov_for_scratch";
400 case ELK_VEC4_OPCODE_ZERO_OOB_PUSH_REGS:
401 return "zero_oob_push_regs";
402
403 case ELK_FS_OPCODE_DDX_COARSE:
404 return "ddx_coarse";
405 case ELK_FS_OPCODE_DDX_FINE:
406 return "ddx_fine";
407 case ELK_FS_OPCODE_DDY_COARSE:
408 return "ddy_coarse";
409 case ELK_FS_OPCODE_DDY_FINE:
410 return "ddy_fine";
411
412 case ELK_FS_OPCODE_LINTERP:
413 return "linterp";
414
415 case ELK_FS_OPCODE_PIXEL_X:
416 return "pixel_x";
417 case ELK_FS_OPCODE_PIXEL_Y:
418 return "pixel_y";
419
420 case ELK_FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
421 return "uniform_pull_const";
422 case ELK_FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GFX4:
423 return "varying_pull_const_gfx4";
424 case ELK_FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
425 return "varying_pull_const_logical";
426
427 case ELK_FS_OPCODE_SET_SAMPLE_ID:
428 return "set_sample_id";
429
430 case ELK_FS_OPCODE_PACK_HALF_2x16_SPLIT:
431 return "pack_half_2x16_split";
432
433 case ELK_SHADER_OPCODE_HALT_TARGET:
434 return "halt_target";
435
436 case ELK_FS_OPCODE_INTERPOLATE_AT_SAMPLE:
437 return "interp_sample";
438 case ELK_FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
439 return "interp_shared_offset";
440 case ELK_FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
441 return "interp_per_slot_offset";
442
443 case ELK_VEC4_VS_OPCODE_URB_WRITE:
444 return "vs_urb_write";
445 case ELK_VS_OPCODE_PULL_CONSTANT_LOAD:
446 return "pull_constant_load";
447 case ELK_VS_OPCODE_PULL_CONSTANT_LOAD_GFX7:
448 return "pull_constant_load_gfx7";
449
450 case ELK_VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
451 return "unpack_flags_simd4x2";
452
453 case ELK_VEC4_GS_OPCODE_URB_WRITE:
454 return "gs_urb_write";
455 case ELK_VEC4_GS_OPCODE_URB_WRITE_ALLOCATE:
456 return "gs_urb_write_allocate";
457 case ELK_GS_OPCODE_THREAD_END:
458 return "gs_thread_end";
459 case ELK_GS_OPCODE_SET_WRITE_OFFSET:
460 return "set_write_offset";
461 case ELK_GS_OPCODE_SET_VERTEX_COUNT:
462 return "set_vertex_count";
463 case ELK_GS_OPCODE_SET_DWORD_2:
464 return "set_dword_2";
465 case ELK_GS_OPCODE_PREPARE_CHANNEL_MASKS:
466 return "prepare_channel_masks";
467 case ELK_GS_OPCODE_SET_CHANNEL_MASKS:
468 return "set_channel_masks";
469 case ELK_GS_OPCODE_GET_INSTANCE_ID:
470 return "get_instance_id";
471 case ELK_GS_OPCODE_FF_SYNC:
472 return "ff_sync";
473 case ELK_GS_OPCODE_SET_PRIMITIVE_ID:
474 return "set_primitive_id";
475 case ELK_GS_OPCODE_SVB_WRITE:
476 return "gs_svb_write";
477 case ELK_GS_OPCODE_SVB_SET_DST_INDEX:
478 return "gs_svb_set_dst_index";
479 case ELK_GS_OPCODE_FF_SYNC_SET_PRIMITIVES:
480 return "gs_ff_sync_set_primitives";
481 case ELK_CS_OPCODE_CS_TERMINATE:
482 return "cs_terminate";
483 case ELK_SHADER_OPCODE_BARRIER:
484 return "barrier";
485 case ELK_SHADER_OPCODE_MULH:
486 return "mulh";
487 case ELK_SHADER_OPCODE_ISUB_SAT:
488 return "isub_sat";
489 case ELK_SHADER_OPCODE_USUB_SAT:
490 return "usub_sat";
491 case ELK_SHADER_OPCODE_MOV_INDIRECT:
492 return "mov_indirect";
493 case ELK_SHADER_OPCODE_MOV_RELOC_IMM:
494 return "mov_reloc_imm";
495
496 case ELK_VEC4_OPCODE_URB_READ:
497 return "urb_read";
498 case ELK_TCS_OPCODE_GET_INSTANCE_ID:
499 return "tcs_get_instance_id";
500 case ELK_VEC4_TCS_OPCODE_URB_WRITE:
501 return "tcs_urb_write";
502 case ELK_VEC4_TCS_OPCODE_SET_INPUT_URB_OFFSETS:
503 return "tcs_set_input_urb_offsets";
504 case ELK_VEC4_TCS_OPCODE_SET_OUTPUT_URB_OFFSETS:
505 return "tcs_set_output_urb_offsets";
506 case ELK_TCS_OPCODE_GET_PRIMITIVE_ID:
507 return "tcs_get_primitive_id";
508 case ELK_TCS_OPCODE_CREATE_BARRIER_HEADER:
509 return "tcs_create_barrier_header";
510 case ELK_TCS_OPCODE_SRC0_010_IS_ZERO:
511 return "tcs_src0<0,1,0>_is_zero";
512 case ELK_TCS_OPCODE_RELEASE_INPUT:
513 return "tcs_release_input";
514 case ELK_TCS_OPCODE_THREAD_END:
515 return "tcs_thread_end";
516 case ELK_TES_OPCODE_CREATE_INPUT_READ_HEADER:
517 return "tes_create_input_read_header";
518 case ELK_TES_OPCODE_ADD_INDIRECT_URB_OFFSET:
519 return "tes_add_indirect_urb_offset";
520 case ELK_TES_OPCODE_GET_PRIMITIVE_ID:
521 return "tes_get_primitive_id";
522
523 case ELK_RT_OPCODE_TRACE_RAY_LOGICAL:
524 return "rt_trace_ray_logical";
525
526 case ELK_SHADER_OPCODE_RND_MODE:
527 return "rnd_mode";
528 case ELK_SHADER_OPCODE_FLOAT_CONTROL_MODE:
529 return "float_control_mode";
530 case ELK_SHADER_OPCODE_BTD_SPAWN_LOGICAL:
531 return "btd_spawn_logical";
532 case ELK_SHADER_OPCODE_BTD_RETIRE_LOGICAL:
533 return "btd_retire_logical";
534 case ELK_SHADER_OPCODE_READ_SR_REG:
535 return "read_sr_reg";
536 }
537
538 unreachable("not reached");
539 }
540
541 bool
elk_saturate_immediate(enum elk_reg_type type,struct elk_reg * reg)542 elk_saturate_immediate(enum elk_reg_type type, struct elk_reg *reg)
543 {
544 union {
545 unsigned ud;
546 int d;
547 float f;
548 double df;
549 } imm, sat_imm = { 0 };
550
551 const unsigned size = type_sz(type);
552
553 /* We want to either do a 32-bit or 64-bit data copy, the type is otherwise
554 * irrelevant, so just check the size of the type and copy from/to an
555 * appropriately sized field.
556 */
557 if (size < 8)
558 imm.ud = reg->ud;
559 else
560 imm.df = reg->df;
561
562 switch (type) {
563 case ELK_REGISTER_TYPE_UD:
564 case ELK_REGISTER_TYPE_D:
565 case ELK_REGISTER_TYPE_UW:
566 case ELK_REGISTER_TYPE_W:
567 case ELK_REGISTER_TYPE_UQ:
568 case ELK_REGISTER_TYPE_Q:
569 /* Nothing to do. */
570 return false;
571 case ELK_REGISTER_TYPE_F:
572 sat_imm.f = SATURATE(imm.f);
573 break;
574 case ELK_REGISTER_TYPE_DF:
575 sat_imm.df = SATURATE(imm.df);
576 break;
577 case ELK_REGISTER_TYPE_UB:
578 case ELK_REGISTER_TYPE_B:
579 unreachable("no UB/B immediates");
580 case ELK_REGISTER_TYPE_V:
581 case ELK_REGISTER_TYPE_UV:
582 case ELK_REGISTER_TYPE_VF:
583 unreachable("unimplemented: saturate vector immediate");
584 case ELK_REGISTER_TYPE_HF:
585 unreachable("unimplemented: saturate HF immediate");
586 case ELK_REGISTER_TYPE_NF:
587 unreachable("no NF immediates");
588 }
589
590 if (size < 8) {
591 if (imm.ud != sat_imm.ud) {
592 reg->ud = sat_imm.ud;
593 return true;
594 }
595 } else {
596 if (imm.df != sat_imm.df) {
597 reg->df = sat_imm.df;
598 return true;
599 }
600 }
601 return false;
602 }
603
604 bool
elk_negate_immediate(enum elk_reg_type type,struct elk_reg * reg)605 elk_negate_immediate(enum elk_reg_type type, struct elk_reg *reg)
606 {
607 switch (type) {
608 case ELK_REGISTER_TYPE_D:
609 case ELK_REGISTER_TYPE_UD:
610 reg->d = -reg->d;
611 return true;
612 case ELK_REGISTER_TYPE_W:
613 case ELK_REGISTER_TYPE_UW: {
614 uint16_t value = -(int16_t)reg->ud;
615 reg->ud = value | (uint32_t)value << 16;
616 return true;
617 }
618 case ELK_REGISTER_TYPE_F:
619 reg->f = -reg->f;
620 return true;
621 case ELK_REGISTER_TYPE_VF:
622 reg->ud ^= 0x80808080;
623 return true;
624 case ELK_REGISTER_TYPE_DF:
625 reg->df = -reg->df;
626 return true;
627 case ELK_REGISTER_TYPE_UQ:
628 case ELK_REGISTER_TYPE_Q:
629 reg->d64 = -reg->d64;
630 return true;
631 case ELK_REGISTER_TYPE_UB:
632 case ELK_REGISTER_TYPE_B:
633 unreachable("no UB/B immediates");
634 case ELK_REGISTER_TYPE_UV:
635 case ELK_REGISTER_TYPE_V:
636 assert(!"unimplemented: negate UV/V immediate");
637 case ELK_REGISTER_TYPE_HF:
638 reg->ud ^= 0x80008000;
639 return true;
640 case ELK_REGISTER_TYPE_NF:
641 unreachable("no NF immediates");
642 }
643
644 return false;
645 }
646
647 bool
elk_abs_immediate(enum elk_reg_type type,struct elk_reg * reg)648 elk_abs_immediate(enum elk_reg_type type, struct elk_reg *reg)
649 {
650 switch (type) {
651 case ELK_REGISTER_TYPE_D:
652 reg->d = abs(reg->d);
653 return true;
654 case ELK_REGISTER_TYPE_W: {
655 uint16_t value = abs((int16_t)reg->ud);
656 reg->ud = value | (uint32_t)value << 16;
657 return true;
658 }
659 case ELK_REGISTER_TYPE_F:
660 reg->f = fabsf(reg->f);
661 return true;
662 case ELK_REGISTER_TYPE_DF:
663 reg->df = fabs(reg->df);
664 return true;
665 case ELK_REGISTER_TYPE_VF:
666 reg->ud &= ~0x80808080;
667 return true;
668 case ELK_REGISTER_TYPE_Q:
669 reg->d64 = imaxabs(reg->d64);
670 return true;
671 case ELK_REGISTER_TYPE_UB:
672 case ELK_REGISTER_TYPE_B:
673 unreachable("no UB/B immediates");
674 case ELK_REGISTER_TYPE_UQ:
675 case ELK_REGISTER_TYPE_UD:
676 case ELK_REGISTER_TYPE_UW:
677 case ELK_REGISTER_TYPE_UV:
678 /* Presumably the absolute value modifier on an unsigned source is a
679 * nop, but it would be nice to confirm.
680 */
681 assert(!"unimplemented: abs unsigned immediate");
682 case ELK_REGISTER_TYPE_V:
683 assert(!"unimplemented: abs V immediate");
684 case ELK_REGISTER_TYPE_HF:
685 reg->ud &= ~0x80008000;
686 return true;
687 case ELK_REGISTER_TYPE_NF:
688 unreachable("no NF immediates");
689 }
690
691 return false;
692 }
693
elk_backend_shader(const struct elk_compiler * compiler,const struct elk_compile_params * params,const nir_shader * shader,struct elk_stage_prog_data * stage_prog_data,bool debug_enabled)694 elk_backend_shader::elk_backend_shader(const struct elk_compiler *compiler,
695 const struct elk_compile_params *params,
696 const nir_shader *shader,
697 struct elk_stage_prog_data *stage_prog_data,
698 bool debug_enabled)
699 : compiler(compiler),
700 log_data(params->log_data),
701 devinfo(compiler->devinfo),
702 nir(shader),
703 stage_prog_data(stage_prog_data),
704 mem_ctx(params->mem_ctx),
705 cfg(NULL), idom_analysis(this),
706 stage(shader->info.stage),
707 debug_enabled(debug_enabled)
708 {
709 }
710
~elk_backend_shader()711 elk_backend_shader::~elk_backend_shader()
712 {
713 }
714
715 bool
equals(const elk_backend_reg & r) const716 elk_backend_reg::equals(const elk_backend_reg &r) const
717 {
718 return elk_regs_equal(this, &r) && offset == r.offset;
719 }
720
721 bool
negative_equals(const elk_backend_reg & r) const722 elk_backend_reg::negative_equals(const elk_backend_reg &r) const
723 {
724 return elk_regs_negative_equal(this, &r) && offset == r.offset;
725 }
726
727 bool
is_zero() const728 elk_backend_reg::is_zero() const
729 {
730 if (file != IMM)
731 return false;
732
733 assert(type_sz(type) > 1);
734
735 switch (type) {
736 case ELK_REGISTER_TYPE_HF:
737 assert((d & 0xffff) == ((d >> 16) & 0xffff));
738 return (d & 0xffff) == 0 || (d & 0xffff) == 0x8000;
739 case ELK_REGISTER_TYPE_F:
740 return f == 0;
741 case ELK_REGISTER_TYPE_DF:
742 return df == 0;
743 case ELK_REGISTER_TYPE_W:
744 case ELK_REGISTER_TYPE_UW:
745 assert((d & 0xffff) == ((d >> 16) & 0xffff));
746 return (d & 0xffff) == 0;
747 case ELK_REGISTER_TYPE_D:
748 case ELK_REGISTER_TYPE_UD:
749 return d == 0;
750 case ELK_REGISTER_TYPE_UQ:
751 case ELK_REGISTER_TYPE_Q:
752 return u64 == 0;
753 default:
754 return false;
755 }
756 }
757
758 bool
is_one() const759 elk_backend_reg::is_one() const
760 {
761 if (file != IMM)
762 return false;
763
764 assert(type_sz(type) > 1);
765
766 switch (type) {
767 case ELK_REGISTER_TYPE_HF:
768 assert((d & 0xffff) == ((d >> 16) & 0xffff));
769 return (d & 0xffff) == 0x3c00;
770 case ELK_REGISTER_TYPE_F:
771 return f == 1.0f;
772 case ELK_REGISTER_TYPE_DF:
773 return df == 1.0;
774 case ELK_REGISTER_TYPE_W:
775 case ELK_REGISTER_TYPE_UW:
776 assert((d & 0xffff) == ((d >> 16) & 0xffff));
777 return (d & 0xffff) == 1;
778 case ELK_REGISTER_TYPE_D:
779 case ELK_REGISTER_TYPE_UD:
780 return d == 1;
781 case ELK_REGISTER_TYPE_UQ:
782 case ELK_REGISTER_TYPE_Q:
783 return u64 == 1;
784 default:
785 return false;
786 }
787 }
788
789 bool
is_negative_one() const790 elk_backend_reg::is_negative_one() const
791 {
792 if (file != IMM)
793 return false;
794
795 assert(type_sz(type) > 1);
796
797 switch (type) {
798 case ELK_REGISTER_TYPE_HF:
799 assert((d & 0xffff) == ((d >> 16) & 0xffff));
800 return (d & 0xffff) == 0xbc00;
801 case ELK_REGISTER_TYPE_F:
802 return f == -1.0;
803 case ELK_REGISTER_TYPE_DF:
804 return df == -1.0;
805 case ELK_REGISTER_TYPE_W:
806 assert((d & 0xffff) == ((d >> 16) & 0xffff));
807 return (d & 0xffff) == 0xffff;
808 case ELK_REGISTER_TYPE_D:
809 return d == -1;
810 case ELK_REGISTER_TYPE_Q:
811 return d64 == -1;
812 default:
813 return false;
814 }
815 }
816
817 bool
is_null() const818 elk_backend_reg::is_null() const
819 {
820 return file == ARF && nr == ELK_ARF_NULL;
821 }
822
823
824 bool
is_accumulator() const825 elk_backend_reg::is_accumulator() const
826 {
827 return file == ARF && nr == ELK_ARF_ACCUMULATOR;
828 }
829
830 bool
is_commutative() const831 elk_backend_instruction::is_commutative() const
832 {
833 switch (opcode) {
834 case ELK_OPCODE_AND:
835 case ELK_OPCODE_OR:
836 case ELK_OPCODE_XOR:
837 case ELK_OPCODE_ADD:
838 case ELK_OPCODE_ADD3:
839 case ELK_OPCODE_MUL:
840 case ELK_SHADER_OPCODE_MULH:
841 return true;
842 case ELK_OPCODE_SEL:
843 /* MIN and MAX are commutative. */
844 if (conditional_mod == ELK_CONDITIONAL_GE ||
845 conditional_mod == ELK_CONDITIONAL_L) {
846 return true;
847 }
848 FALLTHROUGH;
849 default:
850 return false;
851 }
852 }
853
854 bool
elk_is_3src(const struct elk_compiler * compiler) const855 elk_backend_instruction::elk_is_3src(const struct elk_compiler *compiler) const
856 {
857 return ::elk_is_3src(&compiler->isa, opcode);
858 }
859
860 bool
is_math() const861 elk_backend_instruction::is_math() const
862 {
863 return (opcode == ELK_SHADER_OPCODE_RCP ||
864 opcode == ELK_SHADER_OPCODE_RSQ ||
865 opcode == ELK_SHADER_OPCODE_SQRT ||
866 opcode == ELK_SHADER_OPCODE_EXP2 ||
867 opcode == ELK_SHADER_OPCODE_LOG2 ||
868 opcode == ELK_SHADER_OPCODE_SIN ||
869 opcode == ELK_SHADER_OPCODE_COS ||
870 opcode == ELK_SHADER_OPCODE_INT_QUOTIENT ||
871 opcode == ELK_SHADER_OPCODE_INT_REMAINDER ||
872 opcode == ELK_SHADER_OPCODE_POW);
873 }
874
875 bool
is_control_flow_begin() const876 elk_backend_instruction::is_control_flow_begin() const
877 {
878 switch (opcode) {
879 case ELK_OPCODE_DO:
880 case ELK_OPCODE_IF:
881 case ELK_OPCODE_ELSE:
882 return true;
883 default:
884 return false;
885 }
886 }
887
888 bool
is_control_flow_end() const889 elk_backend_instruction::is_control_flow_end() const
890 {
891 switch (opcode) {
892 case ELK_OPCODE_ELSE:
893 case ELK_OPCODE_WHILE:
894 case ELK_OPCODE_ENDIF:
895 return true;
896 default:
897 return false;
898 }
899 }
900
901 bool
is_control_flow() const902 elk_backend_instruction::is_control_flow() const
903 {
904 switch (opcode) {
905 case ELK_OPCODE_DO:
906 case ELK_OPCODE_WHILE:
907 case ELK_OPCODE_IF:
908 case ELK_OPCODE_ELSE:
909 case ELK_OPCODE_ENDIF:
910 case ELK_OPCODE_BREAK:
911 case ELK_OPCODE_CONTINUE:
912 return true;
913 default:
914 return false;
915 }
916 }
917
918 bool
uses_indirect_addressing() const919 elk_backend_instruction::uses_indirect_addressing() const
920 {
921 switch (opcode) {
922 case ELK_SHADER_OPCODE_BROADCAST:
923 case ELK_SHADER_OPCODE_CLUSTER_BROADCAST:
924 case ELK_SHADER_OPCODE_MOV_INDIRECT:
925 return true;
926 default:
927 return false;
928 }
929 }
930
931 bool
can_do_source_mods() const932 elk_backend_instruction::can_do_source_mods() const
933 {
934 switch (opcode) {
935 case ELK_OPCODE_ADDC:
936 case ELK_OPCODE_BFE:
937 case ELK_OPCODE_BFI1:
938 case ELK_OPCODE_BFI2:
939 case ELK_OPCODE_BFREV:
940 case ELK_OPCODE_CBIT:
941 case ELK_OPCODE_FBH:
942 case ELK_OPCODE_FBL:
943 case ELK_OPCODE_ROL:
944 case ELK_OPCODE_ROR:
945 case ELK_OPCODE_SUBB:
946 case ELK_OPCODE_DP4A:
947 case ELK_OPCODE_DPAS:
948 case ELK_SHADER_OPCODE_BROADCAST:
949 case ELK_SHADER_OPCODE_CLUSTER_BROADCAST:
950 case ELK_SHADER_OPCODE_MOV_INDIRECT:
951 case ELK_SHADER_OPCODE_SHUFFLE:
952 case ELK_SHADER_OPCODE_INT_QUOTIENT:
953 case ELK_SHADER_OPCODE_INT_REMAINDER:
954 return false;
955 default:
956 return true;
957 }
958 }
959
960 bool
can_do_saturate() const961 elk_backend_instruction::can_do_saturate() const
962 {
963 switch (opcode) {
964 case ELK_OPCODE_ADD:
965 case ELK_OPCODE_ADD3:
966 case ELK_OPCODE_ASR:
967 case ELK_OPCODE_AVG:
968 case ELK_OPCODE_CSEL:
969 case ELK_OPCODE_DP2:
970 case ELK_OPCODE_DP3:
971 case ELK_OPCODE_DP4:
972 case ELK_OPCODE_DPH:
973 case ELK_OPCODE_DP4A:
974 case ELK_OPCODE_F16TO32:
975 case ELK_OPCODE_F32TO16:
976 case ELK_OPCODE_LINE:
977 case ELK_OPCODE_LRP:
978 case ELK_OPCODE_MAC:
979 case ELK_OPCODE_MAD:
980 case ELK_OPCODE_MATH:
981 case ELK_OPCODE_MOV:
982 case ELK_OPCODE_MUL:
983 case ELK_SHADER_OPCODE_MULH:
984 case ELK_OPCODE_PLN:
985 case ELK_OPCODE_RNDD:
986 case ELK_OPCODE_RNDE:
987 case ELK_OPCODE_RNDU:
988 case ELK_OPCODE_RNDZ:
989 case ELK_OPCODE_SEL:
990 case ELK_OPCODE_SHL:
991 case ELK_OPCODE_SHR:
992 case ELK_FS_OPCODE_LINTERP:
993 case ELK_SHADER_OPCODE_COS:
994 case ELK_SHADER_OPCODE_EXP2:
995 case ELK_SHADER_OPCODE_LOG2:
996 case ELK_SHADER_OPCODE_POW:
997 case ELK_SHADER_OPCODE_RCP:
998 case ELK_SHADER_OPCODE_RSQ:
999 case ELK_SHADER_OPCODE_SIN:
1000 case ELK_SHADER_OPCODE_SQRT:
1001 return true;
1002 default:
1003 return false;
1004 }
1005 }
1006
1007 bool
can_do_cmod() const1008 elk_backend_instruction::can_do_cmod() const
1009 {
1010 switch (opcode) {
1011 case ELK_OPCODE_ADD:
1012 case ELK_OPCODE_ADD3:
1013 case ELK_OPCODE_ADDC:
1014 case ELK_OPCODE_AND:
1015 case ELK_OPCODE_ASR:
1016 case ELK_OPCODE_AVG:
1017 case ELK_OPCODE_CMP:
1018 case ELK_OPCODE_CMPN:
1019 case ELK_OPCODE_DP2:
1020 case ELK_OPCODE_DP3:
1021 case ELK_OPCODE_DP4:
1022 case ELK_OPCODE_DPH:
1023 case ELK_OPCODE_F16TO32:
1024 case ELK_OPCODE_F32TO16:
1025 case ELK_OPCODE_FRC:
1026 case ELK_OPCODE_LINE:
1027 case ELK_OPCODE_LRP:
1028 case ELK_OPCODE_LZD:
1029 case ELK_OPCODE_MAC:
1030 case ELK_OPCODE_MACH:
1031 case ELK_OPCODE_MAD:
1032 case ELK_OPCODE_MOV:
1033 case ELK_OPCODE_MUL:
1034 case ELK_OPCODE_NOT:
1035 case ELK_OPCODE_OR:
1036 case ELK_OPCODE_PLN:
1037 case ELK_OPCODE_RNDD:
1038 case ELK_OPCODE_RNDE:
1039 case ELK_OPCODE_RNDU:
1040 case ELK_OPCODE_RNDZ:
1041 case ELK_OPCODE_SAD2:
1042 case ELK_OPCODE_SADA2:
1043 case ELK_OPCODE_SHL:
1044 case ELK_OPCODE_SHR:
1045 case ELK_OPCODE_SUBB:
1046 case ELK_OPCODE_XOR:
1047 case ELK_FS_OPCODE_LINTERP:
1048 return true;
1049 default:
1050 return false;
1051 }
1052 }
1053
1054 bool
reads_accumulator_implicitly() const1055 elk_backend_instruction::reads_accumulator_implicitly() const
1056 {
1057 switch (opcode) {
1058 case ELK_OPCODE_MAC:
1059 case ELK_OPCODE_MACH:
1060 case ELK_OPCODE_SADA2:
1061 return true;
1062 default:
1063 return false;
1064 }
1065 }
1066
1067 bool
writes_accumulator_implicitly(const struct intel_device_info * devinfo) const1068 elk_backend_instruction::writes_accumulator_implicitly(const struct intel_device_info *devinfo) const
1069 {
1070 return writes_accumulator ||
1071 (devinfo->ver < 6 &&
1072 ((opcode >= ELK_OPCODE_ADD && opcode < ELK_OPCODE_NOP) ||
1073 (opcode >= ELK_FS_OPCODE_DDX_COARSE && opcode <= ELK_FS_OPCODE_LINTERP))) ||
1074 (opcode == ELK_FS_OPCODE_LINTERP &&
1075 (!devinfo->has_pln || devinfo->ver <= 6)) ||
1076 (eot && intel_needs_workaround(devinfo, 14010017096));
1077 }
1078
1079 bool
has_side_effects() const1080 elk_backend_instruction::has_side_effects() const
1081 {
1082 switch (opcode) {
1083 case ELK_SHADER_OPCODE_SEND:
1084 return send_has_side_effects;
1085
1086 case ELK_OPCODE_SYNC:
1087 case ELK_VEC4_OPCODE_UNTYPED_ATOMIC:
1088 case ELK_SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL:
1089 case ELK_SHADER_OPCODE_GFX4_SCRATCH_WRITE:
1090 case ELK_VEC4_OPCODE_UNTYPED_SURFACE_WRITE:
1091 case ELK_SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL:
1092 case ELK_SHADER_OPCODE_A64_UNTYPED_WRITE_LOGICAL:
1093 case ELK_SHADER_OPCODE_A64_BYTE_SCATTERED_WRITE_LOGICAL:
1094 case ELK_SHADER_OPCODE_A64_UNTYPED_ATOMIC_LOGICAL:
1095 case ELK_SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL:
1096 case ELK_SHADER_OPCODE_DWORD_SCATTERED_WRITE_LOGICAL:
1097 case ELK_SHADER_OPCODE_TYPED_ATOMIC_LOGICAL:
1098 case ELK_SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL:
1099 case ELK_SHADER_OPCODE_MEMORY_FENCE:
1100 case ELK_SHADER_OPCODE_INTERLOCK:
1101 case ELK_SHADER_OPCODE_URB_WRITE_LOGICAL:
1102 case ELK_FS_OPCODE_FB_WRITE:
1103 case ELK_FS_OPCODE_FB_WRITE_LOGICAL:
1104 case ELK_FS_OPCODE_REP_FB_WRITE:
1105 case ELK_SHADER_OPCODE_BARRIER:
1106 case ELK_VEC4_TCS_OPCODE_URB_WRITE:
1107 case ELK_TCS_OPCODE_RELEASE_INPUT:
1108 case ELK_SHADER_OPCODE_RND_MODE:
1109 case ELK_SHADER_OPCODE_FLOAT_CONTROL_MODE:
1110 case ELK_FS_OPCODE_SCHEDULING_FENCE:
1111 case ELK_SHADER_OPCODE_OWORD_BLOCK_WRITE_LOGICAL:
1112 case ELK_SHADER_OPCODE_A64_OWORD_BLOCK_WRITE_LOGICAL:
1113 case ELK_SHADER_OPCODE_BTD_SPAWN_LOGICAL:
1114 case ELK_SHADER_OPCODE_BTD_RETIRE_LOGICAL:
1115 case ELK_RT_OPCODE_TRACE_RAY_LOGICAL:
1116 case ELK_VEC4_OPCODE_ZERO_OOB_PUSH_REGS:
1117 return true;
1118 default:
1119 return eot;
1120 }
1121 }
1122
1123 bool
is_volatile() const1124 elk_backend_instruction::is_volatile() const
1125 {
1126 switch (opcode) {
1127 case ELK_SHADER_OPCODE_SEND:
1128 return send_is_volatile;
1129
1130 case ELK_VEC4_OPCODE_UNTYPED_SURFACE_READ:
1131 case ELK_SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL:
1132 case ELK_SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL:
1133 case ELK_SHADER_OPCODE_BYTE_SCATTERED_READ_LOGICAL:
1134 case ELK_SHADER_OPCODE_DWORD_SCATTERED_READ_LOGICAL:
1135 case ELK_SHADER_OPCODE_A64_UNTYPED_READ_LOGICAL:
1136 case ELK_SHADER_OPCODE_A64_BYTE_SCATTERED_READ_LOGICAL:
1137 case ELK_VEC4_OPCODE_URB_READ:
1138 return true;
1139 default:
1140 return false;
1141 }
1142 }
1143
1144 #ifndef NDEBUG
1145 static bool
inst_is_in_block(const elk_bblock_t * block,const elk_backend_instruction * inst)1146 inst_is_in_block(const elk_bblock_t *block, const elk_backend_instruction *inst)
1147 {
1148 const exec_node *n = inst;
1149
1150 /* Find the tail sentinel. If the tail sentinel is the sentinel from the
1151 * list header in the elk_bblock_t, then this instruction is in that basic
1152 * block.
1153 */
1154 while (!n->is_tail_sentinel())
1155 n = n->get_next();
1156
1157 return n == &block->instructions.tail_sentinel;
1158 }
1159 #endif
1160
1161 static void
adjust_later_block_ips(elk_bblock_t * start_block,int ip_adjustment)1162 adjust_later_block_ips(elk_bblock_t *start_block, int ip_adjustment)
1163 {
1164 for (elk_bblock_t *block_iter = start_block->next();
1165 block_iter;
1166 block_iter = block_iter->next()) {
1167 block_iter->start_ip += ip_adjustment;
1168 block_iter->end_ip += ip_adjustment;
1169 }
1170 }
1171
1172 void
insert_after(elk_bblock_t * block,elk_backend_instruction * inst)1173 elk_backend_instruction::insert_after(elk_bblock_t *block, elk_backend_instruction *inst)
1174 {
1175 assert(this != inst);
1176 assert(block->end_ip_delta == 0);
1177
1178 if (!this->is_head_sentinel())
1179 assert(inst_is_in_block(block, this) || !"Instruction not in block");
1180
1181 block->end_ip++;
1182
1183 adjust_later_block_ips(block, 1);
1184
1185 exec_node::insert_after(inst);
1186 }
1187
1188 void
insert_before(elk_bblock_t * block,elk_backend_instruction * inst)1189 elk_backend_instruction::insert_before(elk_bblock_t *block, elk_backend_instruction *inst)
1190 {
1191 assert(this != inst);
1192 assert(block->end_ip_delta == 0);
1193
1194 if (!this->is_tail_sentinel())
1195 assert(inst_is_in_block(block, this) || !"Instruction not in block");
1196
1197 block->end_ip++;
1198
1199 adjust_later_block_ips(block, 1);
1200
1201 exec_node::insert_before(inst);
1202 }
1203
1204 void
remove(elk_bblock_t * block,bool defer_later_block_ip_updates)1205 elk_backend_instruction::remove(elk_bblock_t *block, bool defer_later_block_ip_updates)
1206 {
1207 assert(inst_is_in_block(block, this) || !"Instruction not in block");
1208
1209 if (defer_later_block_ip_updates) {
1210 block->end_ip_delta--;
1211 } else {
1212 assert(block->end_ip_delta == 0);
1213 adjust_later_block_ips(block, -1);
1214 }
1215
1216 if (block->start_ip == block->end_ip) {
1217 if (block->end_ip_delta != 0) {
1218 adjust_later_block_ips(block, block->end_ip_delta);
1219 block->end_ip_delta = 0;
1220 }
1221
1222 block->cfg->remove_block(block);
1223 } else {
1224 block->end_ip--;
1225 }
1226
1227 exec_node::remove();
1228 }
1229
1230 void
dump_instructions(const char * name) const1231 elk_backend_shader::dump_instructions(const char *name) const
1232 {
1233 FILE *file = stderr;
1234 if (name && __normal_user()) {
1235 file = fopen(name, "w");
1236 if (!file)
1237 file = stderr;
1238 }
1239
1240 dump_instructions_to_file(file);
1241
1242 if (file != stderr) {
1243 fclose(file);
1244 }
1245 }
1246
1247 void
dump_instructions_to_file(FILE * file) const1248 elk_backend_shader::dump_instructions_to_file(FILE *file) const
1249 {
1250 if (cfg) {
1251 int ip = 0;
1252 foreach_block_and_inst(block, elk_backend_instruction, inst, cfg) {
1253 if (!INTEL_DEBUG(DEBUG_OPTIMIZER))
1254 fprintf(file, "%4d: ", ip++);
1255 dump_instruction(inst, file);
1256 }
1257 } else {
1258 int ip = 0;
1259 foreach_in_list(elk_backend_instruction, inst, &instructions) {
1260 if (!INTEL_DEBUG(DEBUG_OPTIMIZER))
1261 fprintf(file, "%4d: ", ip++);
1262 dump_instruction(inst, file);
1263 }
1264 }
1265 }
1266
1267 void
calculate_cfg()1268 elk_backend_shader::calculate_cfg()
1269 {
1270 if (this->cfg)
1271 return;
1272 cfg = new(mem_ctx) elk_cfg_t(this, &this->instructions);
1273 }
1274
1275 void
invalidate_analysis(elk::analysis_dependency_class c)1276 elk_backend_shader::invalidate_analysis(elk::analysis_dependency_class c)
1277 {
1278 idom_analysis.invalidate(c);
1279 }
1280
1281 extern "C" const unsigned *
elk_compile_tes(const struct elk_compiler * compiler,elk_compile_tes_params * params)1282 elk_compile_tes(const struct elk_compiler *compiler,
1283 elk_compile_tes_params *params)
1284 {
1285 const struct intel_device_info *devinfo = compiler->devinfo;
1286 nir_shader *nir = params->base.nir;
1287 const struct elk_tes_prog_key *key = params->key;
1288 const struct intel_vue_map *input_vue_map = params->input_vue_map;
1289 struct elk_tes_prog_data *prog_data = params->prog_data;
1290
1291 const bool is_scalar = compiler->scalar_stage[MESA_SHADER_TESS_EVAL];
1292 const bool debug_enabled = elk_should_print_shader(nir, DEBUG_TES);
1293 const unsigned *assembly;
1294
1295 prog_data->base.base.stage = MESA_SHADER_TESS_EVAL;
1296 prog_data->base.base.ray_queries = nir->info.ray_queries;
1297
1298 nir->info.inputs_read = key->inputs_read;
1299 nir->info.patch_inputs_read = key->patch_inputs_read;
1300
1301 elk_nir_apply_key(nir, compiler, &key->base, 8);
1302 elk_nir_lower_tes_inputs(nir, input_vue_map);
1303 elk_nir_lower_vue_outputs(nir);
1304 elk_postprocess_nir(nir, compiler, debug_enabled,
1305 key->base.robust_flags);
1306
1307 elk_compute_vue_map(devinfo, &prog_data->base.vue_map,
1308 nir->info.outputs_written,
1309 nir->info.separate_shader, 1);
1310
1311 unsigned output_size_bytes = prog_data->base.vue_map.num_slots * 4 * 4;
1312
1313 assert(output_size_bytes >= 1);
1314 if (output_size_bytes > GFX7_MAX_DS_URB_ENTRY_SIZE_BYTES) {
1315 params->base.error_str = ralloc_strdup(params->base.mem_ctx,
1316 "DS outputs exceed maximum size");
1317 return NULL;
1318 }
1319
1320 prog_data->base.clip_distance_mask =
1321 ((1 << nir->info.clip_distance_array_size) - 1);
1322 prog_data->base.cull_distance_mask =
1323 ((1 << nir->info.cull_distance_array_size) - 1) <<
1324 nir->info.clip_distance_array_size;
1325
1326 prog_data->include_primitive_id =
1327 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_PRIMITIVE_ID);
1328
1329 /* URB entry sizes are stored as a multiple of 64 bytes. */
1330 prog_data->base.urb_entry_size = ALIGN(output_size_bytes, 64) / 64;
1331
1332 prog_data->base.urb_read_length = 0;
1333
1334 STATIC_ASSERT(INTEL_TESS_PARTITIONING_INTEGER == TESS_SPACING_EQUAL - 1);
1335 STATIC_ASSERT(INTEL_TESS_PARTITIONING_ODD_FRACTIONAL ==
1336 TESS_SPACING_FRACTIONAL_ODD - 1);
1337 STATIC_ASSERT(INTEL_TESS_PARTITIONING_EVEN_FRACTIONAL ==
1338 TESS_SPACING_FRACTIONAL_EVEN - 1);
1339
1340 prog_data->partitioning =
1341 (enum intel_tess_partitioning) (nir->info.tess.spacing - 1);
1342
1343 switch (nir->info.tess._primitive_mode) {
1344 case TESS_PRIMITIVE_QUADS:
1345 prog_data->domain = INTEL_TESS_DOMAIN_QUAD;
1346 break;
1347 case TESS_PRIMITIVE_TRIANGLES:
1348 prog_data->domain = INTEL_TESS_DOMAIN_TRI;
1349 break;
1350 case TESS_PRIMITIVE_ISOLINES:
1351 prog_data->domain = INTEL_TESS_DOMAIN_ISOLINE;
1352 break;
1353 default:
1354 unreachable("invalid domain shader primitive mode");
1355 }
1356
1357 if (nir->info.tess.point_mode) {
1358 prog_data->output_topology = INTEL_TESS_OUTPUT_TOPOLOGY_POINT;
1359 } else if (nir->info.tess._primitive_mode == TESS_PRIMITIVE_ISOLINES) {
1360 prog_data->output_topology = INTEL_TESS_OUTPUT_TOPOLOGY_LINE;
1361 } else {
1362 /* Hardware winding order is backwards from OpenGL */
1363 prog_data->output_topology =
1364 nir->info.tess.ccw ? INTEL_TESS_OUTPUT_TOPOLOGY_TRI_CW
1365 : INTEL_TESS_OUTPUT_TOPOLOGY_TRI_CCW;
1366 }
1367
1368 if (unlikely(debug_enabled)) {
1369 fprintf(stderr, "TES Input ");
1370 elk_print_vue_map(stderr, input_vue_map, MESA_SHADER_TESS_EVAL);
1371 fprintf(stderr, "TES Output ");
1372 elk_print_vue_map(stderr, &prog_data->base.vue_map,
1373 MESA_SHADER_TESS_EVAL);
1374 }
1375
1376 if (is_scalar) {
1377 const unsigned dispatch_width = devinfo->ver >= 20 ? 16 : 8;
1378 elk_fs_visitor v(compiler, ¶ms->base, &key->base,
1379 &prog_data->base.base, nir, dispatch_width,
1380 params->base.stats != NULL, debug_enabled);
1381 if (!v.run_tes()) {
1382 params->base.error_str =
1383 ralloc_strdup(params->base.mem_ctx, v.fail_msg);
1384 return NULL;
1385 }
1386
1387 assert(v.payload().num_regs % reg_unit(devinfo) == 0);
1388 prog_data->base.base.dispatch_grf_start_reg = v.payload().num_regs / reg_unit(devinfo);
1389
1390 prog_data->base.dispatch_mode = INTEL_DISPATCH_MODE_SIMD8;
1391
1392 elk_fs_generator g(compiler, ¶ms->base,
1393 &prog_data->base.base, false, MESA_SHADER_TESS_EVAL);
1394 if (unlikely(debug_enabled)) {
1395 g.enable_debug(ralloc_asprintf(params->base.mem_ctx,
1396 "%s tessellation evaluation shader %s",
1397 nir->info.label ? nir->info.label
1398 : "unnamed",
1399 nir->info.name));
1400 }
1401
1402 g.generate_code(v.cfg, dispatch_width, v.shader_stats,
1403 v.performance_analysis.require(), params->base.stats);
1404
1405 g.add_const_data(nir->constant_data, nir->constant_data_size);
1406
1407 assembly = g.get_assembly();
1408 } else {
1409 elk::vec4_tes_visitor v(compiler, ¶ms->base, key, prog_data,
1410 nir, debug_enabled);
1411 if (!v.run()) {
1412 params->base.error_str =
1413 ralloc_strdup(params->base.mem_ctx, v.fail_msg);
1414 return NULL;
1415 }
1416
1417 if (unlikely(debug_enabled))
1418 v.dump_instructions();
1419
1420 assembly = elk_vec4_generate_assembly(compiler, ¶ms->base, nir,
1421 &prog_data->base, v.cfg,
1422 v.performance_analysis.require(),
1423 debug_enabled);
1424 }
1425
1426 return assembly;
1427 }
1428