1 /*
2 * Copyright © 2023 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include <assert.h>
25 #include <stdbool.h>
26
27 #include "util/macros.h"
28
29 #include "anv_private.h"
30
31 #include "genxml/gen_macros.h"
32 #include "genxml/genX_pack.h"
33 #include "common/intel_genX_state_brw.h"
34
35 static void
genX(emit_simpler_shader_init_fragment)36 genX(emit_simpler_shader_init_fragment)(struct anv_simple_shader *state)
37 {
38 assert(state->cmd_buffer == NULL ||
39 state->cmd_buffer->state.current_pipeline == _3D);
40
41 struct anv_batch *batch = state->batch;
42 struct anv_device *device = state->device;
43 const struct brw_wm_prog_data *prog_data =
44 brw_wm_prog_data_const(state->kernel->prog_data);
45
46 uint32_t *dw = anv_batch_emitn(batch,
47 1 + 2 * GENX(VERTEX_ELEMENT_STATE_length),
48 GENX(3DSTATE_VERTEX_ELEMENTS));
49 /* You might think there is some shady stuff going here and you would be
50 * right. We're setting up 2 VERTEX_ELEMENT_STATE yet we're only providing
51 * 1 (positions) VERTEX_BUFFER_STATE later.
52 *
53 * Find more about how to set up a 3D pipeline with a fragment shader but
54 * without a vertex shader in blorp_emit_vertex_elements() in
55 * blorp_genX_exec_brw.h.
56 */
57 GENX(VERTEX_ELEMENT_STATE_pack)(
58 batch, dw + 1, &(struct GENX(VERTEX_ELEMENT_STATE)) {
59 .VertexBufferIndex = 1,
60 .Valid = true,
61 .SourceElementFormat = ISL_FORMAT_R32G32B32A32_FLOAT,
62 .SourceElementOffset = 0,
63 .Component0Control = VFCOMP_STORE_SRC,
64 .Component1Control = VFCOMP_STORE_0,
65 .Component2Control = VFCOMP_STORE_0,
66 .Component3Control = VFCOMP_STORE_0,
67 });
68 GENX(VERTEX_ELEMENT_STATE_pack)(
69 batch, dw + 3, &(struct GENX(VERTEX_ELEMENT_STATE)) {
70 .VertexBufferIndex = 0,
71 .Valid = true,
72 .SourceElementFormat = ISL_FORMAT_R32G32B32_FLOAT,
73 .SourceElementOffset = 0,
74 .Component0Control = VFCOMP_STORE_SRC,
75 .Component1Control = VFCOMP_STORE_SRC,
76 .Component2Control = VFCOMP_STORE_SRC,
77 .Component3Control = VFCOMP_STORE_1_FP,
78 });
79
80 anv_batch_emit(batch, GENX(3DSTATE_VF_STATISTICS), vf);
81 anv_batch_emit(batch, GENX(3DSTATE_VF_SGVS), sgvs) {
82 sgvs.InstanceIDEnable = true;
83 sgvs.InstanceIDComponentNumber = COMP_1;
84 sgvs.InstanceIDElementOffset = 0;
85 }
86 #if GFX_VER >= 11
87 anv_batch_emit(batch, GENX(3DSTATE_VF_SGVS_2), sgvs);
88 #endif
89 anv_batch_emit(batch, GENX(3DSTATE_VF_INSTANCING), vfi) {
90 vfi.InstancingEnable = false;
91 vfi.VertexElementIndex = 0;
92 }
93 anv_batch_emit(batch, GENX(3DSTATE_VF_INSTANCING), vfi) {
94 vfi.InstancingEnable = false;
95 vfi.VertexElementIndex = 1;
96 }
97
98 anv_batch_emit(batch, GENX(3DSTATE_VF_TOPOLOGY), topo) {
99 topo.PrimitiveTopologyType = _3DPRIM_RECTLIST;
100 }
101
102 /* Emit URB setup. We tell it that the VS is active because we want it to
103 * allocate space for the VS. Even though one isn't run, we need VUEs to
104 * store the data that VF is going to pass to SOL.
105 */
106 struct intel_urb_config urb_cfg_out = {
107 .size = { DIV_ROUND_UP(32, 64), 1, 1, 1 },
108 };
109
110 genX(emit_l3_config)(batch, device, state->l3_config);
111
112 state->cmd_buffer->state.current_l3_config = state->l3_config;
113
114 enum intel_urb_deref_block_size deref_block_size;
115 genX(emit_urb_setup)(device, batch, state->l3_config,
116 VK_SHADER_STAGE_VERTEX_BIT | VK_SHADER_STAGE_FRAGMENT_BIT,
117 state->urb_cfg, &urb_cfg_out, &deref_block_size);
118
119 anv_batch_emit(batch, GENX(3DSTATE_PS_BLEND), ps_blend) {
120 ps_blend.HasWriteableRT = true;
121 }
122
123 anv_batch_emit(batch, GENX(3DSTATE_WM_DEPTH_STENCIL), wm);
124
125 #if GFX_VER >= 12
126 anv_batch_emit(batch, GENX(3DSTATE_DEPTH_BOUNDS), db) {
127 db.DepthBoundsTestEnable = false;
128 db.DepthBoundsTestMinValue = 0.0;
129 db.DepthBoundsTestMaxValue = 1.0;
130 }
131 #endif
132
133 anv_batch_emit(batch, GENX(3DSTATE_MULTISAMPLE), ms);
134 anv_batch_emit(batch, GENX(3DSTATE_SAMPLE_MASK), sm) {
135 sm.SampleMask = 0x1;
136 }
137
138 anv_batch_emit(batch, GENX(3DSTATE_VS), vs);
139 anv_batch_emit(batch, GENX(3DSTATE_HS), hs);
140 anv_batch_emit(batch, GENX(3DSTATE_TE), te);
141 anv_batch_emit(batch, GENX(3DSTATE_DS), DS);
142
143 #if GFX_VERx10 >= 125
144 if (device->vk.enabled_extensions.EXT_mesh_shader) {
145 anv_batch_emit(batch, GENX(3DSTATE_MESH_CONTROL), mesh);
146 anv_batch_emit(batch, GENX(3DSTATE_TASK_CONTROL), task);
147 }
148 #endif
149
150 anv_batch_emit(batch, GENX(3DSTATE_STREAMOUT), so);
151
152 anv_batch_emit(batch, GENX(3DSTATE_GS), gs);
153
154 anv_batch_emit(batch, GENX(3DSTATE_CLIP), clip) {
155 clip.PerspectiveDivideDisable = true;
156 }
157
158 anv_batch_emit(batch, GENX(3DSTATE_SF), sf) {
159 #if GFX_VER >= 12
160 sf.DerefBlockSize = deref_block_size;
161 #endif
162 }
163
164 anv_batch_emit(batch, GENX(3DSTATE_RASTER), raster) {
165 raster.CullMode = CULLMODE_NONE;
166 }
167
168 anv_batch_emit(batch, GENX(3DSTATE_SBE), sbe) {
169 sbe.VertexURBEntryReadOffset = 1;
170 sbe.NumberofSFOutputAttributes = prog_data->num_varying_inputs;
171 sbe.VertexURBEntryReadLength = MAX2((prog_data->num_varying_inputs + 1) / 2, 1);
172 sbe.ConstantInterpolationEnable = prog_data->flat_inputs;
173 sbe.ForceVertexURBEntryReadLength = true;
174 sbe.ForceVertexURBEntryReadOffset = true;
175 for (unsigned i = 0; i < 32; i++)
176 sbe.AttributeActiveComponentFormat[i] = ACF_XYZW;
177 }
178
179 anv_batch_emit(batch, GENX(3DSTATE_WM), wm);
180
181 anv_batch_emit(batch, GENX(3DSTATE_PS), ps) {
182 intel_set_ps_dispatch_state(&ps, device->info, prog_data,
183 1 /* rasterization_samples */,
184 0 /* msaa_flags */);
185
186 ps.VectorMaskEnable = prog_data->uses_vmask;
187
188 ps.BindingTableEntryCount = GFX_VER == 9 ? 1 : 0;
189 #if GFX_VER < 20
190 ps.PushConstantEnable = prog_data->base.nr_params > 0 ||
191 prog_data->base.ubo_ranges[0].length;
192 #endif
193
194 ps.DispatchGRFStartRegisterForConstantSetupData0 =
195 brw_wm_prog_data_dispatch_grf_start_reg(prog_data, ps, 0);
196 ps.DispatchGRFStartRegisterForConstantSetupData1 =
197 brw_wm_prog_data_dispatch_grf_start_reg(prog_data, ps, 1);
198 #if GFX_VER < 20
199 ps.DispatchGRFStartRegisterForConstantSetupData2 =
200 brw_wm_prog_data_dispatch_grf_start_reg(prog_data, ps, 2);
201 #endif
202
203 ps.KernelStartPointer0 = state->kernel->kernel.offset +
204 brw_wm_prog_data_prog_offset(prog_data, ps, 0);
205 ps.KernelStartPointer1 = state->kernel->kernel.offset +
206 brw_wm_prog_data_prog_offset(prog_data, ps, 1);
207 #if GFX_VER < 20
208 ps.KernelStartPointer2 = state->kernel->kernel.offset +
209 brw_wm_prog_data_prog_offset(prog_data, ps, 2);
210 #endif
211
212 ps.MaximumNumberofThreadsPerPSD = device->info->max_threads_per_psd - 1;
213 }
214
215 anv_batch_emit(batch, GENX(3DSTATE_PS_EXTRA), psx) {
216 psx.PixelShaderValid = true;
217 #if GFX_VER < 20
218 psx.AttributeEnable = prog_data->num_varying_inputs > 0;
219 #endif
220 psx.PixelShaderIsPerSample = prog_data->persample_dispatch;
221 psx.PixelShaderComputedDepthMode = prog_data->computed_depth_mode;
222 psx.PixelShaderComputesStencil = prog_data->computed_stencil;
223 }
224
225 anv_batch_emit(batch, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), cc) {
226 struct anv_state cc_state =
227 anv_state_stream_alloc(state->dynamic_state_stream,
228 4 * GENX(CC_VIEWPORT_length), 32);
229 if (cc_state.map == NULL)
230 return;
231
232 struct GENX(CC_VIEWPORT) cc_viewport = {
233 .MinimumDepth = 0.0f,
234 .MaximumDepth = 1.0f,
235 };
236 GENX(CC_VIEWPORT_pack)(NULL, cc_state.map, &cc_viewport);
237 cc.CCViewportPointer = cc_state.offset;
238 }
239
240 #if GFX_VER >= 12
241 /* Disable Primitive Replication. */
242 anv_batch_emit(batch, GENX(3DSTATE_PRIMITIVE_REPLICATION), pr);
243 #endif
244
245 anv_batch_emit(batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS), alloc);
246 anv_batch_emit(batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_HS), alloc);
247 anv_batch_emit(batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_DS), alloc);
248 anv_batch_emit(batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_GS), alloc);
249 anv_batch_emit(batch, GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS), alloc) {
250 alloc.ConstantBufferOffset = 0;
251 alloc.ConstantBufferSize = device->info->max_constant_urb_size_kb;
252 }
253
254 #if GFX_VERx10 == 125
255 /* DG2: Wa_22011440098
256 * MTL: Wa_18022330953
257 *
258 * In 3D mode, after programming push constant alloc command immediately
259 * program push constant command(ZERO length) without any commit between
260 * them.
261 *
262 * Note that Wa_16011448509 isn't needed here as all address bits are zero.
263 */
264 anv_batch_emit(batch, GENX(3DSTATE_CONSTANT_ALL), c) {
265 /* Update empty push constants for all stages (bitmask = 11111b) */
266 c.ShaderUpdateEnable = 0x1f;
267 c.MOCS = anv_mocs(device, NULL, 0);
268 }
269 #endif
270
271 #if GFX_VER == 9
272 /* Allocate a binding table for Gfx9 for 2 reason :
273 *
274 * 1. we need a to emit a 3DSTATE_BINDING_TABLE_POINTERS_PS to make the
275 * HW apply the preceeding 3DSTATE_CONSTANT_PS
276 *
277 * 2. Emitting an empty 3DSTATE_BINDING_TABLE_POINTERS_PS would cause RT
278 * writes (even though they're empty) to disturb later writes
279 * (probably due to RT cache)
280 *
281 * Our binding table only has one entry to the null surface.
282 */
283 uint32_t bt_offset;
284 state->bt_state =
285 anv_cmd_buffer_alloc_binding_table(state->cmd_buffer, 1, &bt_offset);
286 if (state->bt_state.map == NULL) {
287 VkResult result = anv_cmd_buffer_new_binding_table_block(state->cmd_buffer);
288 if (result != VK_SUCCESS)
289 return;
290
291 /* Re-emit state base addresses so we get the new surface state base
292 * address before we start emitting binding tables etc.
293 */
294 genX(cmd_buffer_emit_state_base_address)(state->cmd_buffer);
295
296 state->bt_state =
297 anv_cmd_buffer_alloc_binding_table(state->cmd_buffer, 1, &bt_offset);
298 assert(state->bt_state.map != NULL);
299 }
300
301 uint32_t *bt_map = state->bt_state.map;
302 bt_map[0] = anv_bindless_state_for_binding_table(
303 device,
304 device->null_surface_state).offset + bt_offset;
305
306 state->cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_FRAGMENT_BIT;
307 #endif
308
309 /* Flag all the instructions emitted by the memcpy. */
310 struct anv_gfx_dynamic_state *hw_state =
311 &state->cmd_buffer->state.gfx.dyn_state;
312
313 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_URB);
314 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VF_STATISTICS);
315 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VF);
316 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VF_TOPOLOGY);
317 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VERTEX_INPUT);
318 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VF_SGVS);
319 #if GFX_VER >= 11
320 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VF_SGVS_2);
321 #endif
322 #if GFX_VER >= 12
323 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_PRIMITIVE_REPLICATION);
324 #endif
325 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_STREAMOUT);
326 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VIEWPORT_CC);
327 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_CLIP);
328 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_RASTER);
329 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_SAMPLE_MASK);
330 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_MULTISAMPLE);
331 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_DEPTH_BOUNDS);
332 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_WM);
333 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_WM_DEPTH_STENCIL);
334 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_SF);
335 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_SBE);
336 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_VS);
337 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_HS);
338 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_DS);
339 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_TE);
340 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_GS);
341 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_PS);
342 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_PS_EXTRA);
343 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_PS_BLEND);
344 if (device->vk.enabled_extensions.EXT_mesh_shader) {
345 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_MESH_CONTROL);
346 BITSET_SET(hw_state->dirty, ANV_GFX_STATE_TASK_CONTROL);
347 }
348
349 /* Update urb config after simple shader. */
350 memcpy(&state->cmd_buffer->state.gfx.urb_cfg, &urb_cfg_out,
351 sizeof(struct intel_urb_config));
352
353 state->cmd_buffer->state.gfx.vb_dirty = BITFIELD_BIT(0);
354 state->cmd_buffer->state.gfx.dirty |= ~(ANV_CMD_DIRTY_INDEX_BUFFER |
355 ANV_CMD_DIRTY_XFB_ENABLE);
356 state->cmd_buffer->state.push_constants_dirty |= VK_SHADER_STAGE_FRAGMENT_BIT;
357 state->cmd_buffer->state.gfx.push_constant_stages = VK_SHADER_STAGE_FRAGMENT_BIT;
358 }
359
360 static void
genX(emit_simpler_shader_init_compute)361 genX(emit_simpler_shader_init_compute)(struct anv_simple_shader *state)
362 {
363 assert(state->cmd_buffer == NULL ||
364 state->cmd_buffer->state.current_pipeline == GPGPU);
365
366 #if GFX_VERx10 >= 125
367 struct anv_shader_bin *cs_bin = state->kernel;
368 const struct brw_cs_prog_data *prog_data =
369 (const struct brw_cs_prog_data *) cs_bin->prog_data;
370 /* Currently our simple shaders are simple enough that they never spill. */
371 assert(prog_data->base.total_scratch == 0);
372 if (state->cmd_buffer != NULL) {
373 genX(cmd_buffer_ensure_cfe_state)(state->cmd_buffer, 0);
374 } else {
375 anv_batch_emit(state->batch, GENX(CFE_STATE), cfe) {
376 cfe.MaximumNumberofThreads =
377 state->device->info->max_cs_threads *
378 state->device->info->subslice_total;
379 }
380 }
381 #endif
382 }
383
384 /** Initialize a simple shader emission */
385 void
genX(emit_simple_shader_init)386 genX(emit_simple_shader_init)(struct anv_simple_shader *state)
387 {
388 assert(state->kernel->stage == MESA_SHADER_FRAGMENT ||
389 state->kernel->stage == MESA_SHADER_COMPUTE);
390
391 if (state->kernel->stage == MESA_SHADER_FRAGMENT)
392 genX(emit_simpler_shader_init_fragment)(state);
393 else
394 genX(emit_simpler_shader_init_compute)(state);
395 }
396
397 /** Allocate push constant data for a simple shader */
398 struct anv_state
genX(simple_shader_alloc_push)399 genX(simple_shader_alloc_push)(struct anv_simple_shader *state, uint32_t size)
400 {
401 struct anv_state s;
402
403 if (state->kernel->stage == MESA_SHADER_FRAGMENT) {
404 s = anv_state_stream_alloc(state->dynamic_state_stream,
405 size, ANV_UBO_ALIGNMENT);
406 } else {
407 #if GFX_VERx10 >= 125
408 s = anv_state_stream_alloc(state->general_state_stream, align(size, 64), 64);
409 #else
410 s = anv_state_stream_alloc(state->dynamic_state_stream, size, 64);
411 #endif
412 }
413
414 if (s.map == NULL)
415 anv_batch_set_error(state->batch, VK_ERROR_OUT_OF_DEVICE_MEMORY);
416
417 return s;
418 }
419
420 /** Get the address of allocated push constant data by
421 * genX(simple_shader_alloc_push)
422 */
423 struct anv_address
genX(simple_shader_push_state_address)424 genX(simple_shader_push_state_address)(struct anv_simple_shader *state,
425 struct anv_state push_state)
426 {
427 if (state->kernel->stage == MESA_SHADER_FRAGMENT) {
428 return anv_state_pool_state_address(
429 &state->device->dynamic_state_pool, push_state);
430 } else {
431 #if GFX_VERx10 >= 125
432 return anv_state_pool_state_address(
433 &state->device->general_state_pool, push_state);
434 #else
435 return anv_state_pool_state_address(
436 &state->device->dynamic_state_pool, push_state);
437 #endif
438 }
439 }
440
441 /** Emit a simple shader dispatch */
442 void
genX(emit_simple_shader_dispatch)443 genX(emit_simple_shader_dispatch)(struct anv_simple_shader *state,
444 uint32_t num_threads,
445 struct anv_state push_state)
446 {
447 struct anv_device *device = state->device;
448 struct anv_batch *batch = state->batch;
449 struct anv_address push_addr =
450 anv_state_pool_state_address(&device->dynamic_state_pool, push_state);
451
452 if (state->kernel->stage == MESA_SHADER_FRAGMENT) {
453 /* At the moment we require a command buffer associated with this
454 * emission as we need to allocate binding tables on Gfx9.
455 */
456 assert(state->cmd_buffer != NULL);
457
458 struct anv_state vs_data_state =
459 anv_state_stream_alloc(state->dynamic_state_stream,
460 9 * sizeof(uint32_t), 32);
461 if (vs_data_state.map == NULL)
462 return;
463
464 float x0 = 0.0f, x1 = MIN2(num_threads, 8192);
465 float y0 = 0.0f, y1 = DIV_ROUND_UP(num_threads, 8192);
466 float z = 0.0f;
467
468 float *vertices = vs_data_state.map;
469 vertices[0] = x1; vertices[1] = y1; vertices[2] = z; /* v0 */
470 vertices[3] = x0; vertices[4] = y1; vertices[5] = z; /* v1 */
471 vertices[6] = x0; vertices[7] = y0; vertices[8] = z; /* v2 */
472
473 uint32_t *dw = anv_batch_emitn(batch,
474 1 + GENX(VERTEX_BUFFER_STATE_length),
475 GENX(3DSTATE_VERTEX_BUFFERS));
476 GENX(VERTEX_BUFFER_STATE_pack)(batch, dw + 1,
477 &(struct GENX(VERTEX_BUFFER_STATE)) {
478 .VertexBufferIndex = 0,
479 .AddressModifyEnable = true,
480 .BufferStartingAddress = (struct anv_address) {
481 .bo = device->dynamic_state_pool.block_pool.bo,
482 .offset = vs_data_state.offset,
483 },
484 .BufferPitch = 3 * sizeof(float),
485 .BufferSize = 9 * sizeof(float),
486 .MOCS = anv_mocs(device, NULL, 0),
487 #if GFX_VER >= 12
488 .L3BypassDisable = true,
489 #endif
490 });
491
492 #if GFX_VERx10 > 120
493 dw =
494 anv_batch_emitn(batch,
495 GENX(3DSTATE_CONSTANT_ALL_length) +
496 GENX(3DSTATE_CONSTANT_ALL_DATA_length),
497 GENX(3DSTATE_CONSTANT_ALL),
498 .ShaderUpdateEnable = BITFIELD_BIT(MESA_SHADER_FRAGMENT),
499 .PointerBufferMask = 0x1,
500 .MOCS = anv_mocs(device, NULL, 0));
501
502 GENX(3DSTATE_CONSTANT_ALL_DATA_pack)(
503 batch, dw + GENX(3DSTATE_CONSTANT_ALL_length),
504 &(struct GENX(3DSTATE_CONSTANT_ALL_DATA)) {
505 .PointerToConstantBuffer = push_addr,
506 .ConstantBufferReadLength = DIV_ROUND_UP(push_state.alloc_size, 32),
507 });
508 #else
509 /* The Skylake PRM contains the following restriction:
510 *
511 * "The driver must ensure The following case does not occur
512 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
513 * buffer 3 read length equal to zero committed followed by a
514 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
515 * zero committed."
516 *
517 * To avoid this, we program the highest slot.
518 */
519 anv_batch_emit(batch, GENX(3DSTATE_CONSTANT_PS), c) {
520 c.MOCS = anv_mocs(device, NULL, 0);
521 c.ConstantBody.ReadLength[3] = DIV_ROUND_UP(push_state.alloc_size, 32);
522 c.ConstantBody.Buffer[3] = push_addr;
523 }
524 #endif
525
526 #if GFX_VER == 9
527 /* Why are the push constants not flushed without a binding table
528 * update??
529 */
530 anv_batch_emit(batch, GENX(3DSTATE_BINDING_TABLE_POINTERS_PS), btp) {
531 btp.PointertoPSBindingTable = state->bt_state.offset;
532 }
533 #endif
534
535 genX(emit_breakpoint)(batch, device, true);
536 anv_batch_emit(batch, GENX(3DPRIMITIVE), prim) {
537 prim.VertexAccessType = SEQUENTIAL;
538 prim.PrimitiveTopologyType = _3DPRIM_RECTLIST;
539 prim.VertexCountPerInstance = 3;
540 prim.InstanceCount = 1;
541 }
542 genX(batch_emit_post_3dprimitive_was)(batch, device, _3DPRIM_RECTLIST, 3);
543 genX(emit_breakpoint)(batch, device, false);
544 } else {
545 const struct intel_device_info *devinfo = device->info;
546 const struct brw_cs_prog_data *prog_data =
547 (const struct brw_cs_prog_data *) state->kernel->prog_data;
548 const struct intel_cs_dispatch_info dispatch =
549 brw_cs_get_dispatch_info(devinfo, prog_data, NULL);
550
551 #if GFX_VERx10 >= 125
552 anv_batch_emit(batch, GENX(COMPUTE_WALKER), cw) {
553 cw.SIMDSize = dispatch.simd_size / 16;
554 cw.IndirectDataStartAddress = push_state.offset;
555 cw.IndirectDataLength = push_state.alloc_size;
556 cw.LocalXMaximum = prog_data->local_size[0] - 1;
557 cw.LocalYMaximum = prog_data->local_size[1] - 1;
558 cw.LocalZMaximum = prog_data->local_size[2] - 1;
559 cw.ThreadGroupIDXDimension = DIV_ROUND_UP(num_threads,
560 dispatch.simd_size);
561 cw.ThreadGroupIDYDimension = 1;
562 cw.ThreadGroupIDZDimension = 1;
563 cw.ExecutionMask = dispatch.right_mask;
564 cw.PostSync.MOCS = anv_mocs(device, NULL, 0);
565
566 #if GFX_VERx10 >= 125
567 cw.GenerateLocalID = prog_data->generate_local_id != 0;
568 cw.EmitLocal = prog_data->generate_local_id;
569 cw.WalkOrder = prog_data->walk_order;
570 cw.TileLayout = prog_data->walk_order == INTEL_WALK_ORDER_YXZ ?
571 TileY32bpe : Linear;
572 #endif
573
574 cw.InterfaceDescriptor = (struct GENX(INTERFACE_DESCRIPTOR_DATA)) {
575 .KernelStartPointer = state->kernel->kernel.offset +
576 brw_cs_prog_data_prog_offset(prog_data,
577 dispatch.simd_size),
578 .SamplerStatePointer = 0,
579 .BindingTablePointer = 0,
580 .BindingTableEntryCount = 0,
581 .NumberofThreadsinGPGPUThreadGroup = dispatch.threads,
582 .SharedLocalMemorySize = encode_slm_size(GFX_VER,
583 prog_data->base.total_shared),
584 .NumberOfBarriers = prog_data->uses_barrier,
585 };
586 }
587 #else
588 const uint32_t vfe_curbe_allocation =
589 ALIGN(prog_data->push.per_thread.regs * dispatch.threads +
590 prog_data->push.cross_thread.regs, 2);
591
592 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
593 *
594 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
595 * the only bits that are changed are scoreboard related: Scoreboard
596 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
597 * these scoreboard related states, a MEDIA_STATE_FLUSH is
598 * sufficient."
599 */
600 enum anv_pipe_bits emitted_bits = 0;
601 genX(emit_apply_pipe_flushes)(batch, device, GPGPU, ANV_PIPE_CS_STALL_BIT,
602 &emitted_bits);
603
604 /* If we have a command buffer allocated with the emission, update the
605 * pending bits.
606 */
607 if (state->cmd_buffer)
608 anv_cmd_buffer_update_pending_query_bits(state->cmd_buffer, emitted_bits);
609
610 anv_batch_emit(batch, GENX(MEDIA_VFE_STATE), vfe) {
611 vfe.StackSize = 0;
612 vfe.MaximumNumberofThreads =
613 devinfo->max_cs_threads * devinfo->subslice_total - 1;
614 vfe.NumberofURBEntries = 2;
615 #if GFX_VER < 11
616 vfe.ResetGatewayTimer = true;
617 #endif
618 vfe.URBEntryAllocationSize = 2;
619 vfe.CURBEAllocationSize = vfe_curbe_allocation;
620
621 if (prog_data->base.total_scratch) {
622 /* Broadwell's Per Thread Scratch Space is in the range [0, 11]
623 * where 0 = 1k, 1 = 2k, 2 = 4k, ..., 11 = 2M.
624 */
625 vfe.PerThreadScratchSpace =
626 ffs(prog_data->base.total_scratch) - 11;
627 vfe.ScratchSpaceBasePointer =
628 (struct anv_address) {
629 .bo = anv_scratch_pool_alloc(device,
630 &device->scratch_pool,
631 MESA_SHADER_COMPUTE,
632 prog_data->base.total_scratch),
633 .offset = 0,
634 };
635 }
636 }
637 struct anv_state iface_desc_state =
638 anv_state_stream_alloc(state->dynamic_state_stream,
639 GENX(INTERFACE_DESCRIPTOR_DATA_length) * 4, 64);
640 if (iface_desc_state.map == NULL)
641 return;
642
643 struct GENX(INTERFACE_DESCRIPTOR_DATA) iface_desc = {
644 .KernelStartPointer = state->kernel->kernel.offset +
645 brw_cs_prog_data_prog_offset(prog_data,
646 dispatch.simd_size),
647
648 .SamplerCount = 0,
649 .BindingTableEntryCount = 0,
650 .BarrierEnable = prog_data->uses_barrier,
651 .SharedLocalMemorySize = encode_slm_size(GFX_VER,
652 prog_data->base.total_shared),
653
654 .ConstantURBEntryReadOffset = 0,
655 .ConstantURBEntryReadLength = prog_data->push.per_thread.regs,
656 .CrossThreadConstantDataReadLength = prog_data->push.cross_thread.regs,
657 #if GFX_VER >= 12
658 /* TODO: Check if we are missing workarounds and enable mid-thread
659 * preemption.
660 *
661 * We still have issues with mid-thread preemption (it was already
662 * disabled by the kernel on gfx11, due to missing workarounds). It's
663 * possible that we are just missing some workarounds, and could
664 * enable it later, but for now let's disable it to fix a GPU in
665 * compute in Car Chase (and possibly more).
666 */
667 .ThreadPreemptionDisable = true,
668 #endif
669 .NumberofThreadsinGPGPUThreadGroup = dispatch.threads,
670 };
671 GENX(INTERFACE_DESCRIPTOR_DATA_pack)(batch, iface_desc_state.map, &iface_desc);
672 anv_batch_emit(batch, GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD), mid) {
673 mid.InterfaceDescriptorTotalLength = iface_desc_state.alloc_size;
674 mid.InterfaceDescriptorDataStartAddress = iface_desc_state.offset;
675 }
676 anv_batch_emit(batch, GENX(MEDIA_CURBE_LOAD), curbe) {
677 curbe.CURBEDataStartAddress = push_state.offset;
678 curbe.CURBETotalDataLength = push_state.alloc_size;
679 }
680 anv_batch_emit(batch, GENX(GPGPU_WALKER), ggw) {
681 ggw.SIMDSize = dispatch.simd_size / 16;
682 ggw.ThreadDepthCounterMaximum = 0;
683 ggw.ThreadHeightCounterMaximum = 0;
684 ggw.ThreadWidthCounterMaximum = dispatch.threads - 1;
685 ggw.ThreadGroupIDXDimension = DIV_ROUND_UP(num_threads,
686 dispatch.simd_size);
687 ggw.ThreadGroupIDYDimension = 1;
688 ggw.ThreadGroupIDZDimension = 1;
689 ggw.RightExecutionMask = dispatch.right_mask;
690 ggw.BottomExecutionMask = 0xffffffff;
691 }
692 #endif
693 }
694 }
695
696 void
genX(emit_simple_shader_end)697 genX(emit_simple_shader_end)(struct anv_simple_shader *state)
698 {
699 anv_batch_emit(state->batch, GENX(MI_BATCH_BUFFER_END), end);
700
701 if ((state->batch->next - state->batch->start) & 4)
702 anv_batch_emit(state->batch, GENX(MI_NOOP), noop);
703 }
704