1# 2# Copyright (C) 2018 Red Hat 3# Copyright (C) 2014 Intel Corporation 4# 5# Permission is hereby granted, free of charge, to any person obtaining a 6# copy of this software and associated documentation files (the "Software"), 7# to deal in the Software without restriction, including without limitation 8# the rights to use, copy, modify, merge, publish, distribute, sublicense, 9# and/or sell copies of the Software, and to permit persons to whom the 10# Software is furnished to do so, subject to the following conditions: 11# 12# The above copyright notice and this permission notice (including the next 13# paragraph) shall be included in all copies or substantial portions of the 14# Software. 15# 16# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 22# IN THE SOFTWARE. 23# 24 25# This file defines all the available intrinsics in one place. 26# 27# The Intrinsic class corresponds one-to-one with nir_intrinsic_info 28# structure. 29 30src0 = ('src', 0) 31src1 = ('src', 1) 32src2 = ('src', 2) 33src3 = ('src', 3) 34src4 = ('src', 4) 35 36class Index(object): 37 def __init__(self, c_data_type, name): 38 self.c_data_type = c_data_type 39 self.name = name 40 41class Intrinsic(object): 42 """Class that represents all the information about an intrinsic opcode. 43 NOTE: this must be kept in sync with nir_intrinsic_info. 44 """ 45 def __init__(self, name, src_components, dest_components, 46 indices, flags, sysval, bit_sizes): 47 """Parameters: 48 49 - name: the intrinsic name 50 - src_components: list of the number of components per src, 0 means 51 vectorized instruction with number of components given in the 52 num_components field in nir_intrinsic_instr. 53 - dest_components: number of destination components, -1 means no 54 dest, 0 means number of components given in num_components field 55 in nir_intrinsic_instr. 56 - indices: list of constant indicies 57 - flags: list of semantic flags 58 - sysval: is this a system-value intrinsic 59 - bit_sizes: allowed dest bit_sizes or the source it must match 60 """ 61 assert isinstance(name, str) 62 assert isinstance(src_components, list) 63 if src_components: 64 assert isinstance(src_components[0], int) 65 assert isinstance(dest_components, int) 66 assert isinstance(indices, list) 67 if indices: 68 assert isinstance(indices[0], Index) 69 assert isinstance(flags, list) 70 if flags: 71 assert isinstance(flags[0], str) 72 assert isinstance(sysval, bool) 73 if isinstance(bit_sizes, list): 74 assert not bit_sizes or isinstance(bit_sizes[0], int) 75 else: 76 assert isinstance(bit_sizes, tuple) 77 assert bit_sizes[0] == 'src' 78 assert isinstance(bit_sizes[1], int) 79 80 self.name = name 81 self.num_srcs = len(src_components) 82 self.src_components = src_components 83 self.has_dest = (dest_components >= 0) 84 self.dest_components = dest_components 85 self.num_indices = len(indices) 86 self.indices = indices 87 self.flags = flags 88 self.sysval = sysval 89 self.bit_sizes = bit_sizes if isinstance(bit_sizes, list) else [] 90 self.bit_size_src = bit_sizes[1] if isinstance(bit_sizes, tuple) else -1 91 92# 93# Possible flags: 94# 95 96CAN_ELIMINATE = "NIR_INTRINSIC_CAN_ELIMINATE" 97CAN_REORDER = "NIR_INTRINSIC_CAN_REORDER" 98 99INTR_INDICES = [] 100INTR_OPCODES = {} 101 102def index(c_data_type, name): 103 idx = Index(c_data_type, name) 104 INTR_INDICES.append(idx) 105 globals()[name.upper()] = idx 106 107# Defines a new NIR intrinsic. By default, the intrinsic will have no sources 108# and no destination. 109# 110# You can set dest_comp=n to enable a destination for the intrinsic, in which 111# case it will have that many components, or =0 for "as many components as the 112# NIR destination value." 113# 114# Set src_comp=n to enable sources for the intruction. It can be an array of 115# component counts, or (for convenience) a scalar component count if there's 116# only one source. If a component count is 0, it will be as many components as 117# the intrinsic has based on the dest_comp. 118def intrinsic(name, src_comp=[], dest_comp=-1, indices=[], 119 flags=[], sysval=False, bit_sizes=[]): 120 assert name not in INTR_OPCODES 121 INTR_OPCODES[name] = Intrinsic(name, src_comp, dest_comp, 122 indices, flags, sysval, bit_sizes) 123 124# 125# Possible indices: 126# 127 128# Generally instructions that take a offset src argument, can encode 129# a constant 'base' value which is added to the offset. 130index("int", "base") 131 132# For store instructions, a writemask for the store. 133index("unsigned", "write_mask") 134 135# The stream-id for GS emit_vertex/end_primitive intrinsics. 136index("unsigned", "stream_id") 137 138# The clip-plane id for load_user_clip_plane intrinsic. 139index("unsigned", "ucp_id") 140 141# The offset to the start of the NIR_INTRINSIC_RANGE. This is an alternative 142# to NIR_INTRINSIC_BASE for describing the valid range in intrinsics that don't 143# have the implicit addition of a base to the offset. 144# 145# If the [range_base, range] is [0, ~0], then we don't know the possible 146# range of the access. 147index("unsigned", "range_base") 148 149# The amount of data, starting from BASE or RANGE_BASE, that this 150# instruction may access. This is used to provide bounds if the offset is 151# not constant. 152index("unsigned", "range") 153 154# The Vulkan descriptor set for vulkan_resource_index intrinsic. 155index("unsigned", "desc_set") 156 157# The Vulkan descriptor set binding for vulkan_resource_index intrinsic. 158index("unsigned", "binding") 159 160# Component offset 161index("unsigned", "component") 162 163# Column index for matrix system values 164index("unsigned", "column") 165 166# Interpolation mode (only meaningful for FS inputs) 167index("unsigned", "interp_mode") 168 169# A binary nir_op to use when performing a reduction or scan operation 170index("unsigned", "reduction_op") 171 172# Cluster size for reduction operations 173index("unsigned", "cluster_size") 174 175# Parameter index for a load_param intrinsic 176index("unsigned", "param_idx") 177 178# Image dimensionality for image intrinsics 179index("enum glsl_sampler_dim", "image_dim") 180 181# Non-zero if we are accessing an array image 182index("bool", "image_array") 183 184# Image format for image intrinsics 185# Vertex buffer format for load_typed_buffer_amd 186index("enum pipe_format", "format") 187 188# Access qualifiers for image and memory access intrinsics. ACCESS_RESTRICT is 189# not set at the intrinsic if the NIR was created from SPIR-V. 190index("enum gl_access_qualifier", "access") 191 192# call index for split raytracing shaders 193index("unsigned", "call_idx") 194 195# The stack size increment/decrement for split raytracing shaders 196index("unsigned", "stack_size") 197 198# Alignment for offsets and addresses 199# 200# These two parameters, specify an alignment in terms of a multiplier and 201# an offset. The multiplier is always a power of two. The offset or 202# address parameter X of the intrinsic is guaranteed to satisfy the 203# following: 204# 205# (X - align_offset) % align_mul == 0 206# 207# For constant offset values, align_mul will be NIR_ALIGN_MUL_MAX and the 208# align_offset will be modulo that. 209index("unsigned", "align_mul") 210index("unsigned", "align_offset") 211 212# The Vulkan descriptor type for a vulkan_resource_[re]index intrinsic. 213index("unsigned", "desc_type") 214 215# The nir_alu_type of input data to a store or conversion 216index("nir_alu_type", "src_type") 217 218# The nir_alu_type of the data output from a load or conversion 219index("nir_alu_type", "dest_type") 220 221# The swizzle mask for quad_swizzle_amd & masked_swizzle_amd 222index("unsigned", "swizzle_mask") 223 224# Allow FI=1 for quad_swizzle_amd & masked_swizzle_amd 225index("bool", "fetch_inactive") 226 227# Offsets for load_shared2_amd/store_shared2_amd 228index("uint8_t", "offset0") 229index("uint8_t", "offset1") 230 231# If true, both offsets have an additional stride of 64 dwords (ie. they are multiplied by 256 bytes 232# in hardware, instead of 4). 233index("bool", "st64") 234 235# When set, range analysis will use it for nir_unsigned_upper_bound 236index("unsigned", "arg_upper_bound_u32_amd") 237 238# Separate source/dest access flags for copies 239index("enum gl_access_qualifier", "dst_access") 240index("enum gl_access_qualifier", "src_access") 241 242# Driver location of attribute 243index("unsigned", "driver_location") 244 245# Ordering and visibility of a memory operation 246index("nir_memory_semantics", "memory_semantics") 247 248# Modes affected by a memory operation 249index("nir_variable_mode", "memory_modes") 250 251# Scope of a memory operation 252index("mesa_scope", "memory_scope") 253 254# Scope of a control barrier 255index("mesa_scope", "execution_scope") 256 257# Semantics of an IO instruction 258index("struct nir_io_semantics", "io_semantics") 259 260# Transform feedback info 261index("struct nir_io_xfb", "io_xfb") 262index("struct nir_io_xfb", "io_xfb2") 263 264# Ray query values accessible from the RayQueryKHR object 265index("nir_ray_query_value", "ray_query_value") 266 267# Select between committed and candidate ray queriy intersections 268index("bool", "committed") 269 270# Rounding mode for conversions 271index("nir_rounding_mode", "rounding_mode") 272 273# Whether or not to saturate in conversions 274index("unsigned", "saturate") 275 276# Whether or not trace_ray_intel is synchronous 277index("bool", "synchronous") 278 279# Value ID to identify SSA value loaded/stored on the stack 280index("unsigned", "value_id") 281 282# Whether to sign-extend offsets in address arithmatic (else zero extend) 283index("bool", "sign_extend") 284 285# Instruction specific flags 286index("unsigned", "flags") 287 288# Logical operation of an atomic intrinsic 289index("nir_atomic_op", "atomic_op") 290 291# Block identifier to push promotion 292index("unsigned", "resource_block_intel") 293 294# Various flags describing the resource access 295index("nir_resource_data_intel", "resource_access_intel") 296 297# Register metadata 298# number of vector components 299index("unsigned", "num_components") 300# size of array (0 for no array) 301index("unsigned", "num_array_elems") 302# The bit-size of each channel; must be one of 1, 8, 16, 32, or 64 303index("unsigned", "bit_size") 304# True if this register may have different values in different SIMD invocations 305# of the shader. 306index("bool", "divergent") 307 308# On a register load, floating-point absolute value/negate loaded value. 309index("bool", "legacy_fabs") 310index("bool", "legacy_fneg") 311 312# On a register store, floating-point saturate the stored value. 313index("bool", "legacy_fsat") 314 315# For Cooperative Matrix intrinsics. 316index("struct glsl_cmat_description", "cmat_desc") 317index("enum glsl_matrix_layout", "matrix_layout") 318index("nir_cmat_signed", "cmat_signed_mask") 319index("nir_op", "alu_op") 320 321# For Intel DPAS instrinsic. 322index("unsigned", "systolic_depth") 323index("unsigned", "repeat_count") 324 325intrinsic("nop", flags=[CAN_ELIMINATE]) 326 327intrinsic("convert_alu_types", dest_comp=0, src_comp=[0], 328 indices=[SRC_TYPE, DEST_TYPE, ROUNDING_MODE, SATURATE], 329 flags=[CAN_ELIMINATE, CAN_REORDER]) 330 331intrinsic("load_param", dest_comp=0, indices=[PARAM_IDX], flags=[CAN_ELIMINATE]) 332 333intrinsic("load_deref", dest_comp=0, src_comp=[-1], 334 indices=[ACCESS], flags=[CAN_ELIMINATE]) 335intrinsic("store_deref", src_comp=[-1, 0], indices=[WRITE_MASK, ACCESS]) 336intrinsic("copy_deref", src_comp=[-1, -1], indices=[DST_ACCESS, SRC_ACCESS]) 337intrinsic("memcpy_deref", src_comp=[-1, -1, 1], indices=[DST_ACCESS, SRC_ACCESS]) 338 339# Returns an opaque handle representing a register indexed by BASE. The 340# logically def-use list of a register is given by the use list of this handle. 341# The shape of the underlying register is given by the indices, the handle 342# itself is always a 32-bit scalar. 343intrinsic("decl_reg", dest_comp=1, 344 indices=[NUM_COMPONENTS, NUM_ARRAY_ELEMS, BIT_SIZE, DIVERGENT], 345 flags=[CAN_ELIMINATE]) 346 347# Load a register given as the source directly with base offset BASE. 348intrinsic("load_reg", dest_comp=0, src_comp=[1], 349 indices=[BASE, LEGACY_FABS, LEGACY_FNEG], flags=[CAN_ELIMINATE]) 350 351# Load a register given as first source indirectly with base offset BASE and 352# indirect offset as second source. 353intrinsic("load_reg_indirect", dest_comp=0, src_comp=[1, 1], 354 indices=[BASE, LEGACY_FABS, LEGACY_FNEG], flags=[CAN_ELIMINATE]) 355 356# Store the value in the first source to a register given as the second source 357# directly with base offset BASE. 358intrinsic("store_reg", src_comp=[0, 1], 359 indices=[BASE, WRITE_MASK, LEGACY_FSAT]) 360 361# Store the value in the first source to a register given as the second 362# source indirectly with base offset BASE and indirect offset as third source. 363intrinsic("store_reg_indirect", src_comp=[0, 1, 1], 364 indices=[BASE, WRITE_MASK, LEGACY_FSAT]) 365 366# Interpolation of input. The interp_deref_at* intrinsics are similar to the 367# load_var intrinsic acting on a shader input except that they interpolate the 368# input differently. The at_sample, at_offset and at_vertex intrinsics take an 369# additional source that is an integer sample id, a vec2 position offset, or a 370# vertex ID respectively. 371 372intrinsic("interp_deref_at_centroid", dest_comp=0, src_comp=[1], 373 flags=[ CAN_ELIMINATE, CAN_REORDER]) 374intrinsic("interp_deref_at_sample", src_comp=[1, 1], dest_comp=0, 375 flags=[CAN_ELIMINATE, CAN_REORDER]) 376intrinsic("interp_deref_at_offset", src_comp=[1, 2], dest_comp=0, 377 flags=[CAN_ELIMINATE, CAN_REORDER]) 378intrinsic("interp_deref_at_vertex", src_comp=[1, 1], dest_comp=0, 379 flags=[CAN_ELIMINATE, CAN_REORDER]) 380 381# Gets the length of an unsized array at the end of a buffer 382intrinsic("deref_buffer_array_length", src_comp=[-1], dest_comp=1, 383 indices=[ACCESS], flags=[CAN_ELIMINATE, CAN_REORDER]) 384 385# Ask the driver for the size of a given SSBO. It takes the buffer index 386# as source. 387intrinsic("get_ssbo_size", src_comp=[-1], dest_comp=1, bit_sizes=[32], 388 indices=[ACCESS], flags=[CAN_ELIMINATE, CAN_REORDER]) 389intrinsic("get_ubo_size", src_comp=[-1], dest_comp=1, 390 flags=[CAN_ELIMINATE, CAN_REORDER]) 391 392# Intrinsics which provide a run-time mode-check. Unlike the compile-time 393# mode checks, a pointer can only have exactly one mode at runtime. 394intrinsic("deref_mode_is", src_comp=[-1], dest_comp=1, 395 indices=[MEMORY_MODES], flags=[CAN_ELIMINATE, CAN_REORDER]) 396intrinsic("addr_mode_is", src_comp=[-1], dest_comp=1, 397 indices=[MEMORY_MODES], flags=[CAN_ELIMINATE, CAN_REORDER]) 398 399intrinsic("is_sparse_texels_resident", dest_comp=1, src_comp=[1], bit_sizes=[1,32], 400 flags=[CAN_ELIMINATE, CAN_REORDER]) 401# result code is resident only if both inputs are resident 402intrinsic("sparse_residency_code_and", dest_comp=1, src_comp=[1, 1], bit_sizes=[32], 403 flags=[CAN_ELIMINATE, CAN_REORDER]) 404 405# a barrier is an intrinsic with no inputs/outputs but which can't be moved 406# around/optimized in general 407def barrier(name): 408 intrinsic(name) 409 410barrier("discard") 411 412# Demote fragment shader invocation to a helper invocation. Any stores to 413# memory after this instruction are suppressed and the fragment does not write 414# outputs to the framebuffer. Unlike discard, demote needs to ensure that 415# derivatives will still work for invocations that were not demoted. 416# 417# As specified by SPV_EXT_demote_to_helper_invocation. 418barrier("demote") 419intrinsic("is_helper_invocation", dest_comp=1, flags=[CAN_ELIMINATE]) 420 421# SpvOpTerminateInvocation from SPIR-V. Essentially a discard "for real". 422barrier("terminate") 423 424# Control/Memory barrier with explicit scope. Follows the semantics of SPIR-V 425# OpMemoryBarrier and OpControlBarrier, used to implement Vulkan Memory Model. 426# Storage that the barrier applies is represented using NIR variable modes. 427# For an OpMemoryBarrier, set EXECUTION_SCOPE to SCOPE_NONE. 428intrinsic("barrier", 429 indices=[EXECUTION_SCOPE, MEMORY_SCOPE, MEMORY_SEMANTICS, MEMORY_MODES]) 430 431# Shader clock intrinsic with semantics analogous to the clock2x32ARB() 432# GLSL intrinsic. 433# The latter can be used as code motion barrier, which is currently not 434# feasible with NIR. 435intrinsic("shader_clock", dest_comp=2, bit_sizes=[32], flags=[CAN_ELIMINATE], 436 indices=[MEMORY_SCOPE]) 437 438# Shader ballot intrinsics with semantics analogous to the 439# 440# ballotARB() 441# readInvocationARB() 442# readFirstInvocationARB() 443# 444# GLSL functions from ARB_shader_ballot. 445intrinsic("ballot", src_comp=[1], dest_comp=0, flags=[CAN_ELIMINATE]) 446intrinsic("read_invocation", src_comp=[0, 1], dest_comp=0, bit_sizes=src0, flags=[CAN_ELIMINATE]) 447intrinsic("read_first_invocation", src_comp=[0], dest_comp=0, bit_sizes=src0, flags=[CAN_ELIMINATE]) 448 449# Same as ballot, but inactive invocations contribute undefined bits. 450intrinsic("ballot_relaxed", src_comp=[1], dest_comp=0, flags=[CAN_ELIMINATE]) 451 452# Allows the backend compiler to move this value to an uniform register. 453# Result is undefined if src is not uniform. 454# Unlike read_first_invocation, it may be replaced by a divergent move or CSE'd. 455intrinsic("as_uniform", src_comp=[0], dest_comp=0, bit_sizes=src0, flags=[CAN_ELIMINATE]) 456 457# Returns the value of the first source for the lane where the second source is 458# true. The second source must be true for exactly one lane. 459intrinsic("read_invocation_cond_ir3", src_comp=[0, 1], dest_comp=0, flags=[CAN_ELIMINATE]) 460 461# Additional SPIR-V ballot intrinsics 462# 463# These correspond to the SPIR-V opcodes 464# 465# OpGroupNonUniformElect 466# OpSubgroupFirstInvocationKHR 467# OpGroupNonUniformInverseBallot 468intrinsic("elect", dest_comp=1, flags=[CAN_ELIMINATE]) 469intrinsic("first_invocation", dest_comp=1, bit_sizes=[32], flags=[CAN_ELIMINATE]) 470intrinsic("last_invocation", dest_comp=1, bit_sizes=[32], flags=[CAN_ELIMINATE]) 471intrinsic("inverse_ballot", src_comp=[0], dest_comp=1, flags=[CAN_ELIMINATE]) 472 473barrier("begin_invocation_interlock") 474barrier("end_invocation_interlock") 475 476# A conditional discard/demote/terminate, with a single boolean source. 477intrinsic("discard_if", src_comp=[1]) 478intrinsic("demote_if", src_comp=[1]) 479intrinsic("terminate_if", src_comp=[1]) 480 481# ARB_shader_group_vote intrinsics 482intrinsic("vote_any", src_comp=[1], dest_comp=1, flags=[CAN_ELIMINATE]) 483intrinsic("vote_all", src_comp=[1], dest_comp=1, flags=[CAN_ELIMINATE]) 484intrinsic("vote_feq", src_comp=[0], dest_comp=1, flags=[CAN_ELIMINATE]) 485intrinsic("vote_ieq", src_comp=[0], dest_comp=1, flags=[CAN_ELIMINATE]) 486 487# Ballot ALU operations from SPIR-V. 488# 489# These operations work like their ALU counterparts except that the operate 490# on a uvec4 which is treated as a 128bit integer. Also, they are, in 491# general, free to ignore any bits which are above the subgroup size. 492intrinsic("ballot_bitfield_extract", src_comp=[4, 1], dest_comp=1, flags=[CAN_ELIMINATE]) 493intrinsic("ballot_bit_count_reduce", src_comp=[4], dest_comp=1, flags=[CAN_ELIMINATE]) 494intrinsic("ballot_bit_count_inclusive", src_comp=[4], dest_comp=1, flags=[CAN_ELIMINATE]) 495intrinsic("ballot_bit_count_exclusive", src_comp=[4], dest_comp=1, flags=[CAN_ELIMINATE]) 496intrinsic("ballot_find_lsb", src_comp=[4], dest_comp=1, flags=[CAN_ELIMINATE]) 497intrinsic("ballot_find_msb", src_comp=[4], dest_comp=1, flags=[CAN_ELIMINATE]) 498 499# Shuffle operations from SPIR-V. 500intrinsic("shuffle", src_comp=[0, 1], dest_comp=0, bit_sizes=src0, flags=[CAN_ELIMINATE]) 501intrinsic("shuffle_xor", src_comp=[0, 1], dest_comp=0, bit_sizes=src0, flags=[CAN_ELIMINATE]) 502intrinsic("shuffle_up", src_comp=[0, 1], dest_comp=0, bit_sizes=src0, flags=[CAN_ELIMINATE]) 503intrinsic("shuffle_down", src_comp=[0, 1], dest_comp=0, bit_sizes=src0, flags=[CAN_ELIMINATE]) 504 505# Quad operations from SPIR-V. 506intrinsic("quad_broadcast", src_comp=[0, 1], dest_comp=0, bit_sizes=src0, flags=[CAN_ELIMINATE]) 507intrinsic("quad_swap_horizontal", src_comp=[0], dest_comp=0, bit_sizes=src0, flags=[CAN_ELIMINATE]) 508intrinsic("quad_swap_vertical", src_comp=[0], dest_comp=0, bit_sizes=src0, flags=[CAN_ELIMINATE]) 509intrinsic("quad_swap_diagonal", src_comp=[0], dest_comp=0, bit_sizes=src0, flags=[CAN_ELIMINATE]) 510 511# Similar to vote_any and vote_all, but per-quad instead of per-wavefront. 512# Equivalent to subgroupOr(val, 4) and subgroupAnd(val, 4) assuming val is 513# boolean. 514intrinsic("quad_vote_any", src_comp=[1], dest_comp=1, flags=[CAN_ELIMINATE]) 515intrinsic("quad_vote_all", src_comp=[1], dest_comp=1, flags=[CAN_ELIMINATE]) 516 517# Rotate operation from SPIR-V: SpvOpGroupNonUniformRotateKHR. 518intrinsic("rotate", src_comp=[0, 1], dest_comp=0, bit_sizes=src0, 519 indices=[EXECUTION_SCOPE, CLUSTER_SIZE], flags=[CAN_ELIMINATE]); 520 521intrinsic("reduce", src_comp=[0], dest_comp=0, bit_sizes=src0, 522 indices=[REDUCTION_OP, CLUSTER_SIZE], flags=[CAN_ELIMINATE]) 523intrinsic("inclusive_scan", src_comp=[0], dest_comp=0, bit_sizes=src0, 524 indices=[REDUCTION_OP], flags=[CAN_ELIMINATE]) 525intrinsic("exclusive_scan", src_comp=[0], dest_comp=0, bit_sizes=src0, 526 indices=[REDUCTION_OP], flags=[CAN_ELIMINATE]) 527 528# AMD shader ballot operations 529intrinsic("quad_swizzle_amd", src_comp=[0], dest_comp=0, bit_sizes=src0, 530 indices=[SWIZZLE_MASK, FETCH_INACTIVE], flags=[CAN_ELIMINATE]) 531intrinsic("masked_swizzle_amd", src_comp=[0], dest_comp=0, bit_sizes=src0, 532 indices=[SWIZZLE_MASK, FETCH_INACTIVE], flags=[CAN_ELIMINATE]) 533intrinsic("write_invocation_amd", src_comp=[0, 0, 1], dest_comp=0, bit_sizes=src0, 534 flags=[CAN_ELIMINATE]) 535# src = [ mask, addition ] 536intrinsic("mbcnt_amd", src_comp=[1, 1], dest_comp=1, bit_sizes=[32], flags=[CAN_ELIMINATE]) 537# Compiled to v_permlane16_b32. src = [ value, lanesel_lo, lanesel_hi ] 538intrinsic("lane_permute_16_amd", src_comp=[1, 1, 1], dest_comp=1, bit_sizes=[32], flags=[CAN_ELIMINATE]) 539 540# Basic Geometry Shader intrinsics. 541# 542# emit_vertex implements GLSL's EmitStreamVertex() built-in. It takes a single 543# index, which is the stream ID to write to. 544# 545# end_primitive implements GLSL's EndPrimitive() built-in. 546intrinsic("emit_vertex", indices=[STREAM_ID]) 547intrinsic("end_primitive", indices=[STREAM_ID]) 548 549# Geometry Shader intrinsics with a vertex count. 550# 551# Alternatively, drivers may implement these intrinsics, and use 552# nir_lower_gs_intrinsics() to convert from the basic intrinsics. 553# 554# These contain four additional unsigned integer sources: 555# 1. The total number of vertices emitted so far. 556# 2. The number of vertices emitted for the current primitive 557# so far if we're counting, otherwise undef. 558# 3. The total number of primitives emitted so far. 559# 4. The total number of decomposed primitives emitted so far. This counts like 560# the PRIMITIVES_GENERATED query: a triangle strip with 5 vertices is counted 561# as 3 primitives (not 1). 562intrinsic("emit_vertex_with_counter", src_comp=[1, 1, 1, 1], indices=[STREAM_ID]) 563intrinsic("end_primitive_with_counter", src_comp=[1, 1, 1, 1], indices=[STREAM_ID]) 564# Contains the final total vertex, primitive, and decomposed primitives counts 565# in the current GS thread. 566intrinsic("set_vertex_and_primitive_count", src_comp=[1, 1, 1], indices=[STREAM_ID]) 567 568# Launches mesh shader workgroups from a task shader, with explicit task_payload. 569# Rules: 570# - This is a terminating instruction. 571# - May only occur in workgroup-uniform control flow. 572# - Dispatch sizes may be divergent (in which case the values 573# from the first invocation are used). 574# Meaning of indices: 575# - BASE: address of the task_payload variable used. 576# - RANGE: size of the task_payload variable used. 577# 578# src[] = {vec(x, y, z)} 579intrinsic("launch_mesh_workgroups", src_comp=[3], indices=[BASE, RANGE]) 580 581# Launches mesh shader workgroups from a task shader, with task_payload variable deref. 582# Same rules as launch_mesh_workgroups apply here as well. 583# src[] = {vec(x, y, z), payload pointer} 584intrinsic("launch_mesh_workgroups_with_payload_deref", src_comp=[3, -1], indices=[]) 585 586# Trace a ray through an acceleration structure 587# 588# This instruction has a lot of parameters: 589# 0. Acceleration Structure 590# 1. Ray Flags 591# 2. Cull Mask 592# 3. SBT Offset 593# 4. SBT Stride 594# 5. Miss shader index 595# 6. Ray Origin 596# 7. Ray Tmin 597# 8. Ray Direction 598# 9. Ray Tmax 599# 10. Payload 600intrinsic("trace_ray", src_comp=[-1, 1, 1, 1, 1, 1, 3, 1, 3, 1, -1]) 601# src[] = { hit_t, hit_kind } 602intrinsic("report_ray_intersection", src_comp=[1, 1], dest_comp=1) 603intrinsic("ignore_ray_intersection") 604intrinsic("accept_ray_intersection") # Not in SPIR-V; useful for lowering 605intrinsic("terminate_ray") 606# src[] = { sbt_index, payload } 607intrinsic("execute_callable", src_comp=[1, -1]) 608 609# Initialize a ray query 610# 611# 0. Ray Query 612# 1. Acceleration Structure 613# 2. Ray Flags 614# 3. Cull Mask 615# 4. Ray Origin 616# 5. Ray Tmin 617# 6. Ray Direction 618# 7. Ray Tmax 619intrinsic("rq_initialize", src_comp=[-1, -1, 1, 1, 3, 1, 3, 1]) 620# src[] = { query } 621intrinsic("rq_terminate", src_comp=[-1]) 622# src[] = { query } 623intrinsic("rq_proceed", src_comp=[-1], dest_comp=1) 624# src[] = { query, hit } 625intrinsic("rq_generate_intersection", src_comp=[-1, 1]) 626# src[] = { query } 627intrinsic("rq_confirm_intersection", src_comp=[-1]) 628# src[] = { query } 629intrinsic("rq_load", src_comp=[-1], dest_comp=0, indices=[RAY_QUERY_VALUE,COMMITTED,COLUMN]) 630 631# Driver independent raytracing helpers 632 633# rt_resume is a helper that that be the first instruction accesing the 634# stack/scratch in a resume shader for a raytracing pipeline. It includes the 635# resume index (for nir_lower_shader_calls_internal reasons) and the stack size 636# of the variables spilled during the call. The stack size can be use to e.g. 637# adjust a stack pointer. 638intrinsic("rt_resume", indices=[CALL_IDX, STACK_SIZE]) 639 640# Lowered version of execute_callabe that includes the index of the resume 641# shader, and the amount of scratch space needed for this call (.ie. how much 642# to increase a stack pointer by). 643# src[] = { sbt_index, payload } 644intrinsic("rt_execute_callable", src_comp=[1, -1], indices=[CALL_IDX,STACK_SIZE]) 645 646# Lowered version of trace_ray in a similar vein to rt_execute_callable. 647# src same as trace_ray 648intrinsic("rt_trace_ray", src_comp=[-1, 1, 1, 1, 1, 1, 3, 1, 3, 1, -1], 649 indices=[CALL_IDX, STACK_SIZE]) 650 651 652# Atomic counters 653# 654# The *_deref variants take an atomic_uint nir_variable, while the other, 655# lowered, variants take a buffer index and register offset. The buffer index 656# is always constant, as there's no way to declare an array of atomic counter 657# buffers. 658# 659# The register offset may be non-constant but must by dynamically uniform 660# ("Atomic counters aggregated into arrays within a shader can only be indexed 661# with dynamically uniform integral expressions, otherwise results are 662# undefined.") 663def atomic(name, flags=[]): 664 intrinsic(name + "_deref", src_comp=[-1], dest_comp=1, flags=flags) 665 intrinsic(name, src_comp=[1], dest_comp=1, indices=[BASE, RANGE_BASE], flags=flags) 666 667def atomic2(name): 668 intrinsic(name + "_deref", src_comp=[-1, 1], dest_comp=1) 669 intrinsic(name, src_comp=[1, 1], dest_comp=1, indices=[BASE, RANGE_BASE]) 670 671def atomic3(name): 672 intrinsic(name + "_deref", src_comp=[-1, 1, 1], dest_comp=1) 673 intrinsic(name, src_comp=[1, 1, 1], dest_comp=1, indices=[BASE, RANGE_BASE]) 674 675atomic("atomic_counter_inc") 676atomic("atomic_counter_pre_dec") 677atomic("atomic_counter_post_dec") 678atomic("atomic_counter_read", flags=[CAN_ELIMINATE]) 679atomic2("atomic_counter_add") 680atomic2("atomic_counter_min") 681atomic2("atomic_counter_max") 682atomic2("atomic_counter_and") 683atomic2("atomic_counter_or") 684atomic2("atomic_counter_xor") 685atomic2("atomic_counter_exchange") 686atomic3("atomic_counter_comp_swap") 687 688# Image load, store and atomic intrinsics. 689# 690# All image intrinsics come in three versions. One which take an image target 691# passed as a deref chain as the first source, one which takes an index as the 692# first source, and one which takes a bindless handle as the first source. 693# In the first version, the image variable contains the memory and layout 694# qualifiers that influence the semantics of the intrinsic. In the second and 695# third, the image format and access qualifiers are provided as constant 696# indices. Up through GLSL ES 3.10, the image index source may only be a 697# constant array access. GLSL ES 3.20 and GLSL 4.00 allow dynamically uniform 698# indexing. 699# 700# All image intrinsics take a four-coordinate vector and a sample index as 701# 2nd and 3rd sources, determining the location within the image that will be 702# accessed by the intrinsic. Components not applicable to the image target 703# in use are undefined. Image store takes an additional four-component 704# argument with the value to be written, and image atomic operations take 705# either one or two additional scalar arguments with the same meaning as in 706# the ARB_shader_image_load_store specification. 707# 708# The last source of many image intrinsics is the LOD. This source is zero 709# unless e.g. SPV_AMD_shader_image_load_store_lod is supported. 710def image(name, src_comp=[], extra_indices=[], **kwargs): 711 intrinsic("image_deref_" + name, src_comp=[-1] + src_comp, 712 indices=[IMAGE_DIM, IMAGE_ARRAY, FORMAT, ACCESS] + extra_indices, **kwargs) 713 intrinsic("image_" + name, src_comp=[1] + src_comp, 714 indices=[IMAGE_DIM, IMAGE_ARRAY, FORMAT, ACCESS, RANGE_BASE] + extra_indices, **kwargs) 715 intrinsic("bindless_image_" + name, src_comp=[-1] + src_comp, 716 indices=[IMAGE_DIM, IMAGE_ARRAY, FORMAT, ACCESS] + extra_indices, **kwargs) 717 718image("load", src_comp=[4, 1, 1], extra_indices=[DEST_TYPE], dest_comp=0, flags=[CAN_ELIMINATE]) 719image("sparse_load", src_comp=[4, 1, 1], extra_indices=[DEST_TYPE], dest_comp=0, flags=[CAN_ELIMINATE]) 720image("store", src_comp=[4, 1, 0, 1], extra_indices=[SRC_TYPE]) 721image("atomic", src_comp=[4, 1, 1], dest_comp=1, extra_indices=[ATOMIC_OP]) 722image("atomic_swap", src_comp=[4, 1, 1, 1], dest_comp=1, extra_indices=[ATOMIC_OP]) 723image("size", dest_comp=0, src_comp=[1], flags=[CAN_ELIMINATE, CAN_REORDER]) 724image("samples", dest_comp=1, flags=[CAN_ELIMINATE, CAN_REORDER]) 725image("texel_address", dest_comp=1, src_comp=[4, 1], 726 flags=[CAN_ELIMINATE, CAN_REORDER]) 727# This returns true if all samples within the pixel have equal color values. 728image("samples_identical", dest_comp=1, src_comp=[4], flags=[CAN_ELIMINATE]) 729# Non-uniform access is not lowered for image_descriptor_amd. 730# dest_comp can be either 4 (buffer) or 8 (image). 731image("descriptor_amd", dest_comp=0, src_comp=[], flags=[CAN_ELIMINATE, CAN_REORDER]) 732# CL-specific format queries 733image("format", dest_comp=1, flags=[CAN_ELIMINATE, CAN_REORDER]) 734image("order", dest_comp=1, flags=[CAN_ELIMINATE, CAN_REORDER]) 735# Multisample fragment mask load 736# src_comp[0] is same as image load src_comp[0] 737image("fragment_mask_load_amd", src_comp=[4], dest_comp=1, bit_sizes=[32], flags=[CAN_ELIMINATE, CAN_REORDER]) 738 739# Vulkan descriptor set intrinsics 740# 741# The Vulkan API uses a different binding model from GL. In the Vulkan 742# API, all external resources are represented by a tuple: 743# 744# (descriptor set, binding, array index) 745# 746# where the array index is the only thing allowed to be indirect. The 747# vulkan_surface_index intrinsic takes the descriptor set and binding as 748# its first two indices and the array index as its source. The third 749# index is a nir_variable_mode in case that's useful to the backend. 750# 751# The intended usage is that the shader will call vulkan_surface_index to 752# get an index and then pass that as the buffer index ubo/ssbo calls. 753# 754# The vulkan_resource_reindex intrinsic takes a resource index in src0 755# (the result of a vulkan_resource_index or vulkan_resource_reindex) which 756# corresponds to the tuple (set, binding, index) and computes an index 757# corresponding to tuple (set, binding, idx + src1). 758intrinsic("vulkan_resource_index", src_comp=[1], dest_comp=0, 759 indices=[DESC_SET, BINDING, DESC_TYPE], 760 flags=[CAN_ELIMINATE, CAN_REORDER]) 761intrinsic("vulkan_resource_reindex", src_comp=[0, 1], dest_comp=0, 762 indices=[DESC_TYPE], flags=[CAN_ELIMINATE, CAN_REORDER]) 763intrinsic("load_vulkan_descriptor", src_comp=[-1], dest_comp=0, 764 indices=[DESC_TYPE], flags=[CAN_ELIMINATE, CAN_REORDER]) 765 766# atomic intrinsics 767# 768# All of these atomic memory operations read a value from memory, compute a new 769# value using one of the operations below, write the new value to memory, and 770# return the original value read. 771# 772# All variable operations take 2 sources except CompSwap that takes 3. These 773# sources represent: 774# 775# 0: A deref to the memory on which to perform the atomic 776# 1: The data parameter to the atomic function (i.e. the value to add 777# in shared_atomic_add, etc). 778# 2: For CompSwap only: the second data parameter. 779# 780# All SSBO operations take 3 sources except CompSwap that takes 4. These 781# sources represent: 782# 783# 0: The SSBO buffer index (dynamically uniform in GLSL, possibly non-uniform 784# with VK_EXT_descriptor_indexing). 785# 1: The offset into the SSBO buffer of the variable that the atomic 786# operation will operate on. 787# 2: The data parameter to the atomic function (i.e. the value to add 788# in ssbo_atomic_add, etc). 789# 3: For CompSwap only: the second data parameter. 790# 791# All shared (and task payload) variable operations take 2 sources 792# except CompSwap that takes 3. 793# These sources represent: 794# 795# 0: The offset into the shared variable storage region that the atomic 796# operation will operate on. 797# 1: The data parameter to the atomic function (i.e. the value to add 798# in shared_atomic_add, etc). 799# 2: For CompSwap only: the second data parameter. 800# 801# All global operations take 2 sources except CompSwap that takes 3. These 802# sources represent: 803# 804# 0: The memory address that the atomic operation will operate on. 805# 1: The data parameter to the atomic function (i.e. the value to add 806# in shared_atomic_add, etc). 807# 2: For CompSwap only: the second data parameter. 808# 809# The 2x32 global variants use a vec2 for the memory address where component X 810# has the low 32-bit and component Y has the high 32-bit. 811# 812# IR3 global operations take 32b vec2 as memory address. IR3 doesn't support 813# float atomics. 814# 815# AGX global variants take a 64-bit base address plus a 32-bit offset in words. 816# The offset is sign-extended or zero-extended based on the SIGN_EXTEND index. 817 818intrinsic("deref_atomic", src_comp=[-1, 1], dest_comp=1, indices=[ACCESS, ATOMIC_OP]) 819intrinsic("ssbo_atomic", src_comp=[-1, 1, 1], dest_comp=1, indices=[ACCESS, ATOMIC_OP]) 820intrinsic("shared_atomic", src_comp=[1, 1], dest_comp=1, indices=[BASE, ATOMIC_OP]) 821intrinsic("task_payload_atomic", src_comp=[1, 1], dest_comp=1, indices=[BASE, ATOMIC_OP]) 822intrinsic("global_atomic", src_comp=[1, 1], dest_comp=1, indices=[ATOMIC_OP]) 823intrinsic("global_atomic_2x32", src_comp=[2, 1], dest_comp=1, indices=[ATOMIC_OP]) 824intrinsic("global_atomic_amd", src_comp=[1, 1, 1], dest_comp=1, indices=[BASE, ATOMIC_OP]) 825intrinsic("global_atomic_ir3", src_comp=[2, 1], dest_comp=1, indices=[BASE, ATOMIC_OP]) 826intrinsic("global_atomic_agx", src_comp=[1, 1, 1], dest_comp=1, indices=[ATOMIC_OP, SIGN_EXTEND]) 827 828intrinsic("deref_atomic_swap", src_comp=[-1, 1, 1], dest_comp=1, indices=[ACCESS, ATOMIC_OP]) 829intrinsic("ssbo_atomic_swap", src_comp=[-1, 1, 1, 1], dest_comp=1, indices=[ACCESS, ATOMIC_OP]) 830intrinsic("shared_atomic_swap", src_comp=[1, 1, 1], dest_comp=1, indices=[BASE, ATOMIC_OP]) 831intrinsic("task_payload_atomic_swap", src_comp=[1, 1, 1], dest_comp=1, indices=[BASE, ATOMIC_OP]) 832intrinsic("global_atomic_swap", src_comp=[1, 1, 1], dest_comp=1, indices=[ATOMIC_OP]) 833intrinsic("global_atomic_swap_2x32", src_comp=[2, 1, 1], dest_comp=1, indices=[ATOMIC_OP]) 834intrinsic("global_atomic_swap_amd", src_comp=[1, 1, 1, 1], dest_comp=1, indices=[BASE, ATOMIC_OP]) 835intrinsic("global_atomic_swap_ir3", src_comp=[2, 1, 1], dest_comp=1, indices=[BASE, ATOMIC_OP]) 836intrinsic("global_atomic_swap_agx", src_comp=[1, 1, 1, 1], dest_comp=1, indices=[ATOMIC_OP, SIGN_EXTEND]) 837 838def system_value(name, dest_comp, indices=[], bit_sizes=[32]): 839 intrinsic("load_" + name, [], dest_comp, indices, 840 flags=[CAN_ELIMINATE, CAN_REORDER], sysval=True, 841 bit_sizes=bit_sizes) 842 843system_value("frag_coord", 4) 844# 16-bit integer vec2 of the pixel X/Y in the framebuffer. 845system_value("pixel_coord", 2, bit_sizes=[16]) 846# Scalar load of frag_coord Z/W components (component=2 for Z, component=3 for 847# W). Backends can lower frag_coord to pixel_coord + frag_coord_zw, in case 848# X/Y is available as an integer but Z/W requires interpolation. 849system_value("frag_coord_zw", 1, indices=[COMPONENT]) 850system_value("point_coord", 2) 851system_value("line_coord", 1) 852system_value("front_face", 1, bit_sizes=[1, 32]) 853system_value("vertex_id", 1) 854system_value("vertex_id_zero_base", 1) 855system_value("first_vertex", 1) 856system_value("is_indexed_draw", 1) 857system_value("base_vertex", 1) 858system_value("instance_id", 1) 859system_value("base_instance", 1) 860system_value("draw_id", 1) 861system_value("sample_id", 1) 862# sample_id_no_per_sample is like sample_id but does not imply per- 863# sample shading. See the lower_helper_invocation option. 864system_value("sample_id_no_per_sample", 1) 865system_value("sample_pos", 2) 866# sample_pos_or_center is like sample_pos but does not imply per-sample 867# shading. When per-sample dispatch is not enabled, it returns (0.5, 0.5). 868system_value("sample_pos_or_center", 2) 869system_value("sample_mask_in", 1) 870system_value("primitive_id", 1) 871system_value("invocation_id", 1) 872system_value("tess_coord", 3) 873# First 2 components of tess_coord only 874system_value("tess_coord_xy", 2) 875system_value("tess_level_outer", 4) 876system_value("tess_level_inner", 2) 877system_value("tess_level_outer_default", 4) 878system_value("tess_level_inner_default", 2) 879system_value("patch_vertices_in", 1) 880system_value("local_invocation_id", 3) 881system_value("local_invocation_index", 1) 882# zero_base indicates it starts from 0 for the current dispatch 883# non-zero_base indicates the base is included 884system_value("workgroup_id", 3) 885system_value("workgroup_id_zero_base", 3) 886# The workgroup_index is intended for situations when a 3 dimensional 887# workgroup_id is not available on the HW, but a 1 dimensional index is. 888system_value("workgroup_index", 1) 889system_value("base_workgroup_id", 3, bit_sizes=[32, 64]) 890system_value("user_clip_plane", 4, indices=[UCP_ID]) 891system_value("num_workgroups", 3) 892system_value("num_vertices", 1) 893system_value("helper_invocation", 1, bit_sizes=[1, 32]) 894system_value("layer_id", 1) 895system_value("view_index", 1) 896system_value("subgroup_size", 1) 897system_value("subgroup_invocation", 1) 898 899# These intrinsics provide a bitmask for all invocations, with one bit per 900# invocation starting with the least significant bit, according to the 901# following table, 902# 903# variable equation for bit values 904# ---------------- -------------------------------- 905# subgroup_eq_mask bit index == subgroup_invocation 906# subgroup_ge_mask bit index >= subgroup_invocation 907# subgroup_gt_mask bit index > subgroup_invocation 908# subgroup_le_mask bit index <= subgroup_invocation 909# subgroup_lt_mask bit index < subgroup_invocation 910# 911# These correspond to gl_SubGroupEqMaskARB, etc. from GL_ARB_shader_ballot, 912# and the above documentation is "borrowed" from that extension spec. 913system_value("subgroup_eq_mask", 0, bit_sizes=[32, 64]) 914system_value("subgroup_ge_mask", 0, bit_sizes=[32, 64]) 915system_value("subgroup_gt_mask", 0, bit_sizes=[32, 64]) 916system_value("subgroup_le_mask", 0, bit_sizes=[32, 64]) 917system_value("subgroup_lt_mask", 0, bit_sizes=[32, 64]) 918 919system_value("num_subgroups", 1) 920system_value("subgroup_id", 1) 921system_value("workgroup_size", 3) 922# note: the definition of global_invocation_id_zero_base is based on 923# (workgroup_id * workgroup_size) + local_invocation_id. 924# it is *not* based on workgroup_id_zero_base, meaning the work group 925# base is already accounted for, and the global base is additive on top of that 926system_value("global_invocation_id", 3, bit_sizes=[32, 64]) 927system_value("global_invocation_id_zero_base", 3, bit_sizes=[32, 64]) 928system_value("base_global_invocation_id", 3, bit_sizes=[32, 64]) 929system_value("global_invocation_index", 1, bit_sizes=[32, 64]) 930system_value("work_dim", 1) 931system_value("line_width", 1) 932system_value("aa_line_width", 1) 933# BASE=0 for global/shader, BASE=1 for local/function 934system_value("scratch_base_ptr", 0, bit_sizes=[32,64], indices=[BASE]) 935system_value("constant_base_ptr", 0, bit_sizes=[32,64]) 936system_value("shared_base_ptr", 0, bit_sizes=[32,64]) 937system_value("global_base_ptr", 0, bit_sizes=[32,64]) 938# Address and size of a transform feedback buffer, indexed by BASE 939system_value("xfb_address", 1, bit_sizes=[32,64], indices=[BASE]) 940system_value("xfb_size", 1, bit_sizes=[32], indices=[BASE]) 941 942# Address of the associated index buffer in a transform feedback program for an 943# indexed draw. This will be used so transform feedback can pull the gl_VertexID 944# from the index buffer. 945system_value("xfb_index_buffer", 1, bit_sizes=[32,64]) 946 947system_value("frag_size", 2) 948system_value("frag_invocation_count", 1) 949# Whether smooth lines or polygon smoothing is enabled 950system_value("poly_line_smooth_enabled", 1, bit_sizes=[1]) 951 952# System values for ray tracing. 953system_value("ray_launch_id", 3) 954system_value("ray_launch_size", 3) 955system_value("ray_world_origin", 3) 956system_value("ray_world_direction", 3) 957system_value("ray_object_origin", 3) 958system_value("ray_object_direction", 3) 959system_value("ray_t_min", 1) 960system_value("ray_t_max", 1) 961system_value("ray_object_to_world", 3, indices=[COLUMN]) 962system_value("ray_world_to_object", 3, indices=[COLUMN]) 963system_value("ray_hit_kind", 1) 964system_value("ray_flags", 1) 965system_value("ray_geometry_index", 1) 966system_value("ray_instance_custom_index", 1) 967system_value("shader_record_ptr", 1, bit_sizes=[64]) 968system_value("cull_mask", 1) 969system_value("ray_triangle_vertex_positions", 3, indices=[COLUMN]) 970 971# Driver-specific viewport scale/offset parameters. 972# 973# VC4 and V3D need to emit a scaled version of the position in the vertex 974# shaders for binning, and having system values lets us move the math for that 975# into NIR. 976# 977# Panfrost needs to implement all coordinate transformation in the 978# vertex shader; system values allow us to share this routine in NIR. 979system_value("viewport_x_scale", 1) 980system_value("viewport_y_scale", 1) 981system_value("viewport_z_scale", 1) 982system_value("viewport_x_offset", 1) 983system_value("viewport_y_offset", 1) 984system_value("viewport_z_offset", 1) 985system_value("viewport_scale", 3) 986system_value("viewport_offset", 3) 987# Pack xy scale and offset into a vec4 load (used by AMD NGG primitive culling) 988system_value("viewport_xy_scale_and_offset", 4) 989 990# Blend constant color values. Float values are clamped. Vectored versions are 991# provided as well for driver convenience 992 993system_value("blend_const_color_r_float", 1) 994system_value("blend_const_color_g_float", 1) 995system_value("blend_const_color_b_float", 1) 996system_value("blend_const_color_a_float", 1) 997system_value("blend_const_color_rgba", 4) 998system_value("blend_const_color_rgba8888_unorm", 1) 999system_value("blend_const_color_aaaa8888_unorm", 1) 1000 1001# System values for gl_Color, for radeonsi which interpolates these in the 1002# shader prolog to handle two-sided color without recompiles and therefore 1003# doesn't handle these in the main shader part like normal varyings. 1004system_value("color0", 4) 1005system_value("color1", 4) 1006 1007# System value for internal compute shaders in radeonsi. 1008system_value("user_data_amd", 4) 1009 1010# In a fragment shader, the current sample mask. At the beginning of the shader, 1011# this is the same as load_sample_mask_in, but as the shader is executed, it may 1012# be affected by writes, discards, etc. 1013# 1014# No frontend generates this, but drivers may use it for internal lowerings. 1015intrinsic("load_sample_mask", [], 1, [], flags=[CAN_ELIMINATE], sysval=True, 1016 bit_sizes=[32]) 1017 1018# Barycentric coordinate intrinsics. 1019# 1020# These set up the barycentric coordinates for a particular interpolation. 1021# The first four are for the simple cases: pixel, centroid, per-sample 1022# (at gl_SampleID), or pull model (1/W, 1/I, 1/J) at the pixel center. The next 1023# two handle interpolating at a specified sample location, or interpolating 1024# with a vec2 offset, 1025# 1026# The interp_mode index should be either the INTERP_MODE_SMOOTH or 1027# INTERP_MODE_NOPERSPECTIVE enum values. 1028# 1029# The vec2 value produced by these intrinsics is intended for use as the 1030# barycoord source of a load_interpolated_input intrinsic. 1031# 1032# The vec3 variants are intended to be used for input barycentric coordinates 1033# which are system values on most hardware, compared to the vec2 variants which 1034# interpolates input varyings. 1035 1036def barycentric(name, dst_comp, src_comp=[]): 1037 intrinsic("load_barycentric_" + name, src_comp=src_comp, dest_comp=dst_comp, 1038 indices=[INTERP_MODE], flags=[CAN_ELIMINATE, CAN_REORDER]) 1039 1040# no sources. 1041barycentric("pixel", 2) 1042barycentric("coord_pixel", 3) 1043barycentric("centroid", 2) 1044barycentric("coord_centroid", 3) 1045barycentric("sample", 2) 1046barycentric("coord_sample", 3) 1047barycentric("model", 3) 1048# src[] = { sample_id }. 1049barycentric("at_sample", 2, [1]) 1050barycentric("coord_at_sample", 3, [1]) 1051# src[] = { offset.xy }. 1052barycentric("at_offset", 2, [2]) 1053barycentric("at_offset_nv", 2, [1]) 1054barycentric("coord_at_offset", 3, [2]) 1055 1056# Load sample position: 1057# 1058# Takes a sample # and returns a sample position. Used for lowering 1059# interpolateAtSample() to interpolateAtOffset() 1060intrinsic("load_sample_pos_from_id", src_comp=[1], dest_comp=2, 1061 flags=[CAN_ELIMINATE, CAN_REORDER]) 1062 1063intrinsic("load_persp_center_rhw_ir3", dest_comp=1, 1064 flags=[CAN_ELIMINATE, CAN_REORDER]) 1065 1066# Load texture scaling values: 1067# 1068# Takes a sampler # and returns 1/size values for multiplying to normalize 1069# texture coordinates. Used for lowering rect textures. 1070intrinsic("load_texture_scale", src_comp=[1], dest_comp=2, 1071 flags=[CAN_ELIMINATE, CAN_REORDER]) 1072 1073# Fragment shader input interpolation delta intrinsic. 1074# 1075# For hw where fragment shader input interpolation is handled in shader, the 1076# load_fs_input_interp deltas intrinsics can be used to load the input deltas 1077# used for interpolation as follows: 1078# 1079# vec3 iid = load_fs_input_interp_deltas(varying_slot) 1080# vec2 bary = load_barycentric_*(...) 1081# float result = iid.x + iid.y * bary.y + iid.z * bary.x 1082 1083intrinsic("load_fs_input_interp_deltas", src_comp=[1], dest_comp=3, 1084 indices=[BASE, COMPONENT, IO_SEMANTICS], flags=[CAN_ELIMINATE, CAN_REORDER]) 1085 1086# Load operations pull data from some piece of GPU memory. All load 1087# operations operate in terms of offsets into some piece of theoretical 1088# memory. Loads from externally visible memory (UBO and SSBO) simply take a 1089# byte offset as a source. Loads from opaque memory (uniforms, inputs, etc.) 1090# take a base+offset pair where the nir_intrinsic_base() gives the location 1091# of the start of the variable being loaded and and the offset source is a 1092# offset into that variable. 1093# 1094# Uniform load operations have a nir_intrinsic_range() index that specifies the 1095# range (starting at base) of the data from which we are loading. If 1096# range == 0, then the range is unknown. 1097# 1098# UBO load operations have a nir_intrinsic_range_base() and 1099# nir_intrinsic_range() that specify the byte range [range_base, 1100# range_base+range] of the UBO that the src offset access must lie within. 1101# 1102# Some load operations such as UBO/SSBO load and per_vertex loads take an 1103# additional source to specify which UBO/SSBO/vertex to load from. 1104# 1105# The exact address type depends on the lowering pass that generates the 1106# load/store intrinsics. Typically, this is vec4 units for things such as 1107# varying slots and float units for fragment shader inputs. UBO and SSBO 1108# offsets are always in bytes. 1109 1110def load(name, src_comp, indices=[], flags=[]): 1111 intrinsic("load_" + name, src_comp, dest_comp=0, indices=indices, 1112 flags=flags) 1113 1114# src[] = { offset }. 1115load("uniform", [1], [BASE, RANGE, DEST_TYPE], [CAN_ELIMINATE, CAN_REORDER]) 1116# src[] = { buffer_index, offset }. 1117load("ubo", [-1, 1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET, RANGE_BASE, RANGE], flags=[CAN_ELIMINATE, CAN_REORDER]) 1118# src[] = { buffer_index, offset in vec4 units }. base is also in vec4 units. 1119load("ubo_vec4", [-1, 1], [ACCESS, BASE, COMPONENT], flags=[CAN_ELIMINATE, CAN_REORDER]) 1120# src[] = { offset }. 1121load("input", [1], [BASE, RANGE, COMPONENT, DEST_TYPE, IO_SEMANTICS], [CAN_ELIMINATE, CAN_REORDER]) 1122# src[] = { vertex_id, offset }. 1123load("input_vertex", [1, 1], [BASE, COMPONENT, DEST_TYPE, IO_SEMANTICS], [CAN_ELIMINATE, CAN_REORDER]) 1124# src[] = { vertex, offset }. 1125load("per_vertex_input", [1, 1], [BASE, RANGE, COMPONENT, DEST_TYPE, IO_SEMANTICS], [CAN_ELIMINATE, CAN_REORDER]) 1126# src[] = { barycoord, offset }. 1127load("interpolated_input", [2, 1], [BASE, COMPONENT, DEST_TYPE, IO_SEMANTICS], [CAN_ELIMINATE, CAN_REORDER]) 1128 1129# src[] = { buffer_index, offset }. 1130load("ssbo", [-1, 1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 1131# src[] = { buffer_index } 1132load("ssbo_address", [1], [], [CAN_ELIMINATE, CAN_REORDER]) 1133# src[] = { offset }. 1134load("output", [1], [BASE, RANGE, COMPONENT, DEST_TYPE, IO_SEMANTICS], flags=[CAN_ELIMINATE]) 1135# src[] = { vertex, offset }. 1136load("per_vertex_output", [1, 1], [BASE, RANGE, COMPONENT, DEST_TYPE, IO_SEMANTICS], [CAN_ELIMINATE]) 1137# src[] = { primitive, offset }. 1138load("per_primitive_output", [1, 1], [BASE, COMPONENT, DEST_TYPE, IO_SEMANTICS], [CAN_ELIMINATE]) 1139# src[] = { offset }. 1140load("shared", [1], [BASE, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 1141# src[] = { offset }. 1142load("task_payload", [1], [BASE, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 1143# src[] = { offset }. 1144load("push_constant", [1], [BASE, RANGE, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE, CAN_REORDER]) 1145# src[] = { offset }. 1146load("constant", [1], [BASE, RANGE, ALIGN_MUL, ALIGN_OFFSET], 1147 [CAN_ELIMINATE, CAN_REORDER]) 1148# src[] = { address }. 1149load("global", [1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 1150# src[] = { address }. 1151load("global_2x32", [2], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 1152# src[] = { address }. 1153load("global_constant", [1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], 1154 [CAN_ELIMINATE, CAN_REORDER]) 1155# src[] = { base_address, offset }. 1156load("global_constant_offset", [1, 1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], 1157 [CAN_ELIMINATE, CAN_REORDER]) 1158# src[] = { base_address, offset, bound }. 1159load("global_constant_bounded", [1, 1, 1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], 1160 [CAN_ELIMINATE, CAN_REORDER]) 1161# src[] = { address }. 1162load("kernel_input", [1], [BASE, RANGE, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE, CAN_REORDER]) 1163# src[] = { offset }. 1164load("scratch", [1], [ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 1165 1166# Stores work the same way as loads, except now the first source is the value 1167# to store and the second (and possibly third) source specify where to store 1168# the value. SSBO and shared memory stores also have a 1169# nir_intrinsic_write_mask() 1170 1171def store(name, srcs, indices=[], flags=[]): 1172 intrinsic("store_" + name, [0] + srcs, indices=indices, flags=flags) 1173 1174# src[] = { value, offset }. 1175store("output", [1], [BASE, RANGE, WRITE_MASK, COMPONENT, SRC_TYPE, IO_SEMANTICS, IO_XFB, IO_XFB2]) 1176# src[] = { value, vertex, offset }. 1177store("per_vertex_output", [1, 1], [BASE, RANGE, WRITE_MASK, COMPONENT, SRC_TYPE, IO_SEMANTICS]) 1178# src[] = { value, primitive, offset }. 1179store("per_primitive_output", [1, 1], [BASE, RANGE, WRITE_MASK, COMPONENT, SRC_TYPE, IO_SEMANTICS]) 1180# src[] = { value, block_index, offset } 1181store("ssbo", [-1, 1], [WRITE_MASK, ACCESS, ALIGN_MUL, ALIGN_OFFSET]) 1182# src[] = { value, offset }. 1183store("shared", [1], [BASE, WRITE_MASK, ALIGN_MUL, ALIGN_OFFSET]) 1184# src[] = { value, offset }. 1185store("task_payload", [1], [BASE, WRITE_MASK, ALIGN_MUL, ALIGN_OFFSET]) 1186# src[] = { value, address }. 1187store("global", [1], [WRITE_MASK, ACCESS, ALIGN_MUL, ALIGN_OFFSET]) 1188# src[] = { value, address }. 1189store("global_2x32", [2], [WRITE_MASK, ACCESS, ALIGN_MUL, ALIGN_OFFSET]) 1190# src[] = { value, offset }. 1191store("scratch", [1], [ALIGN_MUL, ALIGN_OFFSET, WRITE_MASK]) 1192 1193# Intrinsic to load/store from the call stack. 1194# BASE is the offset relative to the current position of the stack 1195# src[] = { }. 1196intrinsic("load_stack", [], dest_comp=0, 1197 indices=[BASE, ALIGN_MUL, ALIGN_OFFSET, CALL_IDX, VALUE_ID], 1198 flags=[CAN_ELIMINATE]) 1199# src[] = { value }. 1200intrinsic("store_stack", [0], 1201 indices=[BASE, ALIGN_MUL, ALIGN_OFFSET, WRITE_MASK, CALL_IDX, VALUE_ID]) 1202 1203 1204# A bit field to implement SPIRV FragmentShadingRateKHR 1205# bit | name | description 1206# 0 | Vertical2Pixels | Fragment invocation covers 2 pixels vertically 1207# 1 | Vertical4Pixels | Fragment invocation covers 4 pixels vertically 1208# 2 | Horizontal2Pixels | Fragment invocation covers 2 pixels horizontally 1209# 3 | Horizontal4Pixels | Fragment invocation covers 4 pixels horizontally 1210intrinsic("load_frag_shading_rate", dest_comp=1, bit_sizes=[32], 1211 flags=[CAN_ELIMINATE, CAN_REORDER]) 1212 1213# Whether the rasterized fragment is fully covered by the generating primitive. 1214system_value("fully_covered", dest_comp=1, bit_sizes=[1]) 1215 1216# OpenCL printf instruction 1217# First source is an index to the format string (u_printf_info element of the shader) 1218# Second source is a deref to a struct containing the args 1219# Dest is success or failure 1220intrinsic("printf", src_comp=[1, 1], dest_comp=1, bit_sizes=[32]) 1221# Since most drivers will want to lower to just dumping args 1222# in a buffer, nir_lower_printf will do that, but requires 1223# the driver to at least provide a base location 1224system_value("printf_buffer_address", 1, bit_sizes=[32,64]) 1225 1226# Mesh shading MultiView intrinsics 1227system_value("mesh_view_count", 1) 1228load("mesh_view_indices", [1], [BASE, RANGE], [CAN_ELIMINATE, CAN_REORDER]) 1229 1230# Used to pass values from the preamble to the main shader. 1231# This should use something similar to Vulkan push constants and load_preamble 1232# should be relatively cheap. 1233# For now we only support accesses with a constant offset. 1234load("preamble", [], indices=[BASE], flags=[CAN_ELIMINATE, CAN_REORDER]) 1235store("preamble", [], indices=[BASE]) 1236 1237# A 64-bit bitfield indexed by I/O location storing 1 in bits corresponding to 1238# varyings that have the flat interpolation specifier in the fragment shader and 1239# 0 otherwise 1240system_value("flat_mask", 1, bit_sizes=[64]) 1241 1242# Whether provoking vertex mode is last 1243system_value("provoking_last", 1) 1244 1245# SPV_KHR_cooperative_matrix. 1246# 1247# Cooperative matrices are referred through derefs to variables, 1248# the destination of the operations appears as the first source, 1249# ordering follows SPIR-V operation. 1250# 1251# Load/Store include an extra source for stride, since that 1252# can be a _dynamically_ uniform value. 1253# 1254# Length takes a type not a value, that's encoded as a MATRIX_DESC. 1255intrinsic("cmat_construct", src_comp=[-1, 1]) 1256intrinsic("cmat_load", src_comp=[-1, -1, 1], indices=[MATRIX_LAYOUT]) 1257intrinsic("cmat_store", src_comp=[-1, -1, 1], indices=[MATRIX_LAYOUT]) 1258intrinsic("cmat_length", src_comp=[], dest_comp=1, indices=[CMAT_DESC], bit_sizes=[32]) 1259intrinsic("cmat_muladd", src_comp=[-1, -1, -1, -1], indices=[SATURATE, CMAT_SIGNED_MASK]) 1260intrinsic("cmat_unary_op", src_comp=[-1, -1], indices=[ALU_OP]) 1261intrinsic("cmat_binary_op", src_comp=[-1, -1, -1], indices=[ALU_OP]) 1262intrinsic("cmat_scalar_op", src_comp=[-1, -1, -1], indices=[ALU_OP]) 1263intrinsic("cmat_bitcast", src_comp=[-1, -1]) 1264intrinsic("cmat_extract", src_comp=[-1, 1], dest_comp=1) 1265intrinsic("cmat_insert", src_comp=[-1, 1, -1, 1]) 1266intrinsic("cmat_copy", src_comp=[-1, -1]) 1267 1268# IR3-specific version of most SSBO intrinsics. The only different 1269# compare to the originals is that they add an extra source to hold 1270# the dword-offset, which is needed by the backend code apart from 1271# the byte-offset already provided by NIR in one of the sources. 1272# 1273# NIR lowering pass 'ir3_nir_lower_io_offset' will replace the 1274# original SSBO intrinsics by these, placing the computed 1275# dword-offset always in the last source. 1276# 1277# The float versions are not handled because those are not supported 1278# by the backend. 1279store("ssbo_ir3", [1, 1, 1], 1280 indices=[WRITE_MASK, ACCESS, ALIGN_MUL, ALIGN_OFFSET]) 1281load("ssbo_ir3", [1, 1, 1], 1282 indices=[ACCESS, ALIGN_MUL, ALIGN_OFFSET], flags=[CAN_ELIMINATE]) 1283intrinsic("ssbo_atomic_ir3", src_comp=[1, 1, 1, 1], dest_comp=1, 1284 indices=[ACCESS, ATOMIC_OP]) 1285intrinsic("ssbo_atomic_swap_ir3", src_comp=[1, 1, 1, 1, 1], dest_comp=1, 1286 indices=[ACCESS, ATOMIC_OP]) 1287 1288# System values for freedreno geometry shaders. 1289system_value("vs_primitive_stride_ir3", 1) 1290system_value("vs_vertex_stride_ir3", 1) 1291system_value("gs_header_ir3", 1) 1292system_value("primitive_location_ir3", 1, indices=[DRIVER_LOCATION]) 1293 1294# System values for freedreno tessellation shaders. 1295system_value("hs_patch_stride_ir3", 1) 1296system_value("tess_factor_base_ir3", 2) 1297system_value("tess_param_base_ir3", 2) 1298system_value("tcs_header_ir3", 1) 1299system_value("rel_patch_id_ir3", 1) 1300 1301# System values for freedreno compute shaders. 1302system_value("subgroup_id_shift_ir3", 1) 1303 1304# System values for freedreno fragment shaders. 1305intrinsic("load_frag_coord_unscaled_ir3", dest_comp=4, 1306 flags=[CAN_ELIMINATE, CAN_REORDER], bit_sizes=[32]) 1307 1308# IR3-specific intrinsics for tessellation control shaders. cond_end_ir3 end 1309# the shader when src0 is false and is used to narrow down the TCS shader to 1310# just thread 0 before writing out tessellation levels. 1311intrinsic("cond_end_ir3", src_comp=[1]) 1312# end_patch_ir3 is used just before thread 0 exist the TCS and presumably 1313# signals the TE that the patch is complete and can be tessellated. 1314intrinsic("end_patch_ir3") 1315 1316# Per-view gl_FragSizeEXT and gl_FragCoord offset. 1317intrinsic("load_frag_size_ir3", src_comp=[1], dest_comp=2, indices=[RANGE], 1318 flags=[CAN_ELIMINATE, CAN_REORDER], bit_sizes=[32]) 1319intrinsic("load_frag_offset_ir3", src_comp=[1], dest_comp=2, indices=[RANGE], 1320 flags=[CAN_ELIMINATE, CAN_REORDER], bit_sizes=[32]) 1321 1322# IR3-specific load/store intrinsics. These access a buffer used to pass data 1323# between geometry stages - perhaps it's explicit access to the vertex cache. 1324 1325# src[] = { value, offset }. 1326store("shared_ir3", [1], [BASE, ALIGN_MUL, ALIGN_OFFSET]) 1327# src[] = { offset }. 1328load("shared_ir3", [1], [BASE, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 1329 1330# IR3-specific load/store global intrinsics. They take a 64-bit base address 1331# and a 32-bit offset. The hardware will add the base and the offset, which 1332# saves us from doing 64-bit math on the base address. 1333 1334# src[] = { value, address(vec2 of hi+lo uint32_t), offset }. 1335# const_index[] = { write_mask, align_mul, align_offset } 1336store("global_ir3", [2, 1], indices=[ACCESS, ALIGN_MUL, ALIGN_OFFSET]) 1337# src[] = { address(vec2 of hi+lo uint32_t), offset }. 1338# const_index[] = { access, align_mul, align_offset } 1339# the alignment applies to the base address 1340load("global_ir3", [2, 1], indices=[ACCESS, ALIGN_MUL, ALIGN_OFFSET, RANGE_BASE, RANGE], flags=[CAN_ELIMINATE]) 1341 1342# IR3-specific bindless handle specifier. Similar to vulkan_resource_index, but 1343# without the binding because the hardware expects a single flattened index 1344# rather than a (binding, index) pair. We may also want to use this with GL. 1345# Note that this doesn't actually turn into a HW instruction. 1346intrinsic("bindless_resource_ir3", [1], dest_comp=1, indices=[DESC_SET], flags=[CAN_ELIMINATE, CAN_REORDER]) 1347 1348# IR3-specific intrinsics for shader preamble. These are meant to be used like 1349# this: 1350# 1351# if (preamble_start()) { 1352# if (subgroupElect()) { 1353# // preamble 1354# ... 1355# preamble_end(); 1356# } 1357# } 1358# // main shader 1359# ... 1360 1361intrinsic("preamble_start_ir3", [], dest_comp=1, flags=[CAN_ELIMINATE, CAN_REORDER]) 1362 1363barrier("preamble_end_ir3") 1364 1365# IR3-specific intrinsic for stc. Should be used in the shader preamble. 1366store("uniform_ir3", [], indices=[BASE]) 1367 1368# IR3-specific intrinsic for ldc.k. Copies UBO to constant file. 1369# base is the const file base in components, range is the amount to copy in 1370# vec4's. 1371intrinsic("copy_ubo_to_uniform_ir3", [1, 1], indices=[BASE, RANGE]) 1372 1373# IR3-specific intrinsic for ldg.k. 1374# base is an offset to apply to the address in bytes, range_base is the 1375# const file base in components, range is the amount to copy in vec4's. 1376intrinsic("copy_global_to_uniform_ir3", [2], indices=[BASE, RANGE_BASE, RANGE]) 1377 1378# IR3-specific intrinsic for stsc. Loads from push consts to constant file 1379# Should be used in the shader preamble. 1380intrinsic("copy_push_const_to_uniform_ir3", [1], indices=[BASE, RANGE]) 1381 1382intrinsic("brcst_active_ir3", dest_comp=1, src_comp=[1, 1], bit_sizes=src0, 1383 indices=[CLUSTER_SIZE]) 1384intrinsic("reduce_clusters_ir3", dest_comp=1, src_comp=[1], bit_sizes=src0, 1385 indices=[REDUCTION_OP]) 1386intrinsic("inclusive_scan_clusters_ir3", dest_comp=1, src_comp=[1], 1387 bit_sizes=src0, indices=[REDUCTION_OP]) 1388intrinsic("exclusive_scan_clusters_ir3", dest_comp=1, src_comp=[1, 1], 1389 bit_sizes=src0, indices=[REDUCTION_OP]) 1390 1391# Intrinsics used by the Midgard/Bifrost blend pipeline. These are defined 1392# within a blend shader to read/write the raw value from the tile buffer, 1393# without applying any format conversion in the process. If the shader needs 1394# usable pixel values, it must apply format conversions itself. 1395# 1396# These definitions are generic, but they are explicitly vendored to prevent 1397# other drivers from using them, as their semantics is defined in terms of the 1398# Midgard/Bifrost hardware tile buffer and may not line up with anything sane. 1399# One notable divergence is sRGB, which is asymmetric: raw_input_pan requires 1400# an sRGB->linear conversion, but linear values should be written to 1401# raw_output_pan and the hardware handles linear->sRGB. 1402# 1403# store_raw_output_pan is used only for blend shaders, and writes out only a 1404# single 128-bit chunk. To support multisampling, the BASE index specifies the 1405# bas sample index written out. 1406 1407# src[] = { value } 1408store("raw_output_pan", [], [IO_SEMANTICS, BASE]) 1409store("combined_output_pan", [1, 1, 1, 4], [IO_SEMANTICS, COMPONENT, SRC_TYPE, DEST_TYPE]) 1410load("raw_output_pan", [1], [IO_SEMANTICS], [CAN_ELIMINATE, CAN_REORDER]) 1411 1412# Loads the sampler paramaters <min_lod, max_lod, lod_bias> 1413# src[] = { sampler_index } 1414load("sampler_lod_parameters_pan", [1], flags=[CAN_ELIMINATE, CAN_REORDER]) 1415 1416# Like load_output but using a specified render target conversion descriptor 1417load("converted_output_pan", [1], indices=[DEST_TYPE, IO_SEMANTICS], flags=[CAN_ELIMINATE]) 1418 1419# Load the render target conversion descriptor for a given render target given 1420# in the BASE index. Converts to a type with size given by the source type. 1421# Valid in fragment and blend stages. 1422system_value("rt_conversion_pan", 1, indices=[BASE, SRC_TYPE], bit_sizes=[32]) 1423 1424# Loads the sample position array on Bifrost, in a packed Arm-specific format 1425system_value("sample_positions_pan", 1, bit_sizes=[64]) 1426 1427# In a fragment shader, is the framebuffer single-sampled? 0/~0 bool 1428system_value("multisampled_pan", 1, bit_sizes=[32]) 1429 1430# R600 specific instrincs 1431# 1432# location where the tesselation data is stored in LDS 1433system_value("tcs_in_param_base_r600", 4) 1434system_value("tcs_out_param_base_r600", 4) 1435system_value("tcs_rel_patch_id_r600", 1) 1436system_value("tcs_tess_factor_base_r600", 1) 1437 1438# load as many components as needed giving per-component addresses 1439intrinsic("load_local_shared_r600", src_comp=[0], dest_comp=0, indices = [], flags = [CAN_ELIMINATE]) 1440 1441store("local_shared_r600", [1], [WRITE_MASK]) 1442store("tf_r600", []) 1443 1444# AMD GCN/RDNA specific intrinsics 1445 1446# This barrier is a hint that prevents moving the instruction that computes 1447# src after this barrier. It's a constraint for the instruction scheduler. 1448# Otherwise it's identical to a move instruction. 1449# On AMD, it also forces the src value to be stored in a VGPR. 1450intrinsic("optimization_barrier_vgpr_amd", dest_comp=0, src_comp=[0], 1451 flags=[CAN_ELIMINATE]) 1452 1453# Untyped buffer load/store instructions of arbitrary length. 1454# src[] = { descriptor, vector byte offset, scalar byte offset, index offset } 1455# The index offset is multiplied by the stride in the descriptor. 1456# The vector/scalar offsets are in bytes, BASE is a constant byte offset. 1457intrinsic("load_buffer_amd", src_comp=[4, 1, 1, 1], dest_comp=0, indices=[BASE, MEMORY_MODES, ACCESS], flags=[CAN_ELIMINATE]) 1458# src[] = { store value, descriptor, vector byte offset, scalar byte offset, index offset } 1459intrinsic("store_buffer_amd", src_comp=[0, 4, 1, 1, 1], indices=[BASE, WRITE_MASK, MEMORY_MODES, ACCESS]) 1460 1461# Typed buffer load of arbitrary length, using a specified format. 1462# src[] = { descriptor, vector byte offset, scalar byte offset, index offset } 1463# 1464# The compiler backend is responsible for emitting correct HW instructions according to alignment, range etc. 1465# Users of this intrinsic must ensure that the first component being loaded is really the first component 1466# of the specified format, because range analysis assumes this. 1467# The size of the specified format also determines the memory range that this instruction is allowed to access. 1468# 1469# The index offset is multiplied by the stride in the descriptor, if any. 1470# The vector/scalar offsets are in bytes, BASE is a constant byte offset. 1471intrinsic("load_typed_buffer_amd", src_comp=[4, 1, 1, 1], dest_comp=0, indices=[BASE, MEMORY_MODES, ACCESS, FORMAT, ALIGN_MUL, ALIGN_OFFSET], flags=[CAN_ELIMINATE]) 1472 1473# src[] = { address, unsigned 32-bit offset }. 1474load("global_amd", [1, 1], indices=[BASE, ACCESS, ALIGN_MUL, ALIGN_OFFSET], flags=[CAN_ELIMINATE]) 1475# src[] = { value, address, unsigned 32-bit offset }. 1476store("global_amd", [1, 1], indices=[BASE, ACCESS, ALIGN_MUL, ALIGN_OFFSET, WRITE_MASK]) 1477 1478# Same as shared_atomic_add, but with GDS. src[] = {store_val, gds_addr, m0} 1479intrinsic("gds_atomic_add_amd", src_comp=[1, 1, 1], dest_comp=1, indices=[BASE]) 1480 1481# src[] = { sample_id, num_samples } 1482intrinsic("load_sample_positions_amd", src_comp=[1, 1], dest_comp=2, flags=[CAN_ELIMINATE, CAN_REORDER]) 1483 1484# Descriptor where TCS outputs are stored for TES 1485system_value("ring_tess_offchip_amd", 4) 1486system_value("ring_tess_offchip_offset_amd", 1) 1487# Descriptor where TCS outputs are stored for the HW tessellator 1488system_value("ring_tess_factors_amd", 4) 1489system_value("ring_tess_factors_offset_amd", 1) 1490# Descriptor where ES outputs are stored for GS to read on GFX6-8 1491system_value("ring_esgs_amd", 4) 1492system_value("ring_es2gs_offset_amd", 1) 1493# Address of the task shader draw ring (used for VARYING_SLOT_TASK_COUNT) 1494system_value("ring_task_draw_amd", 4) 1495# Address of the task shader payload ring (used for all other outputs) 1496system_value("ring_task_payload_amd", 4) 1497# Address of the mesh shader scratch ring (used for excess mesh shader outputs) 1498system_value("ring_mesh_scratch_amd", 4) 1499system_value("ring_mesh_scratch_offset_amd", 1) 1500# Pointer into the draw and payload rings 1501system_value("task_ring_entry_amd", 1) 1502# Descriptor where NGG attributes are stored on GFX11. 1503system_value("ring_attr_amd", 4) 1504system_value("ring_attr_offset_amd", 1) 1505 1506# Load provoking vertex info 1507system_value("provoking_vtx_amd", 1) 1508 1509# Load rasterization primitive 1510system_value("rasterization_primitive_amd", 1); 1511 1512# Number of patches processed by each TCS workgroup 1513system_value("tcs_num_patches_amd", 1) 1514# Relative tessellation patch ID within the current workgroup 1515system_value("tess_rel_patch_id_amd", 1) 1516# Vertex offsets used for GS per-vertex inputs 1517system_value("gs_vertex_offset_amd", 1, [BASE]) 1518# Number of rasterization samples 1519system_value("rasterization_samples_amd", 1) 1520 1521# Descriptor where GS outputs are stored for GS copy shader to read on GFX6-9 1522system_value("ring_gsvs_amd", 4, indices=[STREAM_ID]) 1523# Write offset in gsvs ring for legacy GS shader 1524system_value("ring_gs2vs_offset_amd", 1) 1525 1526# Streamout configuration 1527system_value("streamout_config_amd", 1) 1528# Position to write within the streamout buffers 1529system_value("streamout_write_index_amd", 1) 1530# Offset to write within a streamout buffer 1531system_value("streamout_offset_amd", 1, indices=[BASE]) 1532 1533# AMD merged shader intrinsics 1534 1535# Whether the current invocation index in the subgroup is less than the source. The source must be 1536# subgroup uniform and bits 0-7 must be less than or equal to the wave size. 1537intrinsic("is_subgroup_invocation_lt_amd", src_comp=[1], dest_comp=1, bit_sizes=[1], flags=[CAN_ELIMINATE]) 1538 1539# AMD NGG intrinsics 1540 1541# Number of initial input vertices in the current workgroup. 1542system_value("workgroup_num_input_vertices_amd", 1) 1543# Number of initial input primitives in the current workgroup. 1544system_value("workgroup_num_input_primitives_amd", 1) 1545# For NGG passthrough mode only. Pre-packed argument for export_primitive_amd. 1546system_value("packed_passthrough_primitive_amd", 1) 1547# Whether NGG should execute shader query for pipeline statistics. 1548system_value("pipeline_stat_query_enabled_amd", dest_comp=1, bit_sizes=[1]) 1549# Whether NGG should execute shader query for primitive generated. 1550system_value("prim_gen_query_enabled_amd", dest_comp=1, bit_sizes=[1]) 1551# Whether NGG should execute shader query for primitive streamouted. 1552system_value("prim_xfb_query_enabled_amd", dest_comp=1, bit_sizes=[1]) 1553# Merged wave info. Bits 0-7 are the ES thread count, 8-15 are the GS thread count, 16-24 is the 1554# GS Wave ID, 24-27 is the wave index in the workgroup, and 28-31 is the workgroup size in waves. 1555system_value("merged_wave_info_amd", dest_comp=1) 1556# Global ID for GS waves on GCN/RDNA legacy GS. 1557system_value("gs_wave_id_amd", dest_comp=1) 1558# Whether the shader should clamp vertex color outputs to [0, 1]. 1559system_value("clamp_vertex_color_amd", dest_comp=1, bit_sizes=[1]) 1560# Whether the shader should cull front facing triangles. 1561intrinsic("load_cull_front_face_enabled_amd", dest_comp=1, bit_sizes=[1], flags=[CAN_ELIMINATE]) 1562# Whether the shader should cull back facing triangles. 1563intrinsic("load_cull_back_face_enabled_amd", dest_comp=1, bit_sizes=[1], flags=[CAN_ELIMINATE]) 1564# True if face culling should use CCW (false if CW). 1565intrinsic("load_cull_ccw_amd", dest_comp=1, bit_sizes=[1], flags=[CAN_ELIMINATE]) 1566# Whether the shader should cull small primitives that are not visible in a pixel. 1567intrinsic("load_cull_small_primitives_enabled_amd", dest_comp=1, bit_sizes=[1], flags=[CAN_ELIMINATE]) 1568# Whether any culling setting is enabled in the shader. 1569intrinsic("load_cull_any_enabled_amd", dest_comp=1, bit_sizes=[1], flags=[CAN_ELIMINATE]) 1570# Small primitive culling precision 1571intrinsic("load_cull_small_prim_precision_amd", dest_comp=1, bit_sizes=[32], flags=[CAN_ELIMINATE, CAN_REORDER]) 1572# Initial edge flags in a Vertex Shader, packed into the format the HW needs for primitive export. 1573intrinsic("load_initial_edgeflags_amd", src_comp=[], dest_comp=1, bit_sizes=[32], indices=[]) 1574# Corresponds to s_sendmsg in the GCN/RDNA ISA, src[] = { m0_content }, BASE = imm 1575intrinsic("sendmsg_amd", src_comp=[1], indices=[BASE]) 1576# Overwrites VS input registers, for use with vertex compaction after culling. src = {vertex_id, instance_id}. 1577intrinsic("overwrite_vs_arguments_amd", src_comp=[1, 1], indices=[]) 1578# Overwrites TES input registers, for use with vertex compaction after culling. src = {tes_u, tes_v, rel_patch_id, patch_id}. 1579intrinsic("overwrite_tes_arguments_amd", src_comp=[1, 1, 1, 1], indices=[]) 1580 1581# The address of the sbt descriptors. 1582system_value("sbt_base_amd", 1, bit_sizes=[64]) 1583 1584# 1. HW descriptor 1585# 2. BVH node(64-bit pointer as 2x32 ...) 1586# 3. ray extent 1587# 4. ray origin 1588# 5. ray direction 1589# 6. inverse ray direction (componentwise 1.0/ray direction) 1590intrinsic("bvh64_intersect_ray_amd", [4, 2, 1, 3, 3, 3], 4, flags=[CAN_ELIMINATE, CAN_REORDER]) 1591 1592# Return of a callable in raytracing pipelines 1593intrinsic("rt_return_amd") 1594 1595# offset into scratch for the input callable data in a raytracing pipeline. 1596system_value("rt_arg_scratch_offset_amd", 1) 1597 1598# Whether to call the anyhit shader for an intersection in an intersection shader. 1599system_value("intersection_opaque_amd", 1, bit_sizes=[1]) 1600 1601# pointer to the next resume shader 1602system_value("resume_shader_address_amd", 1, bit_sizes=[64], indices=[CALL_IDX]) 1603 1604# Scratch base of callable stack for ray tracing. 1605system_value("rt_dynamic_callable_stack_base_amd", 1) 1606 1607# Ray Tracing Traversal inputs 1608system_value("sbt_offset_amd", 1) 1609system_value("sbt_stride_amd", 1) 1610system_value("accel_struct_amd", 1, bit_sizes=[64]) 1611system_value("cull_mask_and_flags_amd", 1) 1612 1613# 0. SBT Index 1614# 1. Ray Tmax 1615# 2. Primitive Id 1616# 3. Instance Addr 1617# 4. Geometry Id and Flags 1618# 5. Hit Kind 1619intrinsic("execute_closest_hit_amd", src_comp=[1, 1, 1, 1, 1, 1]) 1620 1621# 0. Ray Tmax 1622intrinsic("execute_miss_amd", src_comp=[1]) 1623 1624# Used for saving and restoring hit attribute variables. 1625# BASE=dword index 1626intrinsic("load_hit_attrib_amd", dest_comp=1, bit_sizes=[32], indices=[BASE]) 1627intrinsic("store_hit_attrib_amd", src_comp=[1], indices=[BASE]) 1628 1629# Load forced VRS rates. 1630intrinsic("load_force_vrs_rates_amd", dest_comp=1, bit_sizes=[32], flags=[CAN_ELIMINATE, CAN_REORDER]) 1631 1632intrinsic("load_scalar_arg_amd", dest_comp=0, bit_sizes=[32], 1633 indices=[BASE, ARG_UPPER_BOUND_U32_AMD], 1634 flags=[CAN_ELIMINATE, CAN_REORDER]) 1635intrinsic("load_vector_arg_amd", dest_comp=0, bit_sizes=[32], 1636 indices=[BASE, ARG_UPPER_BOUND_U32_AMD, FLAGS], 1637 flags=[CAN_ELIMINATE, CAN_REORDER]) 1638store("scalar_arg_amd", [], [BASE]) 1639store("vector_arg_amd", [], [BASE]) 1640 1641# src[] = { 32/64-bit base address, 32-bit offset }. 1642intrinsic("load_smem_amd", src_comp=[1, 1], dest_comp=0, bit_sizes=[32], 1643 indices=[ALIGN_MUL, ALIGN_OFFSET], 1644 flags=[CAN_ELIMINATE, CAN_REORDER]) 1645 1646# src[] = { offset }. 1647intrinsic("load_shared2_amd", [1], dest_comp=2, indices=[OFFSET0, OFFSET1, ST64], flags=[CAN_ELIMINATE]) 1648 1649# src[] = { value, offset }. 1650intrinsic("store_shared2_amd", [2, 1], indices=[OFFSET0, OFFSET1, ST64]) 1651 1652# Vertex stride in LS-HS buffer 1653system_value("lshs_vertex_stride_amd", 1) 1654 1655# Vertex stride in ES-GS buffer 1656system_value("esgs_vertex_stride_amd", 1) 1657 1658# Per patch data offset in HS VRAM output buffer 1659system_value("hs_out_patch_data_offset_amd", 1) 1660 1661# line_width * 0.5 / abs(viewport_scale[2]) 1662system_value("clip_half_line_width_amd", 2) 1663 1664# Number of vertices in a primitive 1665system_value("num_vertices_per_primitive_amd", 1) 1666 1667# Load streamout buffer desc 1668# BASE = buffer index 1669intrinsic("load_streamout_buffer_amd", dest_comp=4, indices=[BASE], bit_sizes=[32], flags=[CAN_ELIMINATE, CAN_REORDER]) 1670 1671# An ID for each workgroup ordered by primitve sequence 1672system_value("ordered_id_amd", 1) 1673 1674# Add src1 to global streamout buffer offsets in the specified order 1675# src[] = { ordered_id, counter } 1676# WRITE_MASK = mask for counter channel to update 1677intrinsic("ordered_xfb_counter_add_amd", dest_comp=0, src_comp=[1, 0], indices=[WRITE_MASK], bit_sizes=[32]) 1678# Subtract from global streamout buffer offsets. Used to fix up the offsets 1679# when we overflow streamout buffers. 1680# src[] = { offsets } 1681# WRITE_MASK = mask of offsets to subtract 1682intrinsic("xfb_counter_sub_amd", src_comp=[0], indices=[WRITE_MASK], bit_sizes=[32]) 1683 1684# Provoking vertex index in a primitive 1685system_value("provoking_vtx_in_prim_amd", 1) 1686 1687# Atomically add current wave's primitive count to query result 1688# * GS emitted primitive is primitive emitted by any GS stream 1689# * generated primitive is primitive that has been produced for that stream by VS/TES/GS 1690# * streamout primitve is primitve that has been written to xfb buffer, may be different 1691# than generated primitive when xfb buffer is too small to hold more primitives 1692# src[] = { primitive_count }. 1693intrinsic("atomic_add_gs_emit_prim_count_amd", [1]) 1694intrinsic("atomic_add_gen_prim_count_amd", [1], indices=[STREAM_ID]) 1695intrinsic("atomic_add_xfb_prim_count_amd", [1], indices=[STREAM_ID]) 1696 1697# Atomically add current shader's invocation count to query result 1698# src[] = { invocation_count }. 1699intrinsic("atomic_add_shader_invocation_count_amd", [1]) 1700 1701# LDS offset for scratch section in NGG shader 1702system_value("lds_ngg_scratch_base_amd", 1) 1703# LDS offset for NGG GS shader vertex emit 1704system_value("lds_ngg_gs_out_vertex_base_amd", 1) 1705 1706# AMD GPU shader output export instruction 1707# src[] = { export_value, row } 1708# BASE = export target 1709# FLAGS = AC_EXP_FLAG_* 1710intrinsic("export_amd", [0], indices=[BASE, WRITE_MASK, FLAGS]) 1711intrinsic("export_row_amd", [0, 1], indices=[BASE, WRITE_MASK, FLAGS]) 1712 1713# Export dual source blend outputs with swizzle operation 1714# src[] = { mrt0, mrt1 } 1715intrinsic("export_dual_src_blend_amd", [0, 0], indices=[WRITE_MASK]) 1716 1717# Alpha test reference value 1718system_value("alpha_reference_amd", 1) 1719 1720# Whether to enable barycentric optimization 1721system_value("barycentric_optimize_amd", dest_comp=1, bit_sizes=[1]) 1722 1723# Copy the input into a register which will remain valid for entire quads, even in control flow. 1724# This should only be used directly for texture sources. 1725intrinsic("strict_wqm_coord_amd", src_comp=[0], dest_comp=0, bit_sizes=[32], indices=[BASE], 1726 flags=[CAN_ELIMINATE]) 1727 1728intrinsic("cmat_muladd_amd", src_comp=[16, 16, 0], dest_comp=0, bit_sizes=src2, 1729 indices=[SATURATE, CMAT_SIGNED_MASK], flags=[CAN_ELIMINATE]) 1730 1731# V3D-specific instrinc for tile buffer color reads. 1732# 1733# The hardware requires that we read the samples and components of a pixel 1734# in order, so we cannot eliminate or remove any loads in a sequence. 1735# 1736# src[] = { render_target } 1737# BASE = sample index 1738load("tlb_color_v3d", [1], [BASE, COMPONENT], []) 1739 1740# V3D-specific instrinc for per-sample tile buffer color writes. 1741# 1742# The driver backend needs to identify per-sample color writes and emit 1743# specific code for them. 1744# 1745# src[] = { value, render_target } 1746# BASE = sample index 1747store("tlb_sample_color_v3d", [1], [BASE, COMPONENT, SRC_TYPE], []) 1748 1749# V3D-specific intrinsic to load the number of layers attached to 1750# the target framebuffer 1751intrinsic("load_fb_layers_v3d", dest_comp=1, flags=[CAN_ELIMINATE, CAN_REORDER]) 1752 1753# Active invocation index within the subgroup. 1754# Equivalent to popcount(ballot(true) & ((1 << subgroup_invocation) - 1)) 1755system_value("active_subgroup_invocation_agx", 1) 1756 1757# With [0, 1] clipping, no transform is needed on the output z' = z. But with [-1, 1758# 1] clipping, we need to transform z' = (z + w) / 2. We express both cases as a 1759# lerp between z and w, where this is the lerp coefficient: 0 for [0, 1] and 0.5 1760# for [-1, 1]. 1761system_value("clip_z_coeff_agx", 1) 1762 1763# mesa_prim for the input topology (in a geometry shader) 1764system_value("input_topology_agx", 1) 1765 1766# Load a bindless sampler handle mapping a binding table sampler. 1767intrinsic("load_sampler_handle_agx", [1], 1, [], 1768 flags=[CAN_ELIMINATE, CAN_REORDER], 1769 bit_sizes=[16]) 1770 1771# Load a bindless texture handle mapping a binding table texture. 1772intrinsic("load_texture_handle_agx", [1], 2, [], 1773 flags=[CAN_ELIMINATE, CAN_REORDER], 1774 bit_sizes=[32]) 1775 1776# Given a vec2 bindless texture handle, load the address of the texture 1777# descriptor described by that vec2. This allows inspecting the descriptor from 1778# the shader. This does not actually load the content of the descriptor, only 1779# the content of the handle (which is the address of the descriptor). 1780intrinsic("load_from_texture_handle_agx", [2], 1, [], 1781 flags=[CAN_ELIMINATE, CAN_REORDER], 1782 bit_sizes=[64]) 1783 1784# Load the coefficient register corresponding to a given fragment shader input. 1785# Coefficient registers are vec3s that are dotted with <x, y, 1> to interpolate 1786# the input, where x and y are relative to the 32x32 supertile. 1787intrinsic("load_coefficients_agx", 1788 bit_sizes = [32], 1789 dest_comp = 3, 1790 indices=[COMPONENT, IO_SEMANTICS, INTERP_MODE], 1791 flags=[CAN_ELIMINATE, CAN_REORDER]) 1792 1793# In a fragment shader, boolean system value that is true if the last vertex 1794# stage writes the layer ID. If false, layer IDs are defined to read back zero. 1795# This system value facilitates that. 16-bit 0/~0 bool allows easy masking. 1796system_value("layer_id_written_agx", 1, bit_sizes=[16]) 1797 1798# Load/store a pixel in local memory. This operation is formatted, with 1799# conversion between the specified format and the implied register format of the 1800# source/destination (for store/loads respectively). This mostly matters for 1801# converting between floating-point registers and normalized memory formats. 1802# 1803# The format is the pipe_format of the local memory (the source), see 1804# agx_internal_formats.h for the supported list. 1805# 1806# Logically, this loads/stores a single sample. The sample to load is 1807# specified by the bitfield sample mask source. However, for stores multiple 1808# bits of the sample mask may be set, which will replicate the value. For 1809# pixel rate shading, use 0xFF as the mask to store to all samples regardless of 1810# the sample count. 1811# 1812# All calculations are relative to an immediate byte offset into local 1813# memory, which acts relative to the start of the sample. These instructions 1814# logically access: 1815# 1816# (((((y * tile_width) + x) * nr_samples) + sample) * sample_stride) + offset 1817# 1818# src[] = { sample mask } 1819# base = offset 1820load("local_pixel_agx", [1], [BASE, FORMAT], [CAN_REORDER, CAN_ELIMINATE]) 1821# src[] = { value, sample mask } 1822# base = offset 1823store("local_pixel_agx", [1], [BASE, WRITE_MASK, FORMAT], [CAN_REORDER]) 1824 1825# Combined depth/stencil emit, applying to a mask of samples. base indicates 1826# which to write (1 = depth, 2 = stencil, 3 = both). 1827# 1828# src[] = { sample mask, depth, stencil } 1829intrinsic("store_zs_agx", [1, 1, 1], indices=[BASE], flags=[]) 1830 1831# Store a block from local memory into a bound image. Used to write out render 1832# targets within the end-of-tile shader, although it is valid in general compute 1833# kernels. 1834# 1835# The format is the pipe_format of the local memory (the source), see 1836# agx_internal_formats.h for the supported list. The image format is 1837# specified in the PBE descriptor. 1838# 1839# The image dimension is used to distinguish multisampled images from 1840# non-multisampled images. It must be 2D or MS. 1841# 1842# src[] = { image index, logical offset within shared memory, layer } 1843intrinsic("block_image_store_agx", [1, 1, 1], bit_sizes=[32, 16, 16], 1844 indices=[FORMAT, IMAGE_DIM, IMAGE_ARRAY], flags=[CAN_REORDER]) 1845 1846# Formatted load/store. The format is the pipe_format in memory (see 1847# agx_internal_formats.h for the supported list). This accesses: 1848# 1849# address + extend(index) << (format shift + shift) 1850# 1851# The nir_intrinsic_base() index encodes the shift. The sign_extend index 1852# determines whether sign- or zero-extension is used for the index. 1853# 1854# All loads and stores on AGX uses these hardware instructions, so while these are 1855# logically load_global_agx/load_global_constant_agx/store_global_agx, the 1856# _global is omitted as it adds nothing. 1857# 1858# src[] = { address, index }. 1859load("agx", [1, 1], [ACCESS, BASE, FORMAT, SIGN_EXTEND], [CAN_ELIMINATE]) 1860load("constant_agx", [1, 1], [ACCESS, BASE, FORMAT, SIGN_EXTEND], 1861 [CAN_ELIMINATE, CAN_REORDER]) 1862# src[] = { value, address, index }. 1863store("agx", [1, 1], [ACCESS, BASE, FORMAT, SIGN_EXTEND]) 1864 1865# Logical complement of load_front_face, mapping to an AGX system value 1866system_value("back_face_agx", 1, bit_sizes=[1, 32]) 1867 1868# Load the base address of an indexed vertex attribute (for lowering). 1869intrinsic("load_vbo_base_agx", src_comp=[1], dest_comp=1, bit_sizes=[64], 1870 flags=[CAN_ELIMINATE, CAN_REORDER]) 1871 1872# When vertex robustness is enabled, loads the maximum valid attribute index for 1873# a given attribute. This is unsigned: the driver ensures that at least one 1874# vertex is always valid to load, directing loads to a zero sink if necessary. 1875intrinsic("load_attrib_clamp_agx", src_comp=[1], dest_comp=1, 1876 bit_sizes=[32], flags=[CAN_ELIMINATE, CAN_REORDER]) 1877 1878# Load a driver-internal system value from a given system value set at a given 1879# binding within the set. This is used for correctness when lowering things like 1880# UBOs with merged shaders. 1881# 1882# The FLAGS are used internally for loading the index of the uniform itself, 1883# rather than the contents, used for lowering bindless handles (which encode 1884# uniform indices as immediates in the NIR for technical reasons). 1885load("sysval_agx", [], [DESC_SET, BINDING, FLAGS], [CAN_REORDER, CAN_ELIMINATE]) 1886 1887# Write out a sample mask for a targeted subset of samples, specified in the two 1888# masks. Maps to the corresponding AGX instruction, the actual workings are 1889# documented elsewhere as they are too complicated for this comment. 1890intrinsic("sample_mask_agx", src_comp=[1, 1]) 1891 1892# Discard a subset of samples given by a specified sample mask. This acts like a 1893# per-sample discard, or an inverted accumulating gl_SampleMask write. The 1894# compiler will lower to sample_mask_agx, but that lowering is nontrivial as 1895# sample_mask_agx also triggers depth/stencil testing. 1896intrinsic("discard_agx", src_comp=[1]) 1897 1898# For a given row of the polygon stipple given as an integer source in [0, 31], 1899# load the 32-bit stipple pattern for that row. 1900intrinsic("load_polygon_stipple_agx", src_comp=[1], dest_comp=1, bit_sizes=[32], 1901 flags=[CAN_ELIMINATE, CAN_ELIMINATE]) 1902 1903# The fixed-function sample mask specified in the API (e.g. glSampleMask) 1904system_value("api_sample_mask_agx", 1, bit_sizes=[16]) 1905 1906# Loads the sample position array as fixed point packed into a 32-bit word 1907system_value("sample_positions_agx", 1, bit_sizes=[32]) 1908 1909# Loads the fixed-function glPointSize() value 1910system_value("fixed_point_size_agx", 1, bit_sizes=[32]) 1911 1912# Bit mask of TEX locations that are replaced with point sprites 1913system_value("tex_sprite_mask_agx", 1, bit_sizes=[16]) 1914 1915# Image loads go through the texture cache, which is not coherent with the PBE 1916# or memory access, so fencing is necessary for writes to become visible. 1917 1918# Make writes via main memory (image atomics) visible for texturing. 1919barrier("fence_pbe_to_tex_agx") 1920 1921# Make writes from global memory instructions (atomics) visible for texturing. 1922barrier("fence_mem_to_tex_agx") 1923 1924# Variant of fence_pbe_to_tex_agx specialized to stores in pixel shaders that 1925# act like render target writes, in conjunction with fragment interlock. 1926barrier("fence_pbe_to_tex_pixel_agx") 1927 1928# Unknown fence used in the helper program on exit. 1929barrier("fence_helper_exit_agx") 1930 1931# Address of state for AGX input assembly lowering for geometry/tessellation 1932system_value("input_assembly_buffer_agx", 1, bit_sizes=[64]) 1933 1934# Address of the parameter buffer for AGX geometry shaders 1935system_value("geometry_param_buffer_agx", 1, bit_sizes=[64]) 1936 1937# Address of the parameter buffer for AGX tessellation shaders 1938system_value("tess_param_buffer_agx", 1, bit_sizes=[64]) 1939 1940# Address of the pipeline statistic query result indexed by BASE 1941system_value("stat_query_address_agx", 1, bit_sizes=[64], indices=[BASE]) 1942 1943# Helper shader intrinsics 1944# src[] = { value }. 1945intrinsic("doorbell_agx", src_comp=[1]) 1946 1947# src[] = { index, stack_address }. 1948intrinsic("stack_map_agx", src_comp=[1, 1]) 1949 1950# src[] = { index }. 1951# dst[] = { stack_address }. 1952intrinsic("stack_unmap_agx", src_comp=[1], dest_comp=1, bit_sizes=[32]) 1953 1954# dst[] = { GPU core ID }. 1955system_value("core_id_agx", 1, bit_sizes=[32]) 1956 1957# dst[] = { Helper operation type }. 1958load("helper_op_id_agx", [], [], [CAN_ELIMINATE]) 1959 1960# dst[] = { Helper argument low 32 bits }. 1961load("helper_arg_lo_agx", [], [], [CAN_ELIMINATE]) 1962 1963# dst[] = { Helper argument high 32 bits }. 1964load("helper_arg_hi_agx", [], [], [CAN_ELIMINATE]) 1965 1966# Intel-specific query for loading from the isl_image_param struct passed 1967# into the shader as a uniform. The variable is a deref to the image 1968# variable. The const index specifies which of the six parameters to load. 1969intrinsic("image_deref_load_param_intel", src_comp=[1], dest_comp=0, 1970 indices=[BASE], flags=[CAN_ELIMINATE, CAN_REORDER]) 1971image("load_raw_intel", src_comp=[1], dest_comp=0, 1972 flags=[CAN_ELIMINATE]) 1973image("store_raw_intel", src_comp=[1, 0]) 1974 1975# Intrinsic to load a block of at least 32B of constant data from a 64-bit 1976# global memory address. The memory address must be uniform and 32B-aligned. 1977# The second source is a predicate which indicates whether or not to actually 1978# do the load. 1979# src[] = { address, predicate }. 1980intrinsic("load_global_const_block_intel", src_comp=[1, 1], dest_comp=0, 1981 bit_sizes=[32], indices=[BASE], flags=[CAN_ELIMINATE, CAN_REORDER]) 1982 1983# Number of data items being operated on for a SIMD program. 1984system_value("simd_width_intel", 1) 1985 1986# Load a relocatable 32-bit value 1987intrinsic("load_reloc_const_intel", dest_comp=1, bit_sizes=[32], 1988 indices=[PARAM_IDX], flags=[CAN_ELIMINATE, CAN_REORDER]) 1989 1990# 1 component 32bit surface index that can be used for bindless or BTI heaps 1991# 1992# This intrinsic is used to figure out what UBOs accesses could be promoted to 1993# push constants. To allow promoting a load_ubo to push constants, we need to 1994# know that the surface & offset are constants. If we want to use the bindless 1995# heap for this we have to build the surface index with a pushed constant for 1996# the descriptor set which prevents us from doing a nir_src_is_const() check. 1997# With this intrinsic, we can just check the surface_index src with 1998# nir_src_is_const() and ignore set_offset. 1999# 2000# src[] = { set_offset, surface_index, array_index } 2001intrinsic("resource_intel", dest_comp=1, bit_sizes=[32], 2002 src_comp=[1, 1, 1], 2003 indices=[DESC_SET, BINDING, RESOURCE_ACCESS_INTEL, RESOURCE_BLOCK_INTEL], 2004 flags=[CAN_ELIMINATE, CAN_REORDER]) 2005 2006# 64-bit global address for a Vulkan descriptor set 2007# src[0] = { set } 2008intrinsic("load_desc_set_address_intel", dest_comp=1, bit_sizes=[64], 2009 src_comp=[1], flags=[CAN_ELIMINATE, CAN_REORDER]) 2010 2011# Base offset for a given set in the flatten array of dynamic offsets 2012# src[0] = { set } 2013intrinsic("load_desc_set_dynamic_index_intel", dest_comp=1, bit_sizes=[32], 2014 src_comp=[1], flags=[CAN_ELIMINATE, CAN_REORDER]) 2015 2016# OpSubgroupBlockReadINTEL and OpSubgroupBlockWriteINTEL from SPV_INTEL_subgroups. 2017intrinsic("load_deref_block_intel", dest_comp=0, src_comp=[-1], 2018 indices=[ACCESS], flags=[CAN_ELIMINATE]) 2019intrinsic("store_deref_block_intel", src_comp=[-1, 0], indices=[WRITE_MASK, ACCESS]) 2020 2021# src[] = { address }. 2022load("global_block_intel", [1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 2023 2024# src[] = { buffer_index, offset }. 2025load("ssbo_block_intel", [-1, 1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 2026 2027# src[] = { offset }. 2028load("shared_block_intel", [1], [BASE, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 2029 2030# src[] = { value, address }. 2031store("global_block_intel", [1], [WRITE_MASK, ACCESS, ALIGN_MUL, ALIGN_OFFSET]) 2032 2033# src[] = { value, block_index, offset } 2034store("ssbo_block_intel", [-1, 1], [WRITE_MASK, ACCESS, ALIGN_MUL, ALIGN_OFFSET]) 2035 2036# src[] = { value, offset }. 2037store("shared_block_intel", [1], [BASE, WRITE_MASK, ALIGN_MUL, ALIGN_OFFSET]) 2038 2039# src[] = { address }. 2040load("global_constant_uniform_block_intel", [1], 2041 [ACCESS, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE, CAN_REORDER]) 2042 2043# Similar to load_global_const_block_intel but for UBOs 2044# offset should be uniform 2045# src[] = { buffer_index, offset }. 2046load("ubo_uniform_block_intel", [-1, 1], 2047 [ACCESS, ALIGN_MUL, ALIGN_OFFSET, RANGE_BASE, RANGE], [CAN_ELIMINATE, CAN_REORDER]) 2048 2049# Similar to load_global_const_block_intel but for SSBOs 2050# offset should be uniform 2051# src[] = { buffer_index, offset }. 2052load("ssbo_uniform_block_intel", [-1, 1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 2053 2054# Similar to load_global_const_block_intel but for shared memory 2055# src[] = { offset }. 2056load("shared_uniform_block_intel", [1], [BASE, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 2057 2058# Intrinsics for Intel mesh shading 2059system_value("mesh_inline_data_intel", 1, [ALIGN_OFFSET], bit_sizes=[32, 64]) 2060 2061# Intrinsics for Intel bindless thread dispatch 2062# BASE=brw_topoloy_id 2063system_value("topology_id_intel", 1, indices=[BASE]) 2064system_value("btd_stack_id_intel", 1) 2065system_value("btd_global_arg_addr_intel", 1, bit_sizes=[64]) 2066system_value("btd_local_arg_addr_intel", 1, bit_sizes=[64]) 2067system_value("btd_resume_sbt_addr_intel", 1, bit_sizes=[64]) 2068# src[] = { global_arg_addr, btd_record } 2069intrinsic("btd_spawn_intel", src_comp=[1, 1]) 2070# RANGE=stack_size 2071intrinsic("btd_stack_push_intel", indices=[STACK_SIZE]) 2072# src[] = { } 2073intrinsic("btd_retire_intel") 2074 2075# Intel-specific ray-tracing intrinsic 2076# src[] = { globals, level, operation } SYNCHRONOUS=synchronous 2077intrinsic("trace_ray_intel", src_comp=[1, 1, 1], indices=[SYNCHRONOUS]) 2078 2079# System values used for ray-tracing on Intel 2080system_value("ray_base_mem_addr_intel", 1, bit_sizes=[64]) 2081system_value("ray_hw_stack_size_intel", 1) 2082system_value("ray_sw_stack_size_intel", 1) 2083system_value("ray_num_dss_rt_stacks_intel", 1) 2084system_value("ray_hit_sbt_addr_intel", 1, bit_sizes=[64]) 2085system_value("ray_hit_sbt_stride_intel", 1, bit_sizes=[16]) 2086system_value("ray_miss_sbt_addr_intel", 1, bit_sizes=[64]) 2087system_value("ray_miss_sbt_stride_intel", 1, bit_sizes=[16]) 2088system_value("callable_sbt_addr_intel", 1, bit_sizes=[64]) 2089system_value("callable_sbt_stride_intel", 1, bit_sizes=[16]) 2090system_value("leaf_opaque_intel", 1, bit_sizes=[1]) 2091system_value("leaf_procedural_intel", 1, bit_sizes=[1]) 2092# Values : 2093# 0: AnyHit 2094# 1: ClosestHit 2095# 2: Miss 2096# 3: Intersection 2097system_value("btd_shader_type_intel", 1) 2098system_value("ray_query_global_intel", 1, bit_sizes=[64]) 2099 2100# Source 0: A matrix (type specified by SRC_TYPE) 2101# Source 1: B matrix (type specified by SRC_TYPE) 2102# Source 2: Accumulator matrix (type specified by DEST_TYPE) 2103# 2104# The matrix parameters are the slices owned by the invocation. 2105intrinsic("dpas_intel", dest_comp=0, src_comp=[0, 0, 0], 2106 indices=[DEST_TYPE, SRC_TYPE, SATURATE, CMAT_SIGNED_MASK, SYSTOLIC_DEPTH, REPEAT_COUNT], 2107 flags=[CAN_ELIMINATE]) 2108 2109# NVIDIA-specific intrinsics 2110intrinsic("load_sysval_nv", dest_comp=1, src_comp=[], bit_sizes=[32, 64], 2111 indices=[ACCESS, BASE], flags=[CAN_ELIMINATE]) 2112intrinsic("isberd_nv", dest_comp=1, src_comp=[1], bit_sizes=[32], 2113 flags=[CAN_ELIMINATE, CAN_REORDER]) 2114intrinsic("al2p_nv", dest_comp=1, src_comp=[1], bit_sizes=[32], 2115 indices=[BASE, FLAGS], flags=[CAN_ELIMINATE, CAN_REORDER]) 2116# src[] = { vtx, offset }. 2117# FLAGS is struct nak_nir_attr_io_flags 2118intrinsic("ald_nv", dest_comp=0, src_comp=[1, 1], bit_sizes=[32], 2119 indices=[BASE, RANGE_BASE, RANGE, FLAGS, ACCESS], 2120 flags=[CAN_ELIMINATE]) 2121# src[] = { data, vtx, offset }. 2122# FLAGS is struct nak_nir_attr_io_flags 2123intrinsic("ast_nv", src_comp=[0, 1, 1], 2124 indices=[BASE, RANGE_BASE, RANGE, FLAGS], flags=[]) 2125# src[] = { inv_w, offset }. 2126intrinsic("ipa_nv", dest_comp=1, src_comp=[1, 1], bit_sizes=[32], 2127 indices=[BASE, FLAGS], flags=[CAN_ELIMINATE, CAN_REORDER]) 2128# FLAGS indicate if we load vertex_id == 2 2129intrinsic("ldtram_nv", dest_comp=2, bit_sizes=[32], 2130 indices=[BASE, FLAGS], flags=[CAN_ELIMINATE, CAN_REORDER]) 2131 2132# NVIDIA-specific Geometry Shader intrinsics. 2133# These contain an additional integer source and destination with the primitive handle input/output. 2134intrinsic("emit_vertex_nv", dest_comp=1, src_comp=[1], indices=[STREAM_ID]) 2135intrinsic("end_primitive_nv", dest_comp=1, src_comp=[1], indices=[STREAM_ID]) 2136# Contains the final primitive handle and indicate the end of emission. 2137intrinsic("final_primitive_nv", src_comp=[1]) 2138 2139intrinsic("bar_set_nv", dest_comp=1, bit_sizes=[32], flags=[CAN_ELIMINATE]) 2140intrinsic("bar_break_nv", dest_comp=1, bit_sizes=[32], src_comp=[1]) 2141# src[] = { bar, bar_set } 2142intrinsic("bar_sync_nv", src_comp=[1, 1]) 2143 2144# Stall until the given SSA value is available 2145intrinsic("ssa_bar_nv", src_comp=[1]) 2146 2147# NVIDIA-specific system values 2148system_value("warps_per_sm_nv", 1, bit_sizes=[32]) 2149system_value("sm_count_nv", 1, bit_sizes=[32]) 2150system_value("warp_id_nv", 1, bit_sizes=[32]) 2151system_value("sm_id_nv", 1, bit_sizes=[32]) 2152 2153# In order to deal with flipped render targets, gl_PointCoord may be flipped 2154# in the shader requiring a shader key or extra instructions or it may be 2155# flipped in hardware based on a state bit. This version of gl_PointCoord 2156# is defined to be whatever thing the hardware can easily give you, so long as 2157# it's in normalized coordinates in the range [0, 1] across the point. 2158intrinsic("load_point_coord_maybe_flipped", dest_comp=2, bit_sizes=[32]) 2159 2160 2161# Load texture size values: 2162# 2163# Takes a sampler # and returns width, height and depth. If texture is a array 2164# texture it returns width, height and array size. Used for txs lowering. 2165intrinsic("load_texture_size_etna", src_comp=[1], dest_comp=3, 2166 flags=[CAN_ELIMINATE, CAN_REORDER]) 2167 2168# Zink specific intrinsics 2169 2170# src[] = { field }. 2171load("push_constant_zink", [1], [COMPONENT], [CAN_ELIMINATE, CAN_REORDER]) 2172 2173system_value("shader_index", 1, bit_sizes=[32]) 2174 2175system_value("coalesced_input_count", 1, bit_sizes=[32]) 2176 2177# Initialize a payload array per scope 2178# 2179# 0. Payloads deref 2180# 1. Payload count 2181# 2. Node index 2182intrinsic("initialize_node_payloads", src_comp=[-1, 1, 1], indices=[EXECUTION_SCOPE]) 2183 2184# Optionally enqueue payloads after shader finished writing to them 2185intrinsic("enqueue_node_payloads", src_comp=[-1]) 2186 2187# Returns true if it has been called for every payload. 2188intrinsic("finalize_incoming_node_payload", src_comp=[-1], dest_comp=1) 2189