1 /* 2 * Copyright © 2016 Broadcom 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 /** 25 * @file qpu_instr.h 26 * 27 * Definitions of the unpacked form of QPU instructions. Assembly and 28 * disassembly will use this for talking about instructions, with qpu_encode.c 29 * and qpu_decode.c handling the pack and unpack of the actual 64-bit QPU 30 * instruction. 31 */ 32 33 #ifndef QPU_INSTR_H 34 #define QPU_INSTR_H 35 36 #include <stdbool.h> 37 #include <stdint.h> 38 #include "util/macros.h" 39 40 struct v3d_device_info; 41 42 struct v3d_qpu_sig { 43 bool thrsw:1; 44 bool ldunif:1; 45 bool ldunifa:1; 46 bool ldunifrf:1; 47 bool ldunifarf:1; 48 bool ldtmu:1; 49 bool ldvary:1; 50 bool ldvpm:1; 51 bool ldtlb:1; 52 bool ldtlbu:1; 53 bool ucb:1; 54 bool rotate:1; 55 bool wrtmuc:1; 56 bool small_imm_a:1; /* raddr_a (add a), since V3D 7.x */ 57 bool small_imm_b:1; /* raddr_b (add b) */ 58 bool small_imm_c:1; /* raddr_c (mul a), since V3D 7.x */ 59 bool small_imm_d:1; /* raddr_d (mul b), since V3D 7.x */ 60 }; 61 62 enum v3d_qpu_cond { 63 V3D_QPU_COND_NONE, 64 V3D_QPU_COND_IFA, 65 V3D_QPU_COND_IFB, 66 V3D_QPU_COND_IFNA, 67 V3D_QPU_COND_IFNB, 68 }; 69 70 enum v3d_qpu_pf { 71 V3D_QPU_PF_NONE, 72 V3D_QPU_PF_PUSHZ, 73 V3D_QPU_PF_PUSHN, 74 V3D_QPU_PF_PUSHC, 75 }; 76 77 enum v3d_qpu_uf { 78 V3D_QPU_UF_NONE, 79 V3D_QPU_UF_ANDZ, 80 V3D_QPU_UF_ANDNZ, 81 V3D_QPU_UF_NORNZ, 82 V3D_QPU_UF_NORZ, 83 V3D_QPU_UF_ANDN, 84 V3D_QPU_UF_ANDNN, 85 V3D_QPU_UF_NORNN, 86 V3D_QPU_UF_NORN, 87 V3D_QPU_UF_ANDC, 88 V3D_QPU_UF_ANDNC, 89 V3D_QPU_UF_NORNC, 90 V3D_QPU_UF_NORC, 91 }; 92 93 enum v3d_qpu_waddr { 94 V3D_QPU_WADDR_R0 = 0, /* Reserved on V3D 7.x */ 95 V3D_QPU_WADDR_R1 = 1, /* Reserved on V3D 7.x */ 96 V3D_QPU_WADDR_R2 = 2, /* Reserved on V3D 7.x */ 97 V3D_QPU_WADDR_R3 = 3, /* Reserved on V3D 7.x */ 98 V3D_QPU_WADDR_R4 = 4, /* Reserved on V3D 7.x */ 99 V3D_QPU_WADDR_R5 = 5, /* V3D 4.x */ 100 V3D_QPU_WADDR_QUAD = 5, /* V3D 7.x */ 101 V3D_QPU_WADDR_NOP = 6, 102 V3D_QPU_WADDR_TLB = 7, 103 V3D_QPU_WADDR_TLBU = 8, 104 V3D_QPU_WADDR_TMU = 9, /* V3D 3.x */ 105 V3D_QPU_WADDR_UNIFA = 9, /* V3D 4.x */ 106 V3D_QPU_WADDR_TMUL = 10, 107 V3D_QPU_WADDR_TMUD = 11, 108 V3D_QPU_WADDR_TMUA = 12, 109 V3D_QPU_WADDR_TMUAU = 13, 110 V3D_QPU_WADDR_VPM = 14, 111 V3D_QPU_WADDR_VPMU = 15, 112 V3D_QPU_WADDR_SYNC = 16, 113 V3D_QPU_WADDR_SYNCU = 17, 114 V3D_QPU_WADDR_SYNCB = 18, 115 V3D_QPU_WADDR_RECIP = 19, /* Reserved on V3D 7.x */ 116 V3D_QPU_WADDR_RSQRT = 20, /* Reserved on V3D 7.x */ 117 V3D_QPU_WADDR_EXP = 21, /* Reserved on V3D 7.x */ 118 V3D_QPU_WADDR_LOG = 22, /* Reserved on V3D 7.x */ 119 V3D_QPU_WADDR_SIN = 23, /* Reserved on V3D 7.x */ 120 V3D_QPU_WADDR_RSQRT2 = 24, /* Reserved on V3D 7.x */ 121 V3D_QPU_WADDR_TMUC = 32, 122 V3D_QPU_WADDR_TMUS = 33, 123 V3D_QPU_WADDR_TMUT = 34, 124 V3D_QPU_WADDR_TMUR = 35, 125 V3D_QPU_WADDR_TMUI = 36, 126 V3D_QPU_WADDR_TMUB = 37, 127 V3D_QPU_WADDR_TMUDREF = 38, 128 V3D_QPU_WADDR_TMUOFF = 39, 129 V3D_QPU_WADDR_TMUSCM = 40, 130 V3D_QPU_WADDR_TMUSF = 41, 131 V3D_QPU_WADDR_TMUSLOD = 42, 132 V3D_QPU_WADDR_TMUHS = 43, 133 V3D_QPU_WADDR_TMUHSCM = 44, 134 V3D_QPU_WADDR_TMUHSF = 45, 135 V3D_QPU_WADDR_TMUHSLOD = 46, 136 V3D_QPU_WADDR_R5REP = 55, /* V3D 4.x */ 137 V3D_QPU_WADDR_REP = 55, /* V3D 7.x */ 138 }; 139 140 struct v3d_qpu_flags { 141 enum v3d_qpu_cond ac, mc; 142 enum v3d_qpu_pf apf, mpf; 143 enum v3d_qpu_uf auf, muf; 144 }; 145 146 enum v3d_qpu_add_op { 147 V3D_QPU_A_FADD, 148 V3D_QPU_A_FADDNF, 149 V3D_QPU_A_VFPACK, 150 V3D_QPU_A_ADD, 151 V3D_QPU_A_SUB, 152 V3D_QPU_A_FSUB, 153 V3D_QPU_A_MIN, 154 V3D_QPU_A_MAX, 155 V3D_QPU_A_UMIN, 156 V3D_QPU_A_UMAX, 157 V3D_QPU_A_SHL, 158 V3D_QPU_A_SHR, 159 V3D_QPU_A_ASR, 160 V3D_QPU_A_ROR, 161 V3D_QPU_A_FMIN, 162 V3D_QPU_A_FMAX, 163 V3D_QPU_A_VFMIN, 164 V3D_QPU_A_AND, 165 V3D_QPU_A_OR, 166 V3D_QPU_A_XOR, 167 V3D_QPU_A_VADD, 168 V3D_QPU_A_VSUB, 169 V3D_QPU_A_NOT, 170 V3D_QPU_A_NEG, 171 V3D_QPU_A_FLAPUSH, 172 V3D_QPU_A_FLBPUSH, 173 V3D_QPU_A_FLPOP, 174 V3D_QPU_A_RECIP, 175 V3D_QPU_A_SETMSF, 176 V3D_QPU_A_SETREVF, 177 V3D_QPU_A_NOP, 178 V3D_QPU_A_TIDX, 179 V3D_QPU_A_EIDX, 180 V3D_QPU_A_LR, 181 V3D_QPU_A_VFLA, 182 V3D_QPU_A_VFLNA, 183 V3D_QPU_A_VFLB, 184 V3D_QPU_A_VFLNB, 185 V3D_QPU_A_FXCD, 186 V3D_QPU_A_XCD, 187 V3D_QPU_A_FYCD, 188 V3D_QPU_A_YCD, 189 V3D_QPU_A_MSF, 190 V3D_QPU_A_REVF, 191 V3D_QPU_A_VDWWT, 192 V3D_QPU_A_IID, 193 V3D_QPU_A_SAMPID, 194 V3D_QPU_A_BARRIERID, 195 V3D_QPU_A_TMUWT, 196 V3D_QPU_A_VPMSETUP, 197 V3D_QPU_A_VPMWT, 198 V3D_QPU_A_FLAFIRST, 199 V3D_QPU_A_FLNAFIRST, 200 V3D_QPU_A_LDVPMV_IN, 201 V3D_QPU_A_LDVPMV_OUT, 202 V3D_QPU_A_LDVPMD_IN, 203 V3D_QPU_A_LDVPMD_OUT, 204 V3D_QPU_A_LDVPMP, 205 V3D_QPU_A_RSQRT, 206 V3D_QPU_A_EXP, 207 V3D_QPU_A_LOG, 208 V3D_QPU_A_SIN, 209 V3D_QPU_A_RSQRT2, 210 V3D_QPU_A_LDVPMG_IN, 211 V3D_QPU_A_LDVPMG_OUT, 212 V3D_QPU_A_FCMP, 213 V3D_QPU_A_VFMAX, 214 V3D_QPU_A_FROUND, 215 V3D_QPU_A_FTOIN, 216 V3D_QPU_A_FTRUNC, 217 V3D_QPU_A_FTOIZ, 218 V3D_QPU_A_FFLOOR, 219 V3D_QPU_A_FTOUZ, 220 V3D_QPU_A_FCEIL, 221 V3D_QPU_A_FTOC, 222 V3D_QPU_A_FDX, 223 V3D_QPU_A_FDY, 224 V3D_QPU_A_STVPMV, 225 V3D_QPU_A_STVPMD, 226 V3D_QPU_A_STVPMP, 227 V3D_QPU_A_ITOF, 228 V3D_QPU_A_CLZ, 229 V3D_QPU_A_UTOF, 230 231 /* V3D 7.x */ 232 V3D_QPU_A_FMOV, 233 V3D_QPU_A_MOV, 234 V3D_QPU_A_VPACK, 235 V3D_QPU_A_V8PACK, 236 V3D_QPU_A_V10PACK, 237 V3D_QPU_A_V11FPACK, 238 V3D_QPU_A_BALLOT, 239 V3D_QPU_A_BCASTF, 240 V3D_QPU_A_ALLEQ, 241 V3D_QPU_A_ALLFEQ, 242 V3D_QPU_A_ROTQ, 243 V3D_QPU_A_ROT, 244 V3D_QPU_A_SHUFFLE, 245 }; 246 247 enum v3d_qpu_mul_op { 248 V3D_QPU_M_ADD, 249 V3D_QPU_M_SUB, 250 V3D_QPU_M_UMUL24, 251 V3D_QPU_M_VFMUL, 252 V3D_QPU_M_SMUL24, 253 V3D_QPU_M_MULTOP, 254 V3D_QPU_M_FMOV, 255 V3D_QPU_M_MOV, 256 V3D_QPU_M_NOP, 257 V3D_QPU_M_FMUL, 258 259 /* V3D 7.x */ 260 V3D_QPU_M_FTOUNORM16, 261 V3D_QPU_M_FTOSNORM16, 262 V3D_QPU_M_VFTOUNORM8, 263 V3D_QPU_M_VFTOSNORM8, 264 V3D_QPU_M_VFTOUNORM10LO, 265 V3D_QPU_M_VFTOUNORM10HI, 266 }; 267 268 enum v3d_qpu_output_pack { 269 V3D_QPU_PACK_NONE, 270 /** 271 * Convert to 16-bit float, put in low 16 bits of destination leaving 272 * high unmodified. 273 */ 274 V3D_QPU_PACK_L, 275 /** 276 * Convert to 16-bit float, put in high 16 bits of destination leaving 277 * low unmodified. 278 */ 279 V3D_QPU_PACK_H, 280 }; 281 282 enum v3d_qpu_input_unpack { 283 /** 284 * No-op input unpacking. Note that this enum's value doesn't match 285 * the packed QPU instruction value of the field (we use 0 so that the 286 * default on new instruction creation is no-op). 287 */ 288 V3D_QPU_UNPACK_NONE, 289 /** Absolute value. Only available for some operations. */ 290 V3D_QPU_UNPACK_ABS, 291 /** Convert low 16 bits from 16-bit float to 32-bit float. */ 292 V3D_QPU_UNPACK_L, 293 /** Convert high 16 bits from 16-bit float to 32-bit float. */ 294 V3D_QPU_UNPACK_H, 295 296 /** Convert to 16f and replicate it to the high bits. */ 297 V3D_QPU_UNPACK_REPLICATE_32F_16, 298 299 /** Replicate low 16 bits to high */ 300 V3D_QPU_UNPACK_REPLICATE_L_16, 301 302 /** Replicate high 16 bits to low */ 303 V3D_QPU_UNPACK_REPLICATE_H_16, 304 305 /** Swap high and low 16 bits */ 306 V3D_QPU_UNPACK_SWAP_16, 307 308 /** Convert low 16 bits from 16-bit integer to unsigned 32-bit int */ 309 V3D_QPU_UNPACK_UL, 310 /** Convert high 16 bits from 16-bit integer to unsigned 32-bit int */ 311 V3D_QPU_UNPACK_UH, 312 /** Convert low 16 bits from 16-bit integer to signed 32-bit int */ 313 V3D_QPU_UNPACK_IL, 314 /** Convert high 16 bits from 16-bit integer to signed 32-bit int */ 315 V3D_QPU_UNPACK_IH, 316 }; 317 318 enum v3d_qpu_mux { 319 V3D_QPU_MUX_R0, 320 V3D_QPU_MUX_R1, 321 V3D_QPU_MUX_R2, 322 V3D_QPU_MUX_R3, 323 V3D_QPU_MUX_R4, 324 V3D_QPU_MUX_R5, 325 V3D_QPU_MUX_A, 326 V3D_QPU_MUX_B, 327 }; 328 329 struct v3d_qpu_input { 330 union { 331 enum v3d_qpu_mux mux; /* V3D 4.x */ 332 uint8_t raddr; /* V3D 7.x */ 333 }; 334 enum v3d_qpu_input_unpack unpack; 335 }; 336 337 struct v3d_qpu_alu_instr { 338 struct { 339 enum v3d_qpu_add_op op; 340 struct v3d_qpu_input a, b; 341 uint8_t waddr; 342 bool magic_write; 343 enum v3d_qpu_output_pack output_pack; 344 } add; 345 346 struct { 347 enum v3d_qpu_mul_op op; 348 struct v3d_qpu_input a, b; 349 uint8_t waddr; 350 bool magic_write; 351 enum v3d_qpu_output_pack output_pack; 352 } mul; 353 }; 354 355 enum v3d_qpu_branch_cond { 356 V3D_QPU_BRANCH_COND_ALWAYS, 357 V3D_QPU_BRANCH_COND_A0, 358 V3D_QPU_BRANCH_COND_NA0, 359 V3D_QPU_BRANCH_COND_ALLA, 360 V3D_QPU_BRANCH_COND_ANYNA, 361 V3D_QPU_BRANCH_COND_ANYA, 362 V3D_QPU_BRANCH_COND_ALLNA, 363 }; 364 365 enum v3d_qpu_msfign { 366 /** Ignore multisample flags when determining branch condition. */ 367 V3D_QPU_MSFIGN_NONE, 368 /** 369 * If no multisample flags are set in the lane (a pixel in the FS, a 370 * vertex in the VS), ignore the lane's condition when computing the 371 * branch condition. 372 */ 373 V3D_QPU_MSFIGN_P, 374 /** 375 * If no multisample flags are set in a 2x2 quad in the FS, ignore the 376 * quad's a/b conditions. 377 */ 378 V3D_QPU_MSFIGN_Q, 379 }; 380 381 enum v3d_qpu_branch_dest { 382 V3D_QPU_BRANCH_DEST_ABS, 383 V3D_QPU_BRANCH_DEST_REL, 384 V3D_QPU_BRANCH_DEST_LINK_REG, 385 V3D_QPU_BRANCH_DEST_REGFILE, 386 }; 387 388 struct v3d_qpu_branch_instr { 389 enum v3d_qpu_branch_cond cond; 390 enum v3d_qpu_msfign msfign; 391 392 /** Selects how to compute the new IP if the branch is taken. */ 393 enum v3d_qpu_branch_dest bdi; 394 395 /** 396 * Selects how to compute the new uniforms pointer if the branch is 397 * taken. (ABS/REL implicitly load a uniform and use that) 398 */ 399 enum v3d_qpu_branch_dest bdu; 400 401 /** 402 * If set, then udest determines how the uniform stream will branch, 403 * otherwise the uniform stream is left as is. 404 */ 405 bool ub; 406 407 uint8_t raddr_a; 408 409 uint32_t offset; 410 }; 411 412 enum v3d_qpu_instr_type { 413 V3D_QPU_INSTR_TYPE_ALU, 414 V3D_QPU_INSTR_TYPE_BRANCH, 415 }; 416 417 struct v3d_qpu_instr { 418 enum v3d_qpu_instr_type type; 419 420 struct v3d_qpu_sig sig; 421 uint8_t sig_addr; 422 bool sig_magic; /* If the signal writes to a magic address */ 423 uint8_t raddr_a; /* V3D 4.x */ 424 uint8_t raddr_b; /* V3D 4.x (holds packed small immediate in 7.x too) */ 425 struct v3d_qpu_flags flags; 426 427 union { 428 struct v3d_qpu_alu_instr alu; 429 struct v3d_qpu_branch_instr branch; 430 }; 431 }; 432 433 const char *v3d_qpu_magic_waddr_name(const struct v3d_device_info *devinfo, 434 enum v3d_qpu_waddr waddr); 435 const char *v3d_qpu_add_op_name(enum v3d_qpu_add_op op); 436 const char *v3d_qpu_mul_op_name(enum v3d_qpu_mul_op op); 437 const char *v3d_qpu_cond_name(enum v3d_qpu_cond cond); 438 const char *v3d_qpu_pf_name(enum v3d_qpu_pf pf); 439 const char *v3d_qpu_uf_name(enum v3d_qpu_uf uf); 440 const char *v3d_qpu_pack_name(enum v3d_qpu_output_pack pack); 441 const char *v3d_qpu_unpack_name(enum v3d_qpu_input_unpack unpack); 442 const char *v3d_qpu_branch_cond_name(enum v3d_qpu_branch_cond cond); 443 const char *v3d_qpu_msfign_name(enum v3d_qpu_msfign msfign); 444 445 enum v3d_qpu_cond v3d_qpu_cond_invert(enum v3d_qpu_cond cond) ATTRIBUTE_CONST; 446 447 bool v3d_qpu_add_op_has_dst(enum v3d_qpu_add_op op); 448 bool v3d_qpu_mul_op_has_dst(enum v3d_qpu_mul_op op); 449 int v3d_qpu_add_op_num_src(enum v3d_qpu_add_op op); 450 int v3d_qpu_mul_op_num_src(enum v3d_qpu_mul_op op); 451 452 bool v3d_qpu_sig_pack(const struct v3d_device_info *devinfo, 453 const struct v3d_qpu_sig *sig, 454 uint32_t *packed_sig); 455 bool v3d_qpu_sig_unpack(const struct v3d_device_info *devinfo, 456 uint32_t packed_sig, 457 struct v3d_qpu_sig *sig); 458 459 bool 460 v3d_qpu_flags_pack(const struct v3d_device_info *devinfo, 461 const struct v3d_qpu_flags *cond, 462 uint32_t *packed_cond); 463 bool 464 v3d_qpu_flags_unpack(const struct v3d_device_info *devinfo, 465 uint32_t packed_cond, 466 struct v3d_qpu_flags *cond); 467 468 bool 469 v3d_qpu_small_imm_pack(const struct v3d_device_info *devinfo, 470 uint32_t value, 471 uint32_t *packed_small_immediate); 472 473 bool 474 v3d_qpu_small_imm_unpack(const struct v3d_device_info *devinfo, 475 uint32_t packed_small_immediate, 476 uint32_t *small_immediate); 477 478 bool 479 v3d_qpu_instr_pack(const struct v3d_device_info *devinfo, 480 const struct v3d_qpu_instr *instr, 481 uint64_t *packed_instr); 482 bool 483 v3d_qpu_instr_unpack(const struct v3d_device_info *devinfo, 484 uint64_t packed_instr, 485 struct v3d_qpu_instr *instr); 486 487 bool v3d_qpu_magic_waddr_is_sfu(enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST; 488 bool v3d_qpu_magic_waddr_is_tmu(const struct v3d_device_info *devinfo, 489 enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST; 490 bool v3d_qpu_magic_waddr_is_tlb(enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST; 491 bool v3d_qpu_magic_waddr_is_vpm(enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST; 492 bool v3d_qpu_magic_waddr_is_tsy(enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST; 493 bool v3d_qpu_magic_waddr_loads_unif(enum v3d_qpu_waddr waddr) ATTRIBUTE_CONST; 494 bool v3d_qpu_reads_tlb(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST; 495 bool v3d_qpu_writes_tlb(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST; 496 bool v3d_qpu_uses_tlb(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST; 497 bool v3d_qpu_instr_is_sfu(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST; 498 bool v3d_qpu_instr_is_legacy_sfu(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST; 499 bool v3d_qpu_uses_sfu(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST; 500 bool v3d_qpu_writes_tmu(const struct v3d_device_info *devinfo, 501 const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST; 502 bool v3d_qpu_writes_tmu_not_tmuc(const struct v3d_device_info *devinfo, 503 const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST; 504 bool v3d_qpu_writes_r3(const struct v3d_device_info *devinfo, 505 const struct v3d_qpu_instr *instr) ATTRIBUTE_CONST; 506 bool v3d_qpu_writes_r4(const struct v3d_device_info *devinfo, 507 const struct v3d_qpu_instr *instr) ATTRIBUTE_CONST; 508 bool v3d_qpu_writes_r5(const struct v3d_device_info *devinfo, 509 const struct v3d_qpu_instr *instr) ATTRIBUTE_CONST; 510 bool v3d_qpu_writes_rf0_implicitly(const struct v3d_device_info *devinfo, 511 const struct v3d_qpu_instr *instr) ATTRIBUTE_CONST; 512 bool v3d_qpu_writes_accum(const struct v3d_device_info *devinfo, 513 const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST; 514 bool v3d_qpu_waits_on_tmu(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST; 515 bool v3d_qpu_uses_mux(const struct v3d_qpu_instr *inst, enum v3d_qpu_mux mux); 516 bool v3d_qpu_uses_vpm(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST; 517 bool v3d_qpu_waits_vpm(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST; 518 bool v3d_qpu_reads_vpm(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST; 519 bool v3d_qpu_writes_vpm(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST; 520 bool v3d_qpu_reads_or_writes_vpm(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST; 521 bool v3d_qpu_reads_flags(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST; 522 bool v3d_qpu_writes_flags(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST; 523 bool v3d_qpu_writes_unifa(const struct v3d_device_info *devinfo, 524 const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST; 525 bool v3d_qpu_sig_writes_address(const struct v3d_device_info *devinfo, 526 const struct v3d_qpu_sig *sig) ATTRIBUTE_CONST; 527 bool v3d_qpu_unpacks_f32(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST; 528 bool v3d_qpu_unpacks_f16(const struct v3d_qpu_instr *inst) ATTRIBUTE_CONST; 529 530 bool v3d_qpu_is_nop(struct v3d_qpu_instr *inst) ATTRIBUTE_CONST; 531 532 bool v3d71_qpu_reads_raddr(const struct v3d_qpu_instr *inst, uint8_t raddr); 533 bool v3d71_qpu_writes_waddr_explicitly(const struct v3d_device_info *devinfo, 534 const struct v3d_qpu_instr *inst, 535 uint8_t waddr); 536 #endif 537