1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based on si_state.c
6 * Copyright © 2015 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 /* command buffer handling for AMD GCN */
29
30 #include "radv_cs.h"
31 #include "radv_private.h"
32 #include "radv_shader.h"
33 #include "sid.h"
34
35 static void
radv_write_harvested_raster_configs(struct radv_physical_device * physical_device,struct radeon_cmdbuf * cs,unsigned raster_config,unsigned raster_config_1)36 radv_write_harvested_raster_configs(struct radv_physical_device *physical_device, struct radeon_cmdbuf *cs,
37 unsigned raster_config, unsigned raster_config_1)
38 {
39 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1);
40 unsigned raster_config_se[4];
41 unsigned se;
42
43 ac_get_harvested_configs(&physical_device->rad_info, raster_config, &raster_config_1, raster_config_se);
44
45 for (se = 0; se < num_se; se++) {
46 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
47 if (physical_device->rad_info.gfx_level < GFX7)
48 radeon_set_config_reg(
49 cs, R_00802C_GRBM_GFX_INDEX,
50 S_00802C_SE_INDEX(se) | S_00802C_SH_BROADCAST_WRITES(1) | S_00802C_INSTANCE_BROADCAST_WRITES(1));
51 else
52 radeon_set_uconfig_reg(
53 cs, R_030800_GRBM_GFX_INDEX,
54 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) | S_030800_INSTANCE_BROADCAST_WRITES(1));
55 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
56 }
57
58 /* GRBM_GFX_INDEX has a different offset on GFX6 and GFX7+ */
59 if (physical_device->rad_info.gfx_level < GFX7)
60 radeon_set_config_reg(
61 cs, R_00802C_GRBM_GFX_INDEX,
62 S_00802C_SE_BROADCAST_WRITES(1) | S_00802C_SH_BROADCAST_WRITES(1) | S_00802C_INSTANCE_BROADCAST_WRITES(1));
63 else
64 radeon_set_uconfig_reg(
65 cs, R_030800_GRBM_GFX_INDEX,
66 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) | S_030800_INSTANCE_BROADCAST_WRITES(1));
67
68 if (physical_device->rad_info.gfx_level >= GFX7)
69 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
70 }
71
72 void
radv_emit_compute(struct radv_device * device,struct radeon_cmdbuf * cs)73 radv_emit_compute(struct radv_device *device, struct radeon_cmdbuf *cs)
74 {
75 const struct radeon_info *info = &device->physical_device->rad_info;
76
77 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
78 radeon_emit(cs, 0);
79 radeon_emit(cs, 0);
80 radeon_emit(cs, 0);
81
82 radeon_set_sh_reg(cs, R_00B834_COMPUTE_PGM_HI, S_00B834_DATA(device->physical_device->rad_info.address32_hi >> 8));
83
84 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
85 /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1,
86 * renamed COMPUTE_DESTINATION_EN_SEn on gfx10. */
87 radeon_emit(cs, S_00B858_SH0_CU_EN(info->spi_cu_en) | S_00B858_SH1_CU_EN(info->spi_cu_en));
88 radeon_emit(cs, S_00B858_SH0_CU_EN(info->spi_cu_en) | S_00B858_SH1_CU_EN(info->spi_cu_en));
89
90 if (device->physical_device->rad_info.gfx_level >= GFX7) {
91 /* Also set R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 */
92 radeon_set_sh_reg_seq(cs, R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
93 radeon_emit(cs, S_00B858_SH0_CU_EN(info->spi_cu_en) | S_00B858_SH1_CU_EN(info->spi_cu_en));
94 radeon_emit(cs, S_00B858_SH0_CU_EN(info->spi_cu_en) | S_00B858_SH1_CU_EN(info->spi_cu_en));
95
96 if (device->border_color_data.bo) {
97 uint64_t bc_va = radv_buffer_get_va(device->border_color_data.bo);
98
99 radeon_set_uconfig_reg_seq(cs, R_030E00_TA_CS_BC_BASE_ADDR, 2);
100 radeon_emit(cs, bc_va >> 8);
101 radeon_emit(cs, S_030E04_ADDRESS(bc_va >> 40));
102 }
103 }
104
105 if (device->physical_device->rad_info.gfx_level >= GFX9 && device->physical_device->rad_info.gfx_level < GFX11) {
106 radeon_set_uconfig_reg(cs, R_0301EC_CP_COHER_START_DELAY,
107 device->physical_device->rad_info.gfx_level >= GFX10 ? 0x20 : 0);
108 }
109
110 if (device->physical_device->rad_info.gfx_level >= GFX10) {
111 radeon_set_sh_reg_seq(cs, R_00B890_COMPUTE_USER_ACCUM_0, 4);
112 radeon_emit(cs, 0); /* R_00B890_COMPUTE_USER_ACCUM_0 */
113 radeon_emit(cs, 0); /* R_00B894_COMPUTE_USER_ACCUM_1 */
114 radeon_emit(cs, 0); /* R_00B898_COMPUTE_USER_ACCUM_2 */
115 radeon_emit(cs, 0); /* R_00B89C_COMPUTE_USER_ACCUM_3 */
116
117 radeon_set_sh_reg(cs, R_00B9F4_COMPUTE_DISPATCH_TUNNEL, 0);
118 }
119
120 if (device->physical_device->rad_info.gfx_level == GFX6) {
121 if (device->border_color_data.bo) {
122 uint64_t bc_va = radv_buffer_get_va(device->border_color_data.bo);
123 radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR, bc_va >> 8);
124 }
125 }
126
127 if (device->tma_bo) {
128 uint64_t tba_va, tma_va;
129
130 assert(device->physical_device->rad_info.gfx_level == GFX8);
131
132 tba_va = radv_shader_get_va(device->trap_handler_shader);
133 tma_va = radv_buffer_get_va(device->tma_bo);
134
135 radeon_set_sh_reg_seq(cs, R_00B838_COMPUTE_TBA_LO, 4);
136 radeon_emit(cs, tba_va >> 8);
137 radeon_emit(cs, tba_va >> 40);
138 radeon_emit(cs, tma_va >> 8);
139 radeon_emit(cs, tma_va >> 40);
140 }
141
142 if (device->physical_device->rad_info.gfx_level >= GFX11) {
143 uint32_t spi_cu_en = device->physical_device->rad_info.spi_cu_en;
144
145 radeon_set_sh_reg_seq(cs, R_00B8AC_COMPUTE_STATIC_THREAD_MGMT_SE4, 4);
146 radeon_emit(cs, S_00B8AC_SA0_CU_EN(spi_cu_en) | S_00B8AC_SA1_CU_EN(spi_cu_en)); /* SE4 */
147 radeon_emit(cs, S_00B8AC_SA0_CU_EN(spi_cu_en) | S_00B8AC_SA1_CU_EN(spi_cu_en)); /* SE5 */
148 radeon_emit(cs, S_00B8AC_SA0_CU_EN(spi_cu_en) | S_00B8AC_SA1_CU_EN(spi_cu_en)); /* SE6 */
149 radeon_emit(cs, S_00B8AC_SA0_CU_EN(spi_cu_en) | S_00B8AC_SA1_CU_EN(spi_cu_en)); /* SE7 */
150
151 radeon_set_sh_reg(cs, R_00B8BC_COMPUTE_DISPATCH_INTERLEAVE, 64);
152 }
153 }
154
155 /* 12.4 fixed-point */
156 static unsigned
radv_pack_float_12p4(float x)157 radv_pack_float_12p4(float x)
158 {
159 return x <= 0 ? 0 : x >= 4096 ? 0xffff : x * 16;
160 }
161
162 static void
radv_set_raster_config(struct radv_physical_device * physical_device,struct radeon_cmdbuf * cs)163 radv_set_raster_config(struct radv_physical_device *physical_device, struct radeon_cmdbuf *cs)
164 {
165 unsigned num_rb = MIN2(physical_device->rad_info.max_render_backends, 16);
166 uint64_t rb_mask = physical_device->rad_info.enabled_rb_mask;
167 unsigned raster_config, raster_config_1;
168
169 ac_get_raster_config(&physical_device->rad_info, &raster_config, &raster_config_1, NULL);
170
171 /* Always use the default config when all backends are enabled
172 * (or when we failed to determine the enabled backends).
173 */
174 if (!rb_mask || util_bitcount64(rb_mask) >= num_rb) {
175 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config);
176 if (physical_device->rad_info.gfx_level >= GFX7)
177 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
178 } else {
179 radv_write_harvested_raster_configs(physical_device, cs, raster_config, raster_config_1);
180 }
181 }
182
183 void
radv_emit_graphics(struct radv_device * device,struct radeon_cmdbuf * cs)184 radv_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs)
185 {
186 struct radv_physical_device *physical_device = device->physical_device;
187
188 bool has_clear_state = physical_device->rad_info.has_clear_state;
189 int i;
190
191 if (!device->uses_shadow_regs) {
192 radeon_emit(cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
193 radeon_emit(cs, CC0_UPDATE_LOAD_ENABLES(1));
194 radeon_emit(cs, CC1_UPDATE_SHADOW_ENABLES(1));
195
196 if (has_clear_state) {
197 radeon_emit(cs, PKT3(PKT3_CLEAR_STATE, 0, 0));
198 radeon_emit(cs, 0);
199 }
200 }
201
202 if (physical_device->rad_info.gfx_level <= GFX8)
203 radv_set_raster_config(physical_device, cs);
204
205 /* Emulated in shader code on GFX9+. */
206 if (physical_device->rad_info.gfx_level >= GFX9)
207 radeon_set_context_reg(cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE, 1);
208
209 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
210 if (!has_clear_state)
211 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
212
213 /* FIXME calculate these values somehow ??? */
214 if (physical_device->rad_info.gfx_level <= GFX8) {
215 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
216 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40);
217 }
218
219 if (!has_clear_state) {
220 if (physical_device->rad_info.gfx_level < GFX11) {
221 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2);
222 radeon_set_context_reg(cs, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
223 }
224 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
225 }
226
227 if (physical_device->rad_info.gfx_level <= GFX9)
228 radeon_set_context_reg(cs, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
229 if (!has_clear_state && physical_device->rad_info.gfx_level < GFX11)
230 radeon_set_context_reg(cs, R_028AB8_VGT_VTX_CNT_EN, 0x0);
231 if (physical_device->rad_info.gfx_level < GFX7)
232 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) | S_008A14_CLIP_VTX_REORDER_ENA(1));
233
234 if (!has_clear_state)
235 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
236
237 /* CLEAR_STATE doesn't clear these correctly on certain generations.
238 * I don't know why. Deduced by trial and error.
239 */
240 if (physical_device->rad_info.gfx_level <= GFX7 || !has_clear_state) {
241 radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
242 radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
243 radeon_set_context_reg(cs, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
244 radeon_set_context_reg(cs, R_028244_PA_SC_GENERIC_SCISSOR_BR,
245 S_028244_BR_X(MAX_FRAMEBUFFER_WIDTH) | S_028244_BR_Y(MAX_FRAMEBUFFER_HEIGHT));
246 radeon_set_context_reg(cs, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
247 }
248
249 if (!has_clear_state) {
250 for (i = 0; i < 16; i++) {
251 radeon_set_context_reg(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 + i * 8, 0);
252 radeon_set_context_reg(cs, R_0282D4_PA_SC_VPORT_ZMAX_0 + i * 8, fui(1.0));
253 }
254 }
255
256 if (!has_clear_state) {
257 radeon_set_context_reg(cs, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
258 radeon_set_context_reg(cs, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
259 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on GFX6 */
260 radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
261 radeon_set_context_reg(cs, R_028820_PA_CL_NANINF_CNTL, 0);
262 radeon_set_context_reg(cs, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
263 radeon_set_context_reg(cs, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
264 radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
265 }
266
267 radeon_set_context_reg(
268 cs, R_02800C_DB_RENDER_OVERRIDE,
269 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) | S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
270
271 if (physical_device->rad_info.gfx_level >= GFX10) {
272 radeon_set_context_reg(cs, R_028A98_VGT_DRAW_PAYLOAD_CNTL, 0);
273 radeon_set_uconfig_reg(cs, R_030964_GE_MAX_VTX_INDX, ~0);
274 radeon_set_uconfig_reg(cs, R_030924_GE_MIN_VTX_INDX, 0);
275 radeon_set_uconfig_reg(cs, R_030928_GE_INDX_OFFSET, 0);
276 radeon_set_uconfig_reg(cs, R_03097C_GE_STEREO_CNTL, 0);
277 radeon_set_uconfig_reg(cs, R_030988_GE_USER_VGPR_EN, 0);
278
279 if (physical_device->rad_info.gfx_level < GFX11) {
280 radeon_set_context_reg(cs, R_028038_DB_DFSM_CONTROL, S_028038_PUNCHOUT_MODE(V_028038_FORCE_OFF));
281 }
282 } else if (physical_device->rad_info.gfx_level == GFX9) {
283 radeon_set_uconfig_reg(cs, R_030920_VGT_MAX_VTX_INDX, ~0);
284 radeon_set_uconfig_reg(cs, R_030924_VGT_MIN_VTX_INDX, 0);
285 radeon_set_uconfig_reg(cs, R_030928_VGT_INDX_OFFSET, 0);
286
287 radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL, S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF));
288 } else {
289 /* These registers, when written, also overwrite the
290 * CLEAR_STATE context, so we can't rely on CLEAR_STATE setting
291 * them. It would be an issue if there was another UMD
292 * changing them.
293 */
294 radeon_set_context_reg(cs, R_028400_VGT_MAX_VTX_INDX, ~0);
295 radeon_set_context_reg(cs, R_028404_VGT_MIN_VTX_INDX, 0);
296 radeon_set_context_reg(cs, R_028408_VGT_INDX_OFFSET, 0);
297 }
298
299 if (device->physical_device->rad_info.gfx_level >= GFX10) {
300 radeon_set_sh_reg(cs, R_00B524_SPI_SHADER_PGM_HI_LS,
301 S_00B524_MEM_BASE(device->physical_device->rad_info.address32_hi >> 8));
302 radeon_set_sh_reg(cs, R_00B324_SPI_SHADER_PGM_HI_ES,
303 S_00B324_MEM_BASE(device->physical_device->rad_info.address32_hi >> 8));
304 } else if (device->physical_device->rad_info.gfx_level == GFX9) {
305 radeon_set_sh_reg(cs, R_00B414_SPI_SHADER_PGM_HI_LS,
306 S_00B414_MEM_BASE(device->physical_device->rad_info.address32_hi >> 8));
307 radeon_set_sh_reg(cs, R_00B214_SPI_SHADER_PGM_HI_ES,
308 S_00B214_MEM_BASE(device->physical_device->rad_info.address32_hi >> 8));
309 } else {
310 radeon_set_sh_reg(cs, R_00B524_SPI_SHADER_PGM_HI_LS,
311 S_00B524_MEM_BASE(device->physical_device->rad_info.address32_hi >> 8));
312 radeon_set_sh_reg(cs, R_00B324_SPI_SHADER_PGM_HI_ES,
313 S_00B324_MEM_BASE(device->physical_device->rad_info.address32_hi >> 8));
314 }
315
316 if (device->physical_device->rad_info.gfx_level < GFX11)
317 radeon_set_sh_reg(cs, R_00B124_SPI_SHADER_PGM_HI_VS,
318 S_00B124_MEM_BASE(device->physical_device->rad_info.address32_hi >> 8));
319
320 unsigned cu_mask_ps = 0xffffffff;
321
322 /* It's wasteful to enable all CUs for PS if shader arrays have a
323 * different number of CUs. The reason is that the hardware sends the
324 * same number of PS waves to each shader array, so the slowest shader
325 * array limits the performance. Disable the extra CUs for PS in
326 * other shader arrays to save power and thus increase clocks for busy
327 * CUs. In the future, we might disable or enable this tweak only for
328 * certain apps.
329 */
330 if (physical_device->rad_info.gfx_level >= GFX10_3)
331 cu_mask_ps = u_bit_consecutive(0, physical_device->rad_info.min_good_cu_per_sa);
332
333 if (physical_device->rad_info.gfx_level >= GFX7) {
334 if (physical_device->rad_info.gfx_level >= GFX10 && physical_device->rad_info.gfx_level < GFX11) {
335 /* Logical CUs 16 - 31 */
336 radeon_set_sh_reg_idx(physical_device, cs, R_00B104_SPI_SHADER_PGM_RSRC4_VS, 3,
337 ac_apply_cu_en(S_00B104_CU_EN(0xffff), C_00B104_CU_EN, 16, &physical_device->rad_info));
338 }
339
340 if (physical_device->rad_info.gfx_level >= GFX10) {
341 radeon_set_sh_reg_idx(physical_device, cs, R_00B404_SPI_SHADER_PGM_RSRC4_HS, 3,
342 ac_apply_cu_en(S_00B404_CU_EN(0xffff), C_00B404_CU_EN, 16, &physical_device->rad_info));
343 radeon_set_sh_reg_idx(
344 physical_device, cs, R_00B004_SPI_SHADER_PGM_RSRC4_PS, 3,
345 ac_apply_cu_en(S_00B004_CU_EN(cu_mask_ps >> 16), C_00B004_CU_EN, 16, &physical_device->rad_info));
346 }
347
348 if (physical_device->rad_info.gfx_level >= GFX9) {
349 radeon_set_sh_reg_idx(physical_device, cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 3,
350 ac_apply_cu_en(S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F), C_00B41C_CU_EN, 0,
351 &physical_device->rad_info));
352 } else {
353 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
354 ac_apply_cu_en(S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F), C_00B51C_CU_EN, 0,
355 &physical_device->rad_info));
356 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, S_00B41C_WAVE_LIMIT(0x3F));
357 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
358 ac_apply_cu_en(S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F), C_00B31C_CU_EN, 0,
359 &physical_device->rad_info));
360 /* If this is 0, Bonaire can hang even if GS isn't being used.
361 * Other chips are unaffected. These are suboptimal values,
362 * but we don't use on-chip GS.
363 */
364 radeon_set_context_reg(cs, R_028A44_VGT_GS_ONCHIP_CNTL,
365 S_028A44_ES_VERTS_PER_SUBGRP(64) | S_028A44_GS_PRIMS_PER_SUBGRP(4));
366 }
367
368 radeon_set_sh_reg_idx(physical_device, cs, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, 3,
369 ac_apply_cu_en(S_00B01C_CU_EN(cu_mask_ps) | S_00B01C_WAVE_LIMIT(0x3F) |
370 S_00B01C_LDS_GROUP_SIZE(physical_device->rad_info.gfx_level >= GFX11),
371 C_00B01C_CU_EN, 0, &physical_device->rad_info));
372 }
373
374 if (physical_device->rad_info.gfx_level >= GFX10) {
375 /* Break up a pixel wave if it contains deallocs for more than
376 * half the parameter cache.
377 *
378 * To avoid a deadlock where pixel waves aren't launched
379 * because they're waiting for more pixels while the frontend
380 * is stuck waiting for PC space, the maximum allowed value is
381 * the size of the PC minus the largest possible allocation for
382 * a single primitive shader subgroup.
383 */
384 uint32_t max_deallocs_in_wave = physical_device->rad_info.gfx_level >= GFX11 ? 16 : 512;
385 radeon_set_context_reg(cs, R_028C50_PA_SC_NGG_MODE_CNTL, S_028C50_MAX_DEALLOCS_IN_WAVE(max_deallocs_in_wave));
386
387 if (physical_device->rad_info.gfx_level < GFX11)
388 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
389
390 /* Vulkan doesn't support user edge flags and it also doesn't
391 * need to prevent drawing lines on internal edges of
392 * decomposed primitives (such as quads) with polygon mode = lines.
393 */
394 unsigned vertex_reuse_depth = physical_device->rad_info.gfx_level >= GFX10_3 ? 30 : 0;
395 radeon_set_context_reg(cs, R_028838_PA_CL_NGG_CNTL,
396 S_028838_INDEX_BUF_EDGE_FLAG_ENA(0) | S_028838_VERTEX_REUSE_DEPTH(vertex_reuse_depth));
397
398 /* Enable CMASK/FMASK/HTILE/DCC caching in L2 for small chips. */
399 unsigned meta_write_policy, meta_read_policy;
400 unsigned no_alloc =
401 device->physical_device->rad_info.gfx_level >= GFX11 ? V_02807C_CACHE_NOA_GFX11 : V_02807C_CACHE_NOA_GFX10;
402
403 /* TODO: investigate whether LRU improves performance on other chips too */
404 if (physical_device->rad_info.max_render_backends <= 4) {
405 meta_write_policy = V_02807C_CACHE_LRU_WR; /* cache writes */
406 meta_read_policy = V_02807C_CACHE_LRU_RD; /* cache reads */
407 } else {
408 meta_write_policy = V_02807C_CACHE_STREAM; /* write combine */
409 meta_read_policy = no_alloc; /* don't cache reads */
410 }
411
412 radeon_set_context_reg(cs, R_02807C_DB_RMI_L2_CACHE_CONTROL,
413 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM) | S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM) |
414 S_02807C_HTILE_WR_POLICY(meta_write_policy) |
415 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM) | S_02807C_Z_RD_POLICY(no_alloc) |
416 S_02807C_S_RD_POLICY(no_alloc) | S_02807C_HTILE_RD_POLICY(meta_read_policy));
417
418 uint32_t gl2_cc;
419 if (device->physical_device->rad_info.gfx_level >= GFX11) {
420 gl2_cc = S_028410_DCC_WR_POLICY_GFX11(meta_write_policy) |
421 S_028410_COLOR_WR_POLICY_GFX11(V_028410_CACHE_STREAM) |
422 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_GFX11);
423 } else {
424 gl2_cc = S_028410_CMASK_WR_POLICY(meta_write_policy) | S_028410_FMASK_WR_POLICY(V_028410_CACHE_STREAM) |
425 S_028410_DCC_WR_POLICY_GFX10(meta_write_policy) |
426 S_028410_COLOR_WR_POLICY_GFX10(V_028410_CACHE_STREAM) | S_028410_CMASK_RD_POLICY(meta_read_policy) |
427 S_028410_FMASK_RD_POLICY(V_028410_CACHE_NOA_GFX10) |
428 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_GFX10);
429 }
430
431 radeon_set_context_reg(cs, R_028410_CB_RMI_GL2_CACHE_CONTROL, gl2_cc | S_028410_DCC_RD_POLICY(meta_read_policy));
432 radeon_set_context_reg(cs, R_028428_CB_COVERAGE_OUT_CONTROL, 0);
433
434 radeon_set_sh_reg_seq(cs, R_00B0C8_SPI_SHADER_USER_ACCUM_PS_0, 4);
435 radeon_emit(cs, 0); /* R_00B0C8_SPI_SHADER_USER_ACCUM_PS_0 */
436 radeon_emit(cs, 0); /* R_00B0CC_SPI_SHADER_USER_ACCUM_PS_1 */
437 radeon_emit(cs, 0); /* R_00B0D0_SPI_SHADER_USER_ACCUM_PS_2 */
438 radeon_emit(cs, 0); /* R_00B0D4_SPI_SHADER_USER_ACCUM_PS_3 */
439
440 if (physical_device->rad_info.gfx_level < GFX11) {
441 radeon_set_sh_reg_seq(cs, R_00B1C8_SPI_SHADER_USER_ACCUM_VS_0, 4);
442 radeon_emit(cs, 0); /* R_00B1C8_SPI_SHADER_USER_ACCUM_VS_0 */
443 radeon_emit(cs, 0); /* R_00B1CC_SPI_SHADER_USER_ACCUM_VS_1 */
444 radeon_emit(cs, 0); /* R_00B1D0_SPI_SHADER_USER_ACCUM_VS_2 */
445 radeon_emit(cs, 0); /* R_00B1D4_SPI_SHADER_USER_ACCUM_VS_3 */
446 }
447
448 radeon_set_sh_reg_seq(cs, R_00B2C8_SPI_SHADER_USER_ACCUM_ESGS_0, 4);
449 radeon_emit(cs, 0); /* R_00B2C8_SPI_SHADER_USER_ACCUM_ESGS_0 */
450 radeon_emit(cs, 0); /* R_00B2CC_SPI_SHADER_USER_ACCUM_ESGS_1 */
451 radeon_emit(cs, 0); /* R_00B2D0_SPI_SHADER_USER_ACCUM_ESGS_2 */
452 radeon_emit(cs, 0); /* R_00B2D4_SPI_SHADER_USER_ACCUM_ESGS_3 */
453 radeon_set_sh_reg_seq(cs, R_00B4C8_SPI_SHADER_USER_ACCUM_LSHS_0, 4);
454 radeon_emit(cs, 0); /* R_00B4C8_SPI_SHADER_USER_ACCUM_LSHS_0 */
455 radeon_emit(cs, 0); /* R_00B4CC_SPI_SHADER_USER_ACCUM_LSHS_1 */
456 radeon_emit(cs, 0); /* R_00B4D0_SPI_SHADER_USER_ACCUM_LSHS_2 */
457 radeon_emit(cs, 0); /* R_00B4D4_SPI_SHADER_USER_ACCUM_LSHS_3 */
458
459 radeon_set_sh_reg(cs, R_00B0C0_SPI_SHADER_REQ_CTRL_PS,
460 S_00B0C0_SOFT_GROUPING_EN(1) | S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
461
462 if (physical_device->rad_info.gfx_level < GFX11)
463 radeon_set_sh_reg(cs, R_00B1C0_SPI_SHADER_REQ_CTRL_VS, 0);
464
465 if (physical_device->rad_info.gfx_level >= GFX10_3) {
466 radeon_set_context_reg(cs, R_028750_SX_PS_DOWNCONVERT_CONTROL, 0xff);
467 /* This allows sample shading. */
468 radeon_set_context_reg(cs, R_028848_PA_CL_VRS_CNTL,
469 S_028848_SAMPLE_ITER_COMBINER_MODE(V_028848_SC_VRS_COMB_MODE_OVERRIDE));
470 }
471 }
472
473 if (physical_device->rad_info.gfx_level >= GFX11) {
474 /* ACCUM fields changed their meaning. */
475 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
476 S_028B50_ACCUM_ISOLINE(128) | S_028B50_ACCUM_TRI(128) | S_028B50_ACCUM_QUAD(128) |
477 S_028B50_DONUT_SPLIT_GFX9(24) | S_028B50_TRAP_SPLIT(6));
478 } else if (physical_device->rad_info.gfx_level >= GFX9) {
479 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION,
480 S_028B50_ACCUM_ISOLINE(40) | S_028B50_ACCUM_TRI(30) | S_028B50_ACCUM_QUAD(24) |
481 S_028B50_DONUT_SPLIT_GFX9(24) | S_028B50_TRAP_SPLIT(6));
482 } else if (physical_device->rad_info.gfx_level >= GFX8) {
483 uint32_t vgt_tess_distribution;
484
485 vgt_tess_distribution =
486 S_028B50_ACCUM_ISOLINE(32) | S_028B50_ACCUM_TRI(11) | S_028B50_ACCUM_QUAD(11) | S_028B50_DONUT_SPLIT_GFX81(16);
487
488 if (physical_device->rad_info.family == CHIP_FIJI || physical_device->rad_info.family >= CHIP_POLARIS10)
489 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
490
491 radeon_set_context_reg(cs, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
492 } else if (!has_clear_state) {
493 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
494 radeon_set_context_reg(cs, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
495 }
496
497 if (device->border_color_data.bo) {
498 uint64_t border_color_va = radv_buffer_get_va(device->border_color_data.bo);
499
500 radeon_set_context_reg(cs, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
501 if (physical_device->rad_info.gfx_level >= GFX7) {
502 radeon_set_context_reg(cs, R_028084_TA_BC_BASE_ADDR_HI, S_028084_ADDRESS(border_color_va >> 40));
503 }
504 }
505
506 if (physical_device->rad_info.gfx_level >= GFX8) {
507 /* GFX8+ only compares the bits according to the index type by default,
508 * so we can always leave the programmed value at the maximum.
509 */
510 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0xffffffff);
511 }
512
513 if (physical_device->rad_info.gfx_level >= GFX9) {
514 radeon_set_context_reg(cs, R_028C48_PA_SC_BINNER_CNTL_1,
515 S_028C48_MAX_ALLOC_COUNT(physical_device->rad_info.pbb_max_alloc_count - 1) |
516 S_028C48_MAX_PRIM_PER_BATCH(1023));
517 radeon_set_context_reg(cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL, S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
518 radeon_set_uconfig_reg(cs, R_030968_VGT_INSTANCE_BASE_ID, 0);
519 }
520
521 unsigned tmp = (unsigned)(1.0 * 8.0);
522 radeon_set_context_reg(cs, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
523 radeon_set_context_reg(
524 cs, R_028A04_PA_SU_POINT_MINMAX,
525 S_028A04_MIN_SIZE(radv_pack_float_12p4(0)) | S_028A04_MAX_SIZE(radv_pack_float_12p4(8191.875 / 2)));
526
527 if (!has_clear_state) {
528 radeon_set_context_reg(cs, R_028004_DB_COUNT_CONTROL, S_028004_ZPASS_INCREMENT_DISABLE(1));
529 }
530
531 /* Enable the Polaris small primitive filter control.
532 * XXX: There is possibly an issue when MSAA is off (see RadeonSI
533 * has_msaa_sample_loc_bug). But this doesn't seem to regress anything,
534 * and AMDVLK doesn't have a workaround as well.
535 */
536 if (physical_device->rad_info.family >= CHIP_POLARIS10) {
537 unsigned small_prim_filter_cntl =
538 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
539 /* Workaround for a hw line bug. */
540 S_028830_LINE_FILTER_DISABLE(physical_device->rad_info.family <= CHIP_POLARIS12);
541
542 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL, small_prim_filter_cntl);
543 }
544
545 radeon_set_context_reg(cs, R_0286D4_SPI_INTERP_CONTROL_0,
546 S_0286D4_FLAT_SHADE_ENA(1) | S_0286D4_PNT_SPRITE_ENA(1) |
547 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
548 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
549 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
550 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
551 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
552
553 radeon_set_context_reg(cs, R_028BE4_PA_SU_VTX_CNTL,
554 S_028BE4_PIX_CENTER(1) | S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
555 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
556
557 radeon_set_context_reg(cs, R_028818_PA_CL_VTE_CNTL,
558 S_028818_VTX_W0_FMT(1) | S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
559 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
560 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
561
562 if (device->tma_bo) {
563 uint64_t tba_va, tma_va;
564
565 assert(device->physical_device->rad_info.gfx_level == GFX8);
566
567 tba_va = radv_shader_get_va(device->trap_handler_shader);
568 tma_va = radv_buffer_get_va(device->tma_bo);
569
570 uint32_t regs[] = {R_00B000_SPI_SHADER_TBA_LO_PS, R_00B100_SPI_SHADER_TBA_LO_VS, R_00B200_SPI_SHADER_TBA_LO_GS,
571 R_00B300_SPI_SHADER_TBA_LO_ES, R_00B400_SPI_SHADER_TBA_LO_HS, R_00B500_SPI_SHADER_TBA_LO_LS};
572
573 for (i = 0; i < ARRAY_SIZE(regs); ++i) {
574 radeon_set_sh_reg_seq(cs, regs[i], 4);
575 radeon_emit(cs, tba_va >> 8);
576 radeon_emit(cs, tba_va >> 40);
577 radeon_emit(cs, tma_va >> 8);
578 radeon_emit(cs, tma_va >> 40);
579 }
580 }
581
582 if (physical_device->rad_info.gfx_level >= GFX11) {
583 radeon_set_context_reg(cs, R_028C54_PA_SC_BINNER_CNTL_2,
584 S_028C54_ENABLE_PING_PONG_BIN_ORDER(physical_device->rad_info.gfx_level >= GFX11_5));
585
586 uint64_t rb_mask = BITFIELD64_MASK(physical_device->rad_info.max_render_backends);
587
588 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
589 radeon_emit(cs, EVENT_TYPE(V_028A90_PIXEL_PIPE_STAT_CONTROL) | EVENT_INDEX(1));
590 radeon_emit(cs, PIXEL_PIPE_STATE_CNTL_COUNTER_ID(0) | PIXEL_PIPE_STATE_CNTL_STRIDE(2) |
591 PIXEL_PIPE_STATE_CNTL_INSTANCE_EN_LO(rb_mask));
592 radeon_emit(cs, PIXEL_PIPE_STATE_CNTL_INSTANCE_EN_HI(rb_mask));
593
594 radeon_set_uconfig_reg(cs, R_031110_SPI_GS_THROTTLE_CNTL1, 0x12355123);
595 radeon_set_uconfig_reg(cs, R_031114_SPI_GS_THROTTLE_CNTL2, 0x1544D);
596 }
597
598 /* The exclusion bits can be set to improve rasterization efficiency if no sample lies on the
599 * pixel boundary (-8 sample offset). It's currently always TRUE because the driver doesn't
600 * support 16 samples.
601 */
602 bool exclusion = physical_device->rad_info.gfx_level >= GFX7;
603 radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
604 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) | S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
605
606 radeon_set_context_reg(cs, R_028828_PA_SU_LINE_STIPPLE_SCALE, 0x3f800000);
607 if (physical_device->rad_info.gfx_level >= GFX7) {
608 radeon_set_uconfig_reg(cs, R_030A00_PA_SU_LINE_STIPPLE_VALUE, 0);
609 radeon_set_uconfig_reg(cs, R_030A04_PA_SC_LINE_STIPPLE_STATE, 0);
610 } else {
611 radeon_set_config_reg(cs, R_008A60_PA_SU_LINE_STIPPLE_VALUE, 0);
612 radeon_set_config_reg(cs, R_008B10_PA_SC_LINE_STIPPLE_STATE, 0);
613 }
614
615 if (physical_device->rad_info.gfx_level >= GFX11) {
616 /* Disable primitive restart for all non-indexed draws. */
617 radeon_set_uconfig_reg(cs, R_03092C_GE_MULTI_PRIM_IB_RESET_EN, S_03092C_DISABLE_FOR_AUTO_INDEX(1));
618 }
619
620 radv_emit_compute(device, cs);
621 }
622
623 void
radv_create_gfx_config(struct radv_device * device)624 radv_create_gfx_config(struct radv_device *device)
625 {
626 struct radeon_cmdbuf *cs = device->ws->cs_create(device->ws, AMD_IP_GFX, false);
627 if (!cs)
628 return;
629
630 radeon_check_space(device->ws, cs, 512);
631
632 radv_emit_graphics(device, cs);
633
634 while (cs->cdw & 7) {
635 if (device->physical_device->rad_info.gfx_ib_pad_with_type2)
636 radeon_emit(cs, PKT2_NOP_PAD);
637 else
638 radeon_emit(cs, PKT3_NOP_PAD);
639 }
640
641 VkResult result = device->ws->buffer_create(
642 device->ws, cs->cdw * 4, 4096, device->ws->cs_domain(device->ws),
643 RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING | RADEON_FLAG_READ_ONLY | RADEON_FLAG_GTT_WC,
644 RADV_BO_PRIORITY_CS, 0, &device->gfx_init);
645 if (result != VK_SUCCESS)
646 goto fail;
647
648 void *map = device->ws->buffer_map(device->gfx_init);
649 if (!map) {
650 device->ws->buffer_destroy(device->ws, device->gfx_init);
651 device->gfx_init = NULL;
652 goto fail;
653 }
654 memcpy(map, cs->buf, cs->cdw * 4);
655
656 device->ws->buffer_unmap(device->gfx_init);
657 device->gfx_init_size_dw = cs->cdw;
658 fail:
659 device->ws->cs_destroy(cs);
660 }
661
662 void
radv_get_viewport_xform(const VkViewport * viewport,float scale[3],float translate[3])663 radv_get_viewport_xform(const VkViewport *viewport, float scale[3], float translate[3])
664 {
665 float x = viewport->x;
666 float y = viewport->y;
667 float half_width = 0.5f * viewport->width;
668 float half_height = 0.5f * viewport->height;
669 double n = viewport->minDepth;
670 double f = viewport->maxDepth;
671
672 scale[0] = half_width;
673 translate[0] = half_width + x;
674 scale[1] = half_height;
675 translate[1] = half_height + y;
676
677 scale[2] = (f - n);
678 translate[2] = n;
679 }
680
681 static VkRect2D
radv_scissor_from_viewport(const VkViewport * viewport)682 radv_scissor_from_viewport(const VkViewport *viewport)
683 {
684 float scale[3], translate[3];
685 VkRect2D rect;
686
687 radv_get_viewport_xform(viewport, scale, translate);
688
689 rect.offset.x = translate[0] - fabsf(scale[0]);
690 rect.offset.y = translate[1] - fabsf(scale[1]);
691 rect.extent.width = ceilf(translate[0] + fabsf(scale[0])) - rect.offset.x;
692 rect.extent.height = ceilf(translate[1] + fabsf(scale[1])) - rect.offset.y;
693
694 return rect;
695 }
696
697 static VkRect2D
radv_intersect_scissor(const VkRect2D * a,const VkRect2D * b)698 radv_intersect_scissor(const VkRect2D *a, const VkRect2D *b)
699 {
700 VkRect2D ret;
701 ret.offset.x = MAX2(a->offset.x, b->offset.x);
702 ret.offset.y = MAX2(a->offset.y, b->offset.y);
703 ret.extent.width = MIN2(a->offset.x + a->extent.width, b->offset.x + b->extent.width) - ret.offset.x;
704 ret.extent.height = MIN2(a->offset.y + a->extent.height, b->offset.y + b->extent.height) - ret.offset.y;
705 return ret;
706 }
707
708 void
radv_write_scissors(struct radeon_cmdbuf * cs,int count,const VkRect2D * scissors,const VkViewport * viewports)709 radv_write_scissors(struct radeon_cmdbuf *cs, int count, const VkRect2D *scissors, const VkViewport *viewports)
710 {
711 int i;
712
713 if (!count)
714 return;
715
716 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, count * 2);
717 for (i = 0; i < count; i++) {
718 VkRect2D viewport_scissor = radv_scissor_from_viewport(viewports + i);
719 VkRect2D scissor = radv_intersect_scissor(&scissors[i], &viewport_scissor);
720
721 radeon_emit(
722 cs, S_028250_TL_X(scissor.offset.x) | S_028250_TL_Y(scissor.offset.y) | S_028250_WINDOW_OFFSET_DISABLE(1));
723 radeon_emit(cs, S_028254_BR_X(scissor.offset.x + scissor.extent.width) |
724 S_028254_BR_Y(scissor.offset.y + scissor.extent.height));
725 }
726 }
727
728 void
radv_write_guardband(struct radeon_cmdbuf * cs,int count,const VkViewport * viewports,unsigned rast_prim,unsigned polygon_mode,float line_width)729 radv_write_guardband(struct radeon_cmdbuf *cs, int count, const VkViewport *viewports, unsigned rast_prim,
730 unsigned polygon_mode, float line_width)
731 {
732 const bool draw_points = radv_rast_prim_is_point(rast_prim) || radv_polygon_mode_is_point(polygon_mode);
733 const bool draw_lines = radv_rast_prim_is_line(rast_prim) || radv_polygon_mode_is_line(polygon_mode);
734 int i;
735 float scale[3], translate[3], guardband_x = INFINITY, guardband_y = INFINITY;
736 float discard_x = 1.0f, discard_y = 1.0f;
737 const float max_range = 32767.0f;
738 if (!count)
739 return;
740
741 for (i = 0; i < count; i++) {
742 radv_get_viewport_xform(viewports + i, scale, translate);
743 scale[0] = fabsf(scale[0]);
744 scale[1] = fabsf(scale[1]);
745
746 if (scale[0] < 0.5)
747 scale[0] = 0.5;
748 if (scale[1] < 0.5)
749 scale[1] = 0.5;
750
751 guardband_x = MIN2(guardband_x, (max_range - fabsf(translate[0])) / scale[0]);
752 guardband_y = MIN2(guardband_y, (max_range - fabsf(translate[1])) / scale[1]);
753
754 if (draw_points || draw_lines) {
755 /* When rendering wide points or lines, we need to be more conservative about when to
756 * discard them entirely. */
757 float pixels;
758
759 if (draw_points) {
760 pixels = 8191.875f;
761 } else {
762 pixels = line_width;
763 }
764
765 /* Add half the point size / line width. */
766 discard_x += pixels / (2.0 * scale[0]);
767 discard_y += pixels / (2.0 * scale[1]);
768
769 /* Discard primitives that would lie entirely outside the clip region. */
770 discard_x = MIN2(discard_x, guardband_x);
771 discard_y = MIN2(discard_y, guardband_y);
772 }
773 }
774
775 radeon_set_context_reg_seq(cs, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
776 radeon_emit(cs, fui(guardband_y));
777 radeon_emit(cs, fui(discard_y));
778 radeon_emit(cs, fui(guardband_x));
779 radeon_emit(cs, fui(discard_x));
780 }
781
782 static inline unsigned
radv_prims_for_vertices(struct radv_prim_vertex_count * info,unsigned num)783 radv_prims_for_vertices(struct radv_prim_vertex_count *info, unsigned num)
784 {
785 if (num == 0)
786 return 0;
787
788 if (info->incr == 0)
789 return 0;
790
791 if (num < info->min)
792 return 0;
793
794 return 1 + ((num - info->min) / info->incr);
795 }
796
797 static const struct radv_prim_vertex_count prim_size_table[] = {
798 [V_008958_DI_PT_NONE] = {0, 0}, [V_008958_DI_PT_POINTLIST] = {1, 1},
799 [V_008958_DI_PT_LINELIST] = {2, 2}, [V_008958_DI_PT_LINESTRIP] = {2, 1},
800 [V_008958_DI_PT_TRILIST] = {3, 3}, [V_008958_DI_PT_TRIFAN] = {3, 1},
801 [V_008958_DI_PT_TRISTRIP] = {3, 1}, [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
802 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1}, [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
803 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2}, [V_008958_DI_PT_RECTLIST] = {3, 3},
804 [V_008958_DI_PT_LINELOOP] = {2, 1}, [V_008958_DI_PT_POLYGON] = {3, 1},
805 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
806 };
807
808 uint32_t
radv_get_ia_multi_vgt_param(struct radv_cmd_buffer * cmd_buffer,bool instanced_draw,bool indirect_draw,bool count_from_stream_output,uint32_t draw_vertex_count,unsigned topology,bool prim_restart_enable,unsigned patch_control_points,unsigned num_tess_patches)809 radv_get_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, bool instanced_draw, bool indirect_draw,
810 bool count_from_stream_output, uint32_t draw_vertex_count, unsigned topology,
811 bool prim_restart_enable, unsigned patch_control_points, unsigned num_tess_patches)
812 {
813 const struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;
814 const unsigned max_primgroup_in_wave = 2;
815 /* SWITCH_ON_EOP(0) is always preferable. */
816 bool wd_switch_on_eop = false;
817 bool ia_switch_on_eop = false;
818 bool ia_switch_on_eoi = false;
819 bool partial_vs_wave = false;
820 bool partial_es_wave = cmd_buffer->state.ia_multi_vgt_param.partial_es_wave;
821 bool multi_instances_smaller_than_primgroup;
822 struct radv_prim_vertex_count prim_vertex_count = prim_size_table[topology];
823 unsigned primgroup_size;
824
825 if (radv_cmdbuf_has_stage(cmd_buffer, MESA_SHADER_TESS_CTRL)) {
826 primgroup_size = num_tess_patches;
827 } else if (radv_cmdbuf_has_stage(cmd_buffer, MESA_SHADER_GEOMETRY)) {
828 primgroup_size = 64;
829 } else {
830 primgroup_size = 128; /* recommended without a GS */
831 }
832
833 /* GS requirement. */
834 if (radv_cmdbuf_has_stage(cmd_buffer, MESA_SHADER_GEOMETRY) && info->gfx_level <= GFX8) {
835 unsigned gs_table_depth = cmd_buffer->device->physical_device->gs_table_depth;
836 if (SI_GS_PER_ES / primgroup_size >= gs_table_depth - 3)
837 partial_es_wave = true;
838 }
839
840 if (radv_cmdbuf_has_stage(cmd_buffer, MESA_SHADER_TESS_CTRL)) {
841 if (topology == V_008958_DI_PT_PATCH) {
842 prim_vertex_count.min = patch_control_points;
843 prim_vertex_count.incr = 1;
844 }
845 }
846
847 multi_instances_smaller_than_primgroup = indirect_draw;
848 if (!multi_instances_smaller_than_primgroup && instanced_draw) {
849 uint32_t num_prims = radv_prims_for_vertices(&prim_vertex_count, draw_vertex_count);
850 if (num_prims < primgroup_size)
851 multi_instances_smaller_than_primgroup = true;
852 }
853
854 ia_switch_on_eoi = cmd_buffer->state.ia_multi_vgt_param.ia_switch_on_eoi;
855 partial_vs_wave = cmd_buffer->state.ia_multi_vgt_param.partial_vs_wave;
856
857 if (info->gfx_level >= GFX7) {
858 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
859 * 4 shader engines. Set 1 to pass the assertion below.
860 * The other cases are hardware requirements. */
861 if (info->max_se < 4 || topology == V_008958_DI_PT_POLYGON || topology == V_008958_DI_PT_LINELOOP ||
862 topology == V_008958_DI_PT_TRIFAN || topology == V_008958_DI_PT_TRISTRIP_ADJ ||
863 (prim_restart_enable && (info->family < CHIP_POLARIS10 ||
864 (topology != V_008958_DI_PT_POINTLIST && topology != V_008958_DI_PT_LINESTRIP))))
865 wd_switch_on_eop = true;
866
867 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
868 * We don't know that for indirect drawing, so treat it as
869 * always problematic. */
870 if (info->family == CHIP_HAWAII && (instanced_draw || indirect_draw))
871 wd_switch_on_eop = true;
872
873 /* Performance recommendation for 4 SE Gfx7-8 parts if
874 * instances are smaller than a primgroup.
875 * Assume indirect draws always use small instances.
876 * This is needed for good VS wave utilization.
877 */
878 if (info->gfx_level <= GFX8 && info->max_se == 4 && multi_instances_smaller_than_primgroup)
879 wd_switch_on_eop = true;
880
881 /* Hardware requirement when drawing primitives from a stream
882 * output buffer.
883 */
884 if (count_from_stream_output)
885 wd_switch_on_eop = true;
886
887 /* Required on GFX7 and later. */
888 if (info->max_se > 2 && !wd_switch_on_eop)
889 ia_switch_on_eoi = true;
890
891 /* Required by Hawaii and, for some special cases, by GFX8. */
892 if (ia_switch_on_eoi &&
893 (info->family == CHIP_HAWAII ||
894 (info->gfx_level == GFX8 &&
895 /* max primgroup in wave is always 2 - leave this for documentation */
896 (radv_cmdbuf_has_stage(cmd_buffer, MESA_SHADER_GEOMETRY) || max_primgroup_in_wave != 2))))
897 partial_vs_wave = true;
898
899 /* Instancing bug on Bonaire. */
900 if (info->family == CHIP_BONAIRE && ia_switch_on_eoi && (instanced_draw || indirect_draw))
901 partial_vs_wave = true;
902
903 /* If the WD switch is false, the IA switch must be false too. */
904 assert(wd_switch_on_eop || !ia_switch_on_eop);
905 }
906 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
907 if (info->gfx_level <= GFX8 && ia_switch_on_eoi)
908 partial_es_wave = true;
909
910 if (radv_cmdbuf_has_stage(cmd_buffer, MESA_SHADER_GEOMETRY)) {
911 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
912 * The hw doc says all multi-SE chips are affected, but amdgpu-pro Vulkan
913 * only applies it to Hawaii. Do what amdgpu-pro Vulkan does.
914 */
915 if (info->family == CHIP_HAWAII && ia_switch_on_eoi) {
916 bool set_vgt_flush = indirect_draw;
917 if (!set_vgt_flush && instanced_draw) {
918 uint32_t num_prims = radv_prims_for_vertices(&prim_vertex_count, draw_vertex_count);
919 if (num_prims <= 1)
920 set_vgt_flush = true;
921 }
922 if (set_vgt_flush)
923 cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;
924 }
925 }
926
927 /* Workaround for a VGT hang when strip primitive types are used with
928 * primitive restart.
929 */
930 if (prim_restart_enable && (topology == V_008958_DI_PT_LINESTRIP || topology == V_008958_DI_PT_TRISTRIP ||
931 topology == V_008958_DI_PT_LINESTRIP_ADJ || topology == V_008958_DI_PT_TRISTRIP_ADJ)) {
932 partial_vs_wave = true;
933 }
934
935 return cmd_buffer->state.ia_multi_vgt_param.base | S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
936 S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) | S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
937 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) | S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
938 S_028AA8_WD_SWITCH_ON_EOP(info->gfx_level >= GFX7 ? wd_switch_on_eop : 0);
939 }
940
941 void
radv_cs_emit_write_event_eop(struct radeon_cmdbuf * cs,enum amd_gfx_level gfx_level,enum radv_queue_family qf,unsigned event,unsigned event_flags,unsigned dst_sel,unsigned data_sel,uint64_t va,uint32_t new_fence,uint64_t gfx9_eop_bug_va)942 radv_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, enum radv_queue_family qf,
943 unsigned event, unsigned event_flags, unsigned dst_sel, unsigned data_sel, uint64_t va,
944 uint32_t new_fence, uint64_t gfx9_eop_bug_va)
945 {
946 if (qf == RADV_QUEUE_TRANSFER) {
947 radeon_emit(cs, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, SDMA_FENCE_MTYPE_UC));
948 radeon_emit(cs, va);
949 radeon_emit(cs, va >> 32);
950 radeon_emit(cs, new_fence);
951 return;
952 }
953
954 const bool is_mec = qf == RADV_QUEUE_COMPUTE && gfx_level >= GFX7;
955 unsigned op =
956 EVENT_TYPE(event) | EVENT_INDEX(event == V_028A90_CS_DONE || event == V_028A90_PS_DONE ? 6 : 5) | event_flags;
957 unsigned is_gfx8_mec = is_mec && gfx_level < GFX9;
958 unsigned sel = EOP_DST_SEL(dst_sel) | EOP_DATA_SEL(data_sel);
959
960 /* Wait for write confirmation before writing data, but don't send
961 * an interrupt. */
962 if (data_sel != EOP_DATA_SEL_DISCARD)
963 sel |= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM);
964
965 if (gfx_level >= GFX9 || is_gfx8_mec) {
966 /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion
967 * counters) must immediately precede every timestamp event to
968 * prevent a GPU hang on GFX9.
969 */
970 if (gfx_level == GFX9 && !is_mec) {
971 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
972 radeon_emit(cs, EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1));
973 radeon_emit(cs, gfx9_eop_bug_va);
974 radeon_emit(cs, gfx9_eop_bug_va >> 32);
975 }
976
977 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, false));
978 radeon_emit(cs, op);
979 radeon_emit(cs, sel);
980 radeon_emit(cs, va); /* address lo */
981 radeon_emit(cs, va >> 32); /* address hi */
982 radeon_emit(cs, new_fence); /* immediate data lo */
983 radeon_emit(cs, 0); /* immediate data hi */
984 if (!is_gfx8_mec)
985 radeon_emit(cs, 0); /* unused */
986 } else {
987 /* On GFX6, EOS events are always emitted with EVENT_WRITE_EOS.
988 * On GFX7+, EOS events are emitted with EVENT_WRITE_EOS on
989 * the graphics queue, and with RELEASE_MEM on the compute
990 * queue.
991 */
992 if (event == V_028B9C_CS_DONE || event == V_028B9C_PS_DONE) {
993 assert(event_flags == 0 && dst_sel == EOP_DST_SEL_MEM && data_sel == EOP_DATA_SEL_VALUE_32BIT);
994
995 if (is_mec) {
996 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, 5, false));
997 radeon_emit(cs, op);
998 radeon_emit(cs, sel);
999 radeon_emit(cs, va); /* address lo */
1000 radeon_emit(cs, va >> 32); /* address hi */
1001 radeon_emit(cs, new_fence); /* immediate data lo */
1002 radeon_emit(cs, 0); /* immediate data hi */
1003 } else {
1004 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOS, 3, false));
1005 radeon_emit(cs, op);
1006 radeon_emit(cs, va);
1007 radeon_emit(cs, ((va >> 32) & 0xffff) | EOS_DATA_SEL(EOS_DATA_SEL_VALUE_32BIT));
1008 radeon_emit(cs, new_fence);
1009 }
1010 } else {
1011 if (gfx_level == GFX7 || gfx_level == GFX8) {
1012 /* Two EOP events are required to make all
1013 * engines go idle (and optional cache flushes
1014 * executed) before the timestamp is written.
1015 */
1016 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
1017 radeon_emit(cs, op);
1018 radeon_emit(cs, va);
1019 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
1020 radeon_emit(cs, 0); /* immediate data */
1021 radeon_emit(cs, 0); /* unused */
1022 }
1023
1024 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false));
1025 radeon_emit(cs, op);
1026 radeon_emit(cs, va);
1027 radeon_emit(cs, ((va >> 32) & 0xffff) | sel);
1028 radeon_emit(cs, new_fence); /* immediate data */
1029 radeon_emit(cs, 0); /* unused */
1030 }
1031 }
1032 }
1033
1034 static void
radv_emit_acquire_mem(struct radeon_cmdbuf * cs,bool is_mec,bool is_gfx9,unsigned cp_coher_cntl)1035 radv_emit_acquire_mem(struct radeon_cmdbuf *cs, bool is_mec, bool is_gfx9, unsigned cp_coher_cntl)
1036 {
1037 if (is_mec || is_gfx9) {
1038 uint32_t hi_val = is_gfx9 ? 0xffffff : 0xff;
1039 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, false) | PKT3_SHADER_TYPE_S(is_mec));
1040 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
1041 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1042 radeon_emit(cs, hi_val); /* CP_COHER_SIZE_HI */
1043 radeon_emit(cs, 0); /* CP_COHER_BASE */
1044 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
1045 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1046 } else {
1047 /* ACQUIRE_MEM is only required on a compute ring. */
1048 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, false));
1049 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
1050 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1051 radeon_emit(cs, 0); /* CP_COHER_BASE */
1052 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1053 }
1054 }
1055
1056 static void
gfx10_cs_emit_cache_flush(struct radeon_cmdbuf * cs,enum amd_gfx_level gfx_level,uint32_t * flush_cnt,uint64_t flush_va,enum radv_queue_family qf,enum radv_cmd_flush_bits flush_bits,enum rgp_flush_bits * sqtt_flush_bits,uint64_t gfx9_eop_bug_va)1057 gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, uint32_t *flush_cnt,
1058 uint64_t flush_va, enum radv_queue_family qf, enum radv_cmd_flush_bits flush_bits,
1059 enum rgp_flush_bits *sqtt_flush_bits, uint64_t gfx9_eop_bug_va)
1060 {
1061 const bool is_mec = qf == RADV_QUEUE_COMPUTE;
1062 uint32_t gcr_cntl = 0;
1063 unsigned cb_db_event = 0;
1064
1065 /* We don't need these. */
1066 assert(!(flush_bits & (RADV_CMD_FLAG_VGT_STREAMOUT_SYNC)));
1067
1068 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE) {
1069 gcr_cntl |= S_586_GLI_INV(V_586_GLI_ALL);
1070
1071 *sqtt_flush_bits |= RGP_FLUSH_INVAL_ICACHE;
1072 }
1073 if (flush_bits & RADV_CMD_FLAG_INV_SCACHE) {
1074 /* TODO: When writing to the SMEM L1 cache, we need to set SEQ
1075 * to FORWARD when both L1 and L2 are written out (WB or INV).
1076 */
1077 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLK_INV(1);
1078
1079 *sqtt_flush_bits |= RGP_FLUSH_INVAL_SMEM_L0;
1080 }
1081 if (flush_bits & RADV_CMD_FLAG_INV_VCACHE) {
1082 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLV_INV(1);
1083
1084 *sqtt_flush_bits |= RGP_FLUSH_INVAL_VMEM_L0 | RGP_FLUSH_INVAL_L1;
1085 }
1086 if (flush_bits & RADV_CMD_FLAG_INV_L2) {
1087 /* Writeback and invalidate everything in L2. */
1088 gcr_cntl |= S_586_GL2_INV(1) | S_586_GL2_WB(1) | S_586_GLM_INV(1) | S_586_GLM_WB(1);
1089
1090 *sqtt_flush_bits |= RGP_FLUSH_INVAL_L2;
1091 } else if (flush_bits & RADV_CMD_FLAG_WB_L2) {
1092 /* Writeback but do not invalidate.
1093 * GLM doesn't support WB alone. If WB is set, INV must be set too.
1094 */
1095 gcr_cntl |= S_586_GL2_WB(1) | S_586_GLM_WB(1) | S_586_GLM_INV(1);
1096
1097 *sqtt_flush_bits |= RGP_FLUSH_FLUSH_L2;
1098 } else if (flush_bits & RADV_CMD_FLAG_INV_L2_METADATA) {
1099 gcr_cntl |= S_586_GLM_INV(1) | S_586_GLM_WB(1);
1100 }
1101
1102 if (flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) {
1103 /* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_CB_META */
1104 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
1105 /* Flush CMASK/FMASK/DCC. Will wait for idle later. */
1106 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1107 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
1108
1109 *sqtt_flush_bits |= RGP_FLUSH_FLUSH_CB | RGP_FLUSH_INVAL_CB;
1110 }
1111
1112 /* TODO: trigger on RADV_CMD_FLAG_FLUSH_AND_INV_DB_META ? */
1113 if (gfx_level < GFX11 && (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB)) {
1114 /* Flush HTILE. Will wait for idle later. */
1115 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1116 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
1117
1118 *sqtt_flush_bits |= RGP_FLUSH_FLUSH_DB | RGP_FLUSH_INVAL_DB;
1119 }
1120
1121 /* First flush CB/DB, then L1/L2. */
1122 gcr_cntl |= S_586_SEQ(V_586_SEQ_FORWARD);
1123
1124 if ((flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) ==
1125 (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB)) {
1126 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1127 } else if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
1128 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
1129 } else if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
1130 if (gfx_level == GFX11) {
1131 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1132 } else {
1133 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
1134 }
1135 } else {
1136 assert(0);
1137 }
1138 } else {
1139 /* Wait for graphics shaders to go idle if requested. */
1140 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
1141 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1142 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1143
1144 *sqtt_flush_bits |= RGP_FLUSH_PS_PARTIAL_FLUSH;
1145 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
1146 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1147 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1148
1149 *sqtt_flush_bits |= RGP_FLUSH_VS_PARTIAL_FLUSH;
1150 }
1151 }
1152
1153 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
1154 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1155 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
1156
1157 *sqtt_flush_bits |= RGP_FLUSH_CS_PARTIAL_FLUSH;
1158 }
1159
1160 if (cb_db_event) {
1161 if (gfx_level >= GFX11) {
1162 /* Get GCR_CNTL fields, because the encoding is different in RELEASE_MEM. */
1163 unsigned glm_wb = G_586_GLM_WB(gcr_cntl);
1164 unsigned glm_inv = G_586_GLM_INV(gcr_cntl);
1165 unsigned glk_wb = G_586_GLK_WB(gcr_cntl);
1166 unsigned glk_inv = G_586_GLK_INV(gcr_cntl);
1167 unsigned glv_inv = G_586_GLV_INV(gcr_cntl);
1168 unsigned gl1_inv = G_586_GL1_INV(gcr_cntl);
1169 assert(G_586_GL2_US(gcr_cntl) == 0);
1170 assert(G_586_GL2_RANGE(gcr_cntl) == 0);
1171 assert(G_586_GL2_DISCARD(gcr_cntl) == 0);
1172 unsigned gl2_inv = G_586_GL2_INV(gcr_cntl);
1173 unsigned gl2_wb = G_586_GL2_WB(gcr_cntl);
1174 unsigned gcr_seq = G_586_SEQ(gcr_cntl);
1175
1176 gcr_cntl &= C_586_GLM_WB & C_586_GLM_INV & C_586_GLK_WB & C_586_GLK_INV & C_586_GLV_INV & C_586_GL1_INV &
1177 C_586_GL2_INV & C_586_GL2_WB; /* keep SEQ */
1178
1179 /* Send an event that flushes caches. */
1180 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, 6, 0));
1181 radeon_emit(cs, S_490_EVENT_TYPE(cb_db_event) | S_490_EVENT_INDEX(5) | S_490_GLM_WB(glm_wb) |
1182 S_490_GLM_INV(glm_inv) | S_490_GLV_INV(glv_inv) | S_490_GL1_INV(gl1_inv) |
1183 S_490_GL2_INV(gl2_inv) | S_490_GL2_WB(gl2_wb) | S_490_SEQ(gcr_seq) | S_490_GLK_WB(glk_wb) |
1184 S_490_GLK_INV(glk_inv) | S_490_PWS_ENABLE(1));
1185 radeon_emit(cs, 0); /* DST_SEL, INT_SEL, DATA_SEL */
1186 radeon_emit(cs, 0); /* ADDRESS_LO */
1187 radeon_emit(cs, 0); /* ADDRESS_HI */
1188 radeon_emit(cs, 0); /* DATA_LO */
1189 radeon_emit(cs, 0); /* DATA_HI */
1190 radeon_emit(cs, 0); /* INT_CTXID */
1191
1192 /* Wait for the event and invalidate remaining caches if needed. */
1193 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 6, 0));
1194 radeon_emit(cs, S_580_PWS_STAGE_SEL(V_580_CP_PFP) | S_580_PWS_COUNTER_SEL(V_580_TS_SELECT) |
1195 S_580_PWS_ENA2(1) | S_580_PWS_COUNT(0));
1196 radeon_emit(cs, 0xffffffff); /* GCR_SIZE */
1197 radeon_emit(cs, 0x01ffffff); /* GCR_SIZE_HI */
1198 radeon_emit(cs, 0); /* GCR_BASE_LO */
1199 radeon_emit(cs, 0); /* GCR_BASE_HI */
1200 radeon_emit(cs, S_585_PWS_ENA(1));
1201 radeon_emit(cs, gcr_cntl); /* GCR_CNTL */
1202
1203 gcr_cntl = 0; /* all done */
1204 } else {
1205 /* CB/DB flush and invalidate (or possibly just a wait for a
1206 * meta flush) via RELEASE_MEM.
1207 *
1208 * Combine this with other cache flushes when possible; this
1209 * requires affected shaders to be idle, so do it after the
1210 * CS_PARTIAL_FLUSH before (VS/PS partial flushes are always
1211 * implied).
1212 */
1213 /* Get GCR_CNTL fields, because the encoding is different in RELEASE_MEM. */
1214 unsigned glm_wb = G_586_GLM_WB(gcr_cntl);
1215 unsigned glm_inv = G_586_GLM_INV(gcr_cntl);
1216 unsigned glv_inv = G_586_GLV_INV(gcr_cntl);
1217 unsigned gl1_inv = G_586_GL1_INV(gcr_cntl);
1218 assert(G_586_GL2_US(gcr_cntl) == 0);
1219 assert(G_586_GL2_RANGE(gcr_cntl) == 0);
1220 assert(G_586_GL2_DISCARD(gcr_cntl) == 0);
1221 unsigned gl2_inv = G_586_GL2_INV(gcr_cntl);
1222 unsigned gl2_wb = G_586_GL2_WB(gcr_cntl);
1223 unsigned gcr_seq = G_586_SEQ(gcr_cntl);
1224
1225 gcr_cntl &=
1226 C_586_GLM_WB & C_586_GLM_INV & C_586_GLV_INV & C_586_GL1_INV & C_586_GL2_INV & C_586_GL2_WB; /* keep SEQ */
1227
1228 assert(flush_cnt);
1229 (*flush_cnt)++;
1230
1231 radv_cs_emit_write_event_eop(cs, gfx_level, qf, cb_db_event,
1232 S_490_GLM_WB(glm_wb) | S_490_GLM_INV(glm_inv) | S_490_GLV_INV(glv_inv) |
1233 S_490_GL1_INV(gl1_inv) | S_490_GL2_INV(gl2_inv) | S_490_GL2_WB(gl2_wb) |
1234 S_490_SEQ(gcr_seq),
1235 EOP_DST_SEL_MEM, EOP_DATA_SEL_VALUE_32BIT, flush_va, *flush_cnt, gfx9_eop_bug_va);
1236
1237 radv_cp_wait_mem(cs, qf, WAIT_REG_MEM_EQUAL, flush_va, *flush_cnt, 0xffffffff);
1238 }
1239 }
1240
1241 /* VGT state sync */
1242 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
1243 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1244 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1245 }
1246
1247 /* Ignore fields that only modify the behavior of other fields. */
1248 if (gcr_cntl & C_586_GL1_RANGE & C_586_GL2_RANGE & C_586_SEQ) {
1249 /* Flush caches and wait for the caches to assert idle.
1250 * The cache flush is executed in the ME, but the PFP waits
1251 * for completion.
1252 */
1253 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 6, 0));
1254 radeon_emit(cs, 0); /* CP_COHER_CNTL */
1255 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1256 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
1257 radeon_emit(cs, 0); /* CP_COHER_BASE */
1258 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
1259 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1260 radeon_emit(cs, gcr_cntl); /* GCR_CNTL */
1261 } else if ((cb_db_event || (flush_bits & (RADV_CMD_FLAG_VS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1262 RADV_CMD_FLAG_CS_PARTIAL_FLUSH))) &&
1263 !is_mec) {
1264 /* We need to ensure that PFP waits as well. */
1265 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1266 radeon_emit(cs, 0);
1267
1268 *sqtt_flush_bits |= RGP_FLUSH_PFP_SYNC_ME;
1269 }
1270
1271 if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) {
1272 if (qf == RADV_QUEUE_GENERAL) {
1273 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1274 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) | EVENT_INDEX(0));
1275 } else if (qf == RADV_QUEUE_COMPUTE) {
1276 radeon_set_sh_reg(cs, R_00B828_COMPUTE_PIPELINESTAT_ENABLE, S_00B828_PIPELINESTAT_ENABLE(1));
1277 }
1278 } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) {
1279 if (qf == RADV_QUEUE_GENERAL) {
1280 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1281 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) | EVENT_INDEX(0));
1282 } else if (qf == RADV_QUEUE_COMPUTE) {
1283 radeon_set_sh_reg(cs, R_00B828_COMPUTE_PIPELINESTAT_ENABLE, S_00B828_PIPELINESTAT_ENABLE(0));
1284 }
1285 }
1286 }
1287
1288 void
radv_cs_emit_cache_flush(struct radeon_winsys * ws,struct radeon_cmdbuf * cs,enum amd_gfx_level gfx_level,uint32_t * flush_cnt,uint64_t flush_va,enum radv_queue_family qf,enum radv_cmd_flush_bits flush_bits,enum rgp_flush_bits * sqtt_flush_bits,uint64_t gfx9_eop_bug_va)1289 radv_cs_emit_cache_flush(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level,
1290 uint32_t *flush_cnt, uint64_t flush_va, enum radv_queue_family qf,
1291 enum radv_cmd_flush_bits flush_bits, enum rgp_flush_bits *sqtt_flush_bits,
1292 uint64_t gfx9_eop_bug_va)
1293 {
1294 unsigned cp_coher_cntl = 0;
1295 uint32_t flush_cb_db = flush_bits & (RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_DB);
1296
1297 radeon_check_space(ws, cs, 128);
1298
1299 if (gfx_level >= GFX10) {
1300 /* GFX10 cache flush handling is quite different. */
1301 gfx10_cs_emit_cache_flush(cs, gfx_level, flush_cnt, flush_va, qf, flush_bits, sqtt_flush_bits, gfx9_eop_bug_va);
1302 return;
1303 }
1304
1305 const bool is_mec = qf == RADV_QUEUE_COMPUTE && gfx_level >= GFX7;
1306
1307 if (flush_bits & RADV_CMD_FLAG_INV_ICACHE) {
1308 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
1309 *sqtt_flush_bits |= RGP_FLUSH_INVAL_ICACHE;
1310 }
1311 if (flush_bits & RADV_CMD_FLAG_INV_SCACHE) {
1312 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
1313 *sqtt_flush_bits |= RGP_FLUSH_INVAL_SMEM_L0;
1314 }
1315
1316 if (gfx_level <= GFX8) {
1317 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB) {
1318 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) | S_0085F0_CB0_DEST_BASE_ENA(1) | S_0085F0_CB1_DEST_BASE_ENA(1) |
1319 S_0085F0_CB2_DEST_BASE_ENA(1) | S_0085F0_CB3_DEST_BASE_ENA(1) |
1320 S_0085F0_CB4_DEST_BASE_ENA(1) | S_0085F0_CB5_DEST_BASE_ENA(1) |
1321 S_0085F0_CB6_DEST_BASE_ENA(1) | S_0085F0_CB7_DEST_BASE_ENA(1);
1322
1323 /* Necessary for DCC */
1324 if (gfx_level >= GFX8) {
1325 radv_cs_emit_write_event_eop(cs, gfx_level, is_mec, V_028A90_FLUSH_AND_INV_CB_DATA_TS, 0, EOP_DST_SEL_MEM,
1326 EOP_DATA_SEL_DISCARD, 0, 0, gfx9_eop_bug_va);
1327 }
1328
1329 *sqtt_flush_bits |= RGP_FLUSH_FLUSH_CB | RGP_FLUSH_INVAL_CB;
1330 }
1331 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB) {
1332 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) | S_0085F0_DB_DEST_BASE_ENA(1);
1333
1334 *sqtt_flush_bits |= RGP_FLUSH_FLUSH_DB | RGP_FLUSH_INVAL_DB;
1335 }
1336 }
1337
1338 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_CB_META) {
1339 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1340 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
1341
1342 *sqtt_flush_bits |= RGP_FLUSH_FLUSH_CB | RGP_FLUSH_INVAL_CB;
1343 }
1344
1345 if (flush_bits & RADV_CMD_FLAG_FLUSH_AND_INV_DB_META) {
1346 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1347 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
1348
1349 *sqtt_flush_bits |= RGP_FLUSH_FLUSH_DB | RGP_FLUSH_INVAL_DB;
1350 }
1351
1352 if (flush_bits & RADV_CMD_FLAG_PS_PARTIAL_FLUSH) {
1353 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1354 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1355
1356 *sqtt_flush_bits |= RGP_FLUSH_PS_PARTIAL_FLUSH;
1357 } else if (flush_bits & RADV_CMD_FLAG_VS_PARTIAL_FLUSH) {
1358 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1359 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1360
1361 *sqtt_flush_bits |= RGP_FLUSH_VS_PARTIAL_FLUSH;
1362 }
1363
1364 if (flush_bits & RADV_CMD_FLAG_CS_PARTIAL_FLUSH) {
1365 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1366 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1367
1368 *sqtt_flush_bits |= RGP_FLUSH_CS_PARTIAL_FLUSH;
1369 }
1370
1371 if (gfx_level == GFX9 && flush_cb_db) {
1372 unsigned cb_db_event, tc_flags;
1373
1374 /* Set the CB/DB flush event. */
1375 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1376
1377 /* These are the only allowed combinations. If you need to
1378 * do multiple operations at once, do them separately.
1379 * All operations that invalidate L2 also seem to invalidate
1380 * metadata. Volatile (VOL) and WC flushes are not listed here.
1381 *
1382 * TC | TC_WB = writeback & invalidate L2 & L1
1383 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1384 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1385 * TC | TC_NC = invalidate L2 for MTYPE == NC
1386 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1387 * TCL1 = invalidate L1
1388 */
1389 tc_flags = EVENT_TC_ACTION_ENA | EVENT_TC_MD_ACTION_ENA;
1390
1391 *sqtt_flush_bits |= RGP_FLUSH_FLUSH_CB | RGP_FLUSH_INVAL_CB | RGP_FLUSH_FLUSH_DB | RGP_FLUSH_INVAL_DB;
1392
1393 /* Ideally flush TC together with CB/DB. */
1394 if (flush_bits & RADV_CMD_FLAG_INV_L2) {
1395 /* Writeback and invalidate everything in L2 & L1. */
1396 tc_flags = EVENT_TC_ACTION_ENA | EVENT_TC_WB_ACTION_ENA;
1397
1398 /* Clear the flags. */
1399 flush_bits &= ~(RADV_CMD_FLAG_INV_L2 | RADV_CMD_FLAG_WB_L2 | RADV_CMD_FLAG_INV_VCACHE);
1400
1401 *sqtt_flush_bits |= RGP_FLUSH_INVAL_L2;
1402 }
1403
1404 assert(flush_cnt);
1405 (*flush_cnt)++;
1406
1407 radv_cs_emit_write_event_eop(cs, gfx_level, false, cb_db_event, tc_flags, EOP_DST_SEL_MEM,
1408 EOP_DATA_SEL_VALUE_32BIT, flush_va, *flush_cnt, gfx9_eop_bug_va);
1409 radv_cp_wait_mem(cs, qf, WAIT_REG_MEM_EQUAL, flush_va, *flush_cnt, 0xffffffff);
1410 }
1411
1412 /* VGT state sync */
1413 if (flush_bits & RADV_CMD_FLAG_VGT_FLUSH) {
1414 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1415 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1416 }
1417
1418 /* VGT streamout state sync */
1419 if (flush_bits & RADV_CMD_FLAG_VGT_STREAMOUT_SYNC) {
1420 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1421 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
1422 }
1423
1424 /* Make sure ME is idle (it executes most packets) before continuing.
1425 * This prevents read-after-write hazards between PFP and ME.
1426 */
1427 if ((cp_coher_cntl || (flush_bits & (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_VCACHE |
1428 RADV_CMD_FLAG_INV_L2 | RADV_CMD_FLAG_WB_L2))) &&
1429 !is_mec) {
1430 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1431 radeon_emit(cs, 0);
1432
1433 *sqtt_flush_bits |= RGP_FLUSH_PFP_SYNC_ME;
1434 }
1435
1436 if ((flush_bits & RADV_CMD_FLAG_INV_L2) || (gfx_level <= GFX7 && (flush_bits & RADV_CMD_FLAG_WB_L2))) {
1437 radv_emit_acquire_mem(cs, is_mec, gfx_level == GFX9,
1438 cp_coher_cntl | S_0085F0_TC_ACTION_ENA(1) | S_0085F0_TCL1_ACTION_ENA(1) |
1439 S_0301F0_TC_WB_ACTION_ENA(gfx_level >= GFX8));
1440 cp_coher_cntl = 0;
1441
1442 *sqtt_flush_bits |= RGP_FLUSH_INVAL_L2 | RGP_FLUSH_INVAL_VMEM_L0;
1443 } else {
1444 if (flush_bits & RADV_CMD_FLAG_WB_L2) {
1445 /* WB = write-back
1446 * NC = apply to non-coherent MTYPEs
1447 * (i.e. MTYPE <= 1, which is what we use everywhere)
1448 *
1449 * WB doesn't work without NC.
1450 */
1451 radv_emit_acquire_mem(cs, is_mec, gfx_level == GFX9,
1452 cp_coher_cntl | S_0301F0_TC_WB_ACTION_ENA(1) | S_0301F0_TC_NC_ACTION_ENA(1));
1453 cp_coher_cntl = 0;
1454
1455 *sqtt_flush_bits |= RGP_FLUSH_FLUSH_L2 | RGP_FLUSH_INVAL_VMEM_L0;
1456 }
1457 if (flush_bits & RADV_CMD_FLAG_INV_VCACHE) {
1458 radv_emit_acquire_mem(cs, is_mec, gfx_level == GFX9, cp_coher_cntl | S_0085F0_TCL1_ACTION_ENA(1));
1459 cp_coher_cntl = 0;
1460
1461 *sqtt_flush_bits |= RGP_FLUSH_INVAL_VMEM_L0;
1462 }
1463 }
1464
1465 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
1466 * Therefore, it should be last. Done in PFP.
1467 */
1468 if (cp_coher_cntl)
1469 radv_emit_acquire_mem(cs, is_mec, gfx_level == GFX9, cp_coher_cntl);
1470
1471 if (flush_bits & RADV_CMD_FLAG_START_PIPELINE_STATS) {
1472 if (qf == RADV_QUEUE_GENERAL) {
1473 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1474 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) | EVENT_INDEX(0));
1475 } else if (qf == RADV_QUEUE_COMPUTE) {
1476 radeon_set_sh_reg(cs, R_00B828_COMPUTE_PIPELINESTAT_ENABLE, S_00B828_PIPELINESTAT_ENABLE(1));
1477 }
1478 } else if (flush_bits & RADV_CMD_FLAG_STOP_PIPELINE_STATS) {
1479 if (qf == RADV_QUEUE_GENERAL) {
1480 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1481 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) | EVENT_INDEX(0));
1482 } else if (qf == RADV_QUEUE_COMPUTE) {
1483 radeon_set_sh_reg(cs, R_00B828_COMPUTE_PIPELINESTAT_ENABLE, S_00B828_PIPELINESTAT_ENABLE(0));
1484 }
1485 }
1486 }
1487
1488 void
radv_emit_cache_flush(struct radv_cmd_buffer * cmd_buffer)1489 radv_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
1490 {
1491 bool is_compute = cmd_buffer->qf == RADV_QUEUE_COMPUTE;
1492
1493 if (is_compute)
1494 cmd_buffer->state.flush_bits &=
1495 ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB | RADV_CMD_FLAG_FLUSH_AND_INV_CB_META | RADV_CMD_FLAG_FLUSH_AND_INV_DB |
1496 RADV_CMD_FLAG_FLUSH_AND_INV_DB_META | RADV_CMD_FLAG_INV_L2_METADATA | RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
1497 RADV_CMD_FLAG_VS_PARTIAL_FLUSH | RADV_CMD_FLAG_VGT_FLUSH | RADV_CMD_FLAG_START_PIPELINE_STATS |
1498 RADV_CMD_FLAG_STOP_PIPELINE_STATS);
1499
1500 if (!cmd_buffer->state.flush_bits) {
1501 radv_describe_barrier_end_delayed(cmd_buffer);
1502 return;
1503 }
1504
1505 radv_cs_emit_cache_flush(
1506 cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->device->physical_device->rad_info.gfx_level,
1507 &cmd_buffer->gfx9_fence_idx, cmd_buffer->gfx9_fence_va, radv_cmd_buffer_uses_mec(cmd_buffer),
1508 cmd_buffer->state.flush_bits, &cmd_buffer->state.sqtt_flush_bits, cmd_buffer->gfx9_eop_bug_va);
1509
1510 if (radv_device_fault_detection_enabled(cmd_buffer->device))
1511 radv_cmd_buffer_trace_emit(cmd_buffer);
1512
1513 if (cmd_buffer->state.flush_bits & RADV_CMD_FLAG_INV_L2)
1514 cmd_buffer->state.rb_noncoherent_dirty = false;
1515
1516 /* Clear the caches that have been flushed to avoid syncing too much
1517 * when there is some pending active queries.
1518 */
1519 cmd_buffer->active_query_flush_bits &= ~cmd_buffer->state.flush_bits;
1520
1521 cmd_buffer->state.flush_bits = 0;
1522
1523 /* If the driver used a compute shader for resetting a query pool, it
1524 * should be finished at this point.
1525 */
1526 cmd_buffer->pending_reset_query = false;
1527
1528 radv_describe_barrier_end_delayed(cmd_buffer);
1529 }
1530
1531 /* sets the CP predication state using a boolean stored at va */
1532 void
radv_emit_set_predication_state(struct radv_cmd_buffer * cmd_buffer,bool draw_visible,unsigned pred_op,uint64_t va)1533 radv_emit_set_predication_state(struct radv_cmd_buffer *cmd_buffer, bool draw_visible, unsigned pred_op, uint64_t va)
1534 {
1535 uint32_t op = 0;
1536
1537 radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);
1538
1539 if (va) {
1540 assert(pred_op == PREDICATION_OP_BOOL32 || pred_op == PREDICATION_OP_BOOL64);
1541
1542 op = PRED_OP(pred_op);
1543
1544 /* PREDICATION_DRAW_VISIBLE means that if the 32-bit value is
1545 * zero, all rendering commands are discarded. Otherwise, they
1546 * are discarded if the value is non zero.
1547 */
1548 op |= draw_visible ? PREDICATION_DRAW_VISIBLE : PREDICATION_DRAW_NOT_VISIBLE;
1549 }
1550 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9) {
1551 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
1552 radeon_emit(cmd_buffer->cs, op);
1553 radeon_emit(cmd_buffer->cs, va);
1554 radeon_emit(cmd_buffer->cs, va >> 32);
1555 } else {
1556 radeon_emit(cmd_buffer->cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
1557 radeon_emit(cmd_buffer->cs, va);
1558 radeon_emit(cmd_buffer->cs, op | ((va >> 32) & 0xFF));
1559 }
1560 }
1561
1562 /* Set this if you want the 3D engine to wait until CP DMA is done.
1563 * It should be set on the last CP DMA packet. */
1564 #define CP_DMA_SYNC (1 << 0)
1565
1566 /* Set this if the source data was used as a destination in a previous CP DMA
1567 * packet. It's for preventing a read-after-write (RAW) hazard between two
1568 * CP DMA packets. */
1569 #define CP_DMA_RAW_WAIT (1 << 1)
1570 #define CP_DMA_USE_L2 (1 << 2)
1571 #define CP_DMA_CLEAR (1 << 3)
1572
1573 /* Alignment for optimal performance. */
1574 #define SI_CPDMA_ALIGNMENT 32
1575
1576 /* The max number of bytes that can be copied per packet. */
1577 static inline unsigned
cp_dma_max_byte_count(enum amd_gfx_level gfx_level)1578 cp_dma_max_byte_count(enum amd_gfx_level gfx_level)
1579 {
1580 unsigned max = gfx_level >= GFX11 ? 32767
1581 : gfx_level >= GFX9 ? S_415_BYTE_COUNT_GFX9(~0u)
1582 : S_415_BYTE_COUNT_GFX6(~0u);
1583
1584 /* make it aligned for optimal performance */
1585 return max & ~(SI_CPDMA_ALIGNMENT - 1);
1586 }
1587
1588 /* Emit a CP DMA packet to do a copy from one buffer to another, or to clear
1589 * a buffer. The size must fit in bits [20:0]. If CP_DMA_CLEAR is set, src_va is a 32-bit
1590 * clear value.
1591 */
1592 static void
radv_cs_emit_cp_dma(struct radv_device * device,struct radeon_cmdbuf * cs,bool predicating,uint64_t dst_va,uint64_t src_va,unsigned size,unsigned flags)1593 radv_cs_emit_cp_dma(struct radv_device *device, struct radeon_cmdbuf *cs, bool predicating, uint64_t dst_va,
1594 uint64_t src_va, unsigned size, unsigned flags)
1595 {
1596 uint32_t header = 0, command = 0;
1597
1598 assert(size <= cp_dma_max_byte_count(device->physical_device->rad_info.gfx_level));
1599
1600 radeon_check_space(device->ws, cs, 9);
1601 if (device->physical_device->rad_info.gfx_level >= GFX9)
1602 command |= S_415_BYTE_COUNT_GFX9(size);
1603 else
1604 command |= S_415_BYTE_COUNT_GFX6(size);
1605
1606 /* Sync flags. */
1607 if (flags & CP_DMA_SYNC)
1608 header |= S_411_CP_SYNC(1);
1609
1610 if (flags & CP_DMA_RAW_WAIT)
1611 command |= S_415_RAW_WAIT(1);
1612
1613 /* Src and dst flags. */
1614 if (device->physical_device->rad_info.gfx_level >= GFX9 && !(flags & CP_DMA_CLEAR) && src_va == dst_va)
1615 header |= S_411_DST_SEL(V_411_NOWHERE); /* prefetch only */
1616 else if (flags & CP_DMA_USE_L2)
1617 header |= S_411_DST_SEL(V_411_DST_ADDR_TC_L2);
1618
1619 if (flags & CP_DMA_CLEAR)
1620 header |= S_411_SRC_SEL(V_411_DATA);
1621 else if (flags & CP_DMA_USE_L2)
1622 header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
1623
1624 if (device->physical_device->rad_info.gfx_level >= GFX7) {
1625 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, predicating));
1626 radeon_emit(cs, header);
1627 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1628 radeon_emit(cs, src_va >> 32); /* SRC_ADDR_HI [31:0] */
1629 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1630 radeon_emit(cs, dst_va >> 32); /* DST_ADDR_HI [31:0] */
1631 radeon_emit(cs, command);
1632 } else {
1633 assert(!(flags & CP_DMA_USE_L2));
1634 header |= S_411_SRC_ADDR_HI(src_va >> 32);
1635 radeon_emit(cs, PKT3(PKT3_CP_DMA, 4, predicating));
1636 radeon_emit(cs, src_va); /* SRC_ADDR_LO [31:0] */
1637 radeon_emit(cs, header); /* SRC_ADDR_HI [15:0] + flags. */
1638 radeon_emit(cs, dst_va); /* DST_ADDR_LO [31:0] */
1639 radeon_emit(cs, (dst_va >> 32) & 0xffff); /* DST_ADDR_HI [15:0] */
1640 radeon_emit(cs, command);
1641 }
1642 }
1643
1644 static void
radv_emit_cp_dma(struct radv_cmd_buffer * cmd_buffer,uint64_t dst_va,uint64_t src_va,unsigned size,unsigned flags)1645 radv_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer, uint64_t dst_va, uint64_t src_va, unsigned size, unsigned flags)
1646 {
1647 struct radeon_cmdbuf *cs = cmd_buffer->cs;
1648 struct radv_device *device = cmd_buffer->device;
1649 bool predicating = cmd_buffer->state.predicating;
1650
1651 radv_cs_emit_cp_dma(device, cs, predicating, dst_va, src_va, size, flags);
1652
1653 /* CP DMA is executed in ME, but index buffers are read by PFP.
1654 * This ensures that ME (CP DMA) is idle before PFP starts fetching
1655 * indices. If we wanted to execute CP DMA in PFP, this packet
1656 * should precede it.
1657 */
1658 if (flags & CP_DMA_SYNC) {
1659 if (cmd_buffer->qf == RADV_QUEUE_GENERAL) {
1660 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
1661 radeon_emit(cs, 0);
1662 }
1663
1664 /* CP will see the sync flag and wait for all DMAs to complete. */
1665 cmd_buffer->state.dma_is_busy = false;
1666 }
1667
1668 if (radv_device_fault_detection_enabled(cmd_buffer->device))
1669 radv_cmd_buffer_trace_emit(cmd_buffer);
1670 }
1671
1672 void
radv_cs_cp_dma_prefetch(const struct radv_device * device,struct radeon_cmdbuf * cs,uint64_t va,unsigned size,bool predicating)1673 radv_cs_cp_dma_prefetch(const struct radv_device *device, struct radeon_cmdbuf *cs, uint64_t va, unsigned size,
1674 bool predicating)
1675 {
1676 struct radeon_winsys *ws = device->ws;
1677 enum amd_gfx_level gfx_level = device->physical_device->rad_info.gfx_level;
1678 uint32_t header = 0, command = 0;
1679
1680 if (gfx_level >= GFX11)
1681 size = MIN2(size, 32768 - SI_CPDMA_ALIGNMENT);
1682
1683 assert(size <= cp_dma_max_byte_count(gfx_level));
1684
1685 radeon_check_space(ws, cs, 9);
1686
1687 uint64_t aligned_va = va & ~(SI_CPDMA_ALIGNMENT - 1);
1688 uint64_t aligned_size = ((va + size + SI_CPDMA_ALIGNMENT - 1) & ~(SI_CPDMA_ALIGNMENT - 1)) - aligned_va;
1689
1690 if (gfx_level >= GFX9) {
1691 command |= S_415_BYTE_COUNT_GFX9(aligned_size) | S_415_DISABLE_WR_CONFIRM_GFX9(1);
1692 header |= S_411_DST_SEL(V_411_NOWHERE);
1693 } else {
1694 command |= S_415_BYTE_COUNT_GFX6(aligned_size) | S_415_DISABLE_WR_CONFIRM_GFX6(1);
1695 header |= S_411_DST_SEL(V_411_DST_ADDR_TC_L2);
1696 }
1697
1698 header |= S_411_SRC_SEL(V_411_SRC_ADDR_TC_L2);
1699
1700 radeon_emit(cs, PKT3(PKT3_DMA_DATA, 5, predicating));
1701 radeon_emit(cs, header);
1702 radeon_emit(cs, aligned_va); /* SRC_ADDR_LO [31:0] */
1703 radeon_emit(cs, aligned_va >> 32); /* SRC_ADDR_HI [31:0] */
1704 radeon_emit(cs, aligned_va); /* DST_ADDR_LO [31:0] */
1705 radeon_emit(cs, aligned_va >> 32); /* DST_ADDR_HI [31:0] */
1706 radeon_emit(cs, command);
1707 }
1708
1709 void
radv_cp_dma_prefetch(struct radv_cmd_buffer * cmd_buffer,uint64_t va,unsigned size)1710 radv_cp_dma_prefetch(struct radv_cmd_buffer *cmd_buffer, uint64_t va, unsigned size)
1711 {
1712 radv_cs_cp_dma_prefetch(cmd_buffer->device, cmd_buffer->cs, va, size, cmd_buffer->state.predicating);
1713
1714 if (radv_device_fault_detection_enabled(cmd_buffer->device))
1715 radv_cmd_buffer_trace_emit(cmd_buffer);
1716 }
1717
1718 static void
radv_cp_dma_prepare(struct radv_cmd_buffer * cmd_buffer,uint64_t byte_count,uint64_t remaining_size,unsigned * flags)1719 radv_cp_dma_prepare(struct radv_cmd_buffer *cmd_buffer, uint64_t byte_count, uint64_t remaining_size, unsigned *flags)
1720 {
1721
1722 /* Flush the caches for the first copy only.
1723 * Also wait for the previous CP DMA operations.
1724 */
1725 if (cmd_buffer->state.flush_bits) {
1726 radv_emit_cache_flush(cmd_buffer);
1727 *flags |= CP_DMA_RAW_WAIT;
1728 }
1729
1730 /* Do the synchronization after the last dma, so that all data
1731 * is written to memory.
1732 */
1733 if (byte_count == remaining_size)
1734 *flags |= CP_DMA_SYNC;
1735 }
1736
1737 static void
radv_cp_dma_realign_engine(struct radv_cmd_buffer * cmd_buffer,unsigned size)1738 radv_cp_dma_realign_engine(struct radv_cmd_buffer *cmd_buffer, unsigned size)
1739 {
1740 uint64_t va;
1741 uint32_t offset;
1742 unsigned dma_flags = 0;
1743 unsigned buf_size = SI_CPDMA_ALIGNMENT * 2;
1744 void *ptr;
1745
1746 assert(size < SI_CPDMA_ALIGNMENT);
1747
1748 radv_cmd_buffer_upload_alloc(cmd_buffer, buf_size, &offset, &ptr);
1749
1750 va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);
1751 va += offset;
1752
1753 radv_cp_dma_prepare(cmd_buffer, size, size, &dma_flags);
1754
1755 radv_emit_cp_dma(cmd_buffer, va, va + SI_CPDMA_ALIGNMENT, size, dma_flags);
1756 }
1757
1758 void
radv_cp_dma_buffer_copy(struct radv_cmd_buffer * cmd_buffer,uint64_t src_va,uint64_t dest_va,uint64_t size)1759 radv_cp_dma_buffer_copy(struct radv_cmd_buffer *cmd_buffer, uint64_t src_va, uint64_t dest_va, uint64_t size)
1760 {
1761 enum amd_gfx_level gfx_level = cmd_buffer->device->physical_device->rad_info.gfx_level;
1762 uint64_t main_src_va, main_dest_va;
1763 uint64_t skipped_size = 0, realign_size = 0;
1764
1765 /* Assume that we are not going to sync after the last DMA operation. */
1766 cmd_buffer->state.dma_is_busy = true;
1767
1768 if (cmd_buffer->device->physical_device->rad_info.family <= CHIP_CARRIZO ||
1769 cmd_buffer->device->physical_device->rad_info.family == CHIP_STONEY) {
1770 /* If the size is not aligned, we must add a dummy copy at the end
1771 * just to align the internal counter. Otherwise, the DMA engine
1772 * would slow down by an order of magnitude for following copies.
1773 */
1774 if (size % SI_CPDMA_ALIGNMENT)
1775 realign_size = SI_CPDMA_ALIGNMENT - (size % SI_CPDMA_ALIGNMENT);
1776
1777 /* If the copy begins unaligned, we must start copying from the next
1778 * aligned block and the skipped part should be copied after everything
1779 * else has been copied. Only the src alignment matters, not dst.
1780 */
1781 if (src_va % SI_CPDMA_ALIGNMENT) {
1782 skipped_size = SI_CPDMA_ALIGNMENT - (src_va % SI_CPDMA_ALIGNMENT);
1783 /* The main part will be skipped if the size is too small. */
1784 skipped_size = MIN2(skipped_size, size);
1785 size -= skipped_size;
1786 }
1787 }
1788 main_src_va = src_va + skipped_size;
1789 main_dest_va = dest_va + skipped_size;
1790
1791 while (size) {
1792 unsigned dma_flags = 0;
1793 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(gfx_level));
1794
1795 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9) {
1796 /* DMA operations via L2 are coherent and faster.
1797 * TODO: GFX7-GFX8 should also support this but it
1798 * requires tests/benchmarks.
1799 *
1800 * Also enable on GFX9 so we can use L2 at rest on GFX9+. On Raven
1801 * this didn't seem to be worse.
1802 *
1803 * Note that we only use CP DMA for sizes < RADV_BUFFER_OPS_CS_THRESHOLD,
1804 * which is 4k at the moment, so this is really unlikely to cause
1805 * significant thrashing.
1806 */
1807 dma_flags |= CP_DMA_USE_L2;
1808 }
1809
1810 radv_cp_dma_prepare(cmd_buffer, byte_count, size + skipped_size + realign_size, &dma_flags);
1811
1812 dma_flags &= ~CP_DMA_SYNC;
1813
1814 radv_emit_cp_dma(cmd_buffer, main_dest_va, main_src_va, byte_count, dma_flags);
1815
1816 size -= byte_count;
1817 main_src_va += byte_count;
1818 main_dest_va += byte_count;
1819 }
1820
1821 if (skipped_size) {
1822 unsigned dma_flags = 0;
1823
1824 radv_cp_dma_prepare(cmd_buffer, skipped_size, size + skipped_size + realign_size, &dma_flags);
1825
1826 radv_emit_cp_dma(cmd_buffer, dest_va, src_va, skipped_size, dma_flags);
1827 }
1828 if (realign_size)
1829 radv_cp_dma_realign_engine(cmd_buffer, realign_size);
1830 }
1831
1832 void
radv_cp_dma_clear_buffer(struct radv_cmd_buffer * cmd_buffer,uint64_t va,uint64_t size,unsigned value)1833 radv_cp_dma_clear_buffer(struct radv_cmd_buffer *cmd_buffer, uint64_t va, uint64_t size, unsigned value)
1834 {
1835 if (!size)
1836 return;
1837
1838 assert(va % 4 == 0 && size % 4 == 0);
1839
1840 enum amd_gfx_level gfx_level = cmd_buffer->device->physical_device->rad_info.gfx_level;
1841
1842 /* Assume that we are not going to sync after the last DMA operation. */
1843 cmd_buffer->state.dma_is_busy = true;
1844
1845 while (size) {
1846 unsigned byte_count = MIN2(size, cp_dma_max_byte_count(gfx_level));
1847 unsigned dma_flags = CP_DMA_CLEAR;
1848
1849 if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX9) {
1850 /* DMA operations via L2 are coherent and faster.
1851 * TODO: GFX7-GFX8 should also support this but it
1852 * requires tests/benchmarks.
1853 *
1854 * Also enable on GFX9 so we can use L2 at rest on GFX9+.
1855 */
1856 dma_flags |= CP_DMA_USE_L2;
1857 }
1858
1859 radv_cp_dma_prepare(cmd_buffer, byte_count, size, &dma_flags);
1860
1861 /* Emit the clear packet. */
1862 radv_emit_cp_dma(cmd_buffer, va, value, byte_count, dma_flags);
1863
1864 size -= byte_count;
1865 va += byte_count;
1866 }
1867 }
1868
1869 void
radv_cp_dma_wait_for_idle(struct radv_cmd_buffer * cmd_buffer)1870 radv_cp_dma_wait_for_idle(struct radv_cmd_buffer *cmd_buffer)
1871 {
1872 if (cmd_buffer->device->physical_device->rad_info.gfx_level < GFX7)
1873 return;
1874
1875 if (!cmd_buffer->state.dma_is_busy)
1876 return;
1877
1878 /* Issue a dummy DMA that copies zero bytes.
1879 *
1880 * The DMA engine will see that there's no work to do and skip this
1881 * DMA request, however, the CP will see the sync flag and still wait
1882 * for all DMAs to complete.
1883 */
1884 radv_emit_cp_dma(cmd_buffer, 0, 0, 0, CP_DMA_SYNC);
1885
1886 cmd_buffer->state.dma_is_busy = false;
1887 }
1888
1889 /* For MSAA sample positions. */
1890 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1891 ((((unsigned)(s0x)&0xf) << 0) | (((unsigned)(s0y)&0xf) << 4) | (((unsigned)(s1x)&0xf) << 8) | \
1892 (((unsigned)(s1y)&0xf) << 12) | (((unsigned)(s2x)&0xf) << 16) | (((unsigned)(s2y)&0xf) << 20) | \
1893 (((unsigned)(s3x)&0xf) << 24) | (((unsigned)(s3y)&0xf) << 28))
1894
1895 /* For obtaining location coordinates from registers */
1896 #define SEXT4(x) ((int)((x) | ((x)&0x8 ? 0xfffffff0 : 0)))
1897 #define GET_SFIELD(reg, index) SEXT4(((reg) >> ((index)*4)) & 0xf)
1898 #define GET_SX(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2)
1899 #define GET_SY(reg, index) GET_SFIELD((reg)[(index) / 4], ((index) % 4) * 2 + 1)
1900
1901 /* 1x MSAA */
1902 static const uint32_t sample_locs_1x = FILL_SREG(0, 0, 0, 0, 0, 0, 0, 0);
1903 static const unsigned max_dist_1x = 0;
1904 static const uint64_t centroid_priority_1x = 0x0000000000000000ull;
1905
1906 /* 2xMSAA */
1907 static const uint32_t sample_locs_2x = FILL_SREG(4, 4, -4, -4, 0, 0, 0, 0);
1908 static const unsigned max_dist_2x = 4;
1909 static const uint64_t centroid_priority_2x = 0x1010101010101010ull;
1910
1911 /* 4xMSAA */
1912 static const uint32_t sample_locs_4x = FILL_SREG(-2, -6, 6, -2, -6, 2, 2, 6);
1913 static const unsigned max_dist_4x = 6;
1914 static const uint64_t centroid_priority_4x = 0x3210321032103210ull;
1915
1916 /* 8xMSAA */
1917 static const uint32_t sample_locs_8x[] = {
1918 FILL_SREG(1, -3, -1, 3, 5, 1, -3, -5),
1919 FILL_SREG(-5, 5, -7, -1, 3, 7, 7, -7),
1920 /* The following are unused by hardware, but we emit them to IBs
1921 * instead of multiple SET_CONTEXT_REG packets. */
1922 0,
1923 0,
1924 };
1925 static const unsigned max_dist_8x = 7;
1926 static const uint64_t centroid_priority_8x = 0x7654321076543210ull;
1927
1928 unsigned
radv_get_default_max_sample_dist(int log_samples)1929 radv_get_default_max_sample_dist(int log_samples)
1930 {
1931 unsigned max_dist[] = {
1932 max_dist_1x,
1933 max_dist_2x,
1934 max_dist_4x,
1935 max_dist_8x,
1936 };
1937 return max_dist[log_samples];
1938 }
1939
1940 void
radv_emit_default_sample_locations(struct radeon_cmdbuf * cs,int nr_samples)1941 radv_emit_default_sample_locations(struct radeon_cmdbuf *cs, int nr_samples)
1942 {
1943 switch (nr_samples) {
1944 default:
1945 case 1:
1946 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1947 radeon_emit(cs, (uint32_t)centroid_priority_1x);
1948 radeon_emit(cs, centroid_priority_1x >> 32);
1949 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_1x);
1950 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_1x);
1951 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_1x);
1952 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_1x);
1953 break;
1954 case 2:
1955 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1956 radeon_emit(cs, (uint32_t)centroid_priority_2x);
1957 radeon_emit(cs, centroid_priority_2x >> 32);
1958 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x);
1959 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x);
1960 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x);
1961 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x);
1962 break;
1963 case 4:
1964 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1965 radeon_emit(cs, (uint32_t)centroid_priority_4x);
1966 radeon_emit(cs, centroid_priority_4x >> 32);
1967 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x);
1968 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x);
1969 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x);
1970 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x);
1971 break;
1972 case 8:
1973 radeon_set_context_reg_seq(cs, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1974 radeon_emit(cs, (uint32_t)centroid_priority_8x);
1975 radeon_emit(cs, centroid_priority_8x >> 32);
1976 radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
1977 radeon_emit_array(cs, sample_locs_8x, 4);
1978 radeon_emit_array(cs, sample_locs_8x, 4);
1979 radeon_emit_array(cs, sample_locs_8x, 4);
1980 radeon_emit_array(cs, sample_locs_8x, 2);
1981 break;
1982 }
1983 }
1984
1985 static void
radv_get_sample_position(struct radv_device * device,unsigned sample_count,unsigned sample_index,float * out_value)1986 radv_get_sample_position(struct radv_device *device, unsigned sample_count, unsigned sample_index, float *out_value)
1987 {
1988 const uint32_t *sample_locs;
1989
1990 switch (sample_count) {
1991 case 1:
1992 default:
1993 sample_locs = &sample_locs_1x;
1994 break;
1995 case 2:
1996 sample_locs = &sample_locs_2x;
1997 break;
1998 case 4:
1999 sample_locs = &sample_locs_4x;
2000 break;
2001 case 8:
2002 sample_locs = sample_locs_8x;
2003 break;
2004 }
2005
2006 out_value[0] = (GET_SX(sample_locs, sample_index) + 8) / 16.0f;
2007 out_value[1] = (GET_SY(sample_locs, sample_index) + 8) / 16.0f;
2008 }
2009
2010 void
radv_device_init_msaa(struct radv_device * device)2011 radv_device_init_msaa(struct radv_device *device)
2012 {
2013 int i;
2014
2015 radv_get_sample_position(device, 1, 0, device->sample_locations_1x[0]);
2016
2017 for (i = 0; i < 2; i++)
2018 radv_get_sample_position(device, 2, i, device->sample_locations_2x[i]);
2019 for (i = 0; i < 4; i++)
2020 radv_get_sample_position(device, 4, i, device->sample_locations_4x[i]);
2021 for (i = 0; i < 8; i++)
2022 radv_get_sample_position(device, 8, i, device->sample_locations_8x[i]);
2023 }
2024
2025 void
radv_cs_write_data_imm(struct radeon_cmdbuf * cs,unsigned engine_sel,uint64_t va,uint32_t imm)2026 radv_cs_write_data_imm(struct radeon_cmdbuf *cs, unsigned engine_sel, uint64_t va, uint32_t imm)
2027 {
2028 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
2029 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) | S_370_WR_CONFIRM(1) | S_370_ENGINE_SEL(engine_sel));
2030 radeon_emit(cs, va);
2031 radeon_emit(cs, va >> 32);
2032 radeon_emit(cs, imm);
2033 }
2034