1 /* Copyright 2022 Advanced Micro Devices, Inc.
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice shall be included in
11 * all copies or substantial portions of the Software.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
19 * OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * Authors: AMD
22 *
23 */
24
25 #include "vpe_assert.h"
26 #include "vpe_command.h"
27 #include "plane_desc_writer.h"
28 #include "reg_helper.h"
29
plane_desc_writer_init(struct plane_desc_writer * writer,struct vpe_buf * buf,int32_t nps0,int32_t npd0,int32_t nps1,int32_t npd1,int32_t subop)30 void plane_desc_writer_init(struct plane_desc_writer *writer, struct vpe_buf *buf, int32_t nps0,
31 int32_t npd0, int32_t nps1, int32_t npd1, int32_t subop)
32 {
33 uint32_t *cmd_space;
34 uint64_t size = 4;
35 writer->status = VPE_STATUS_OK;
36 writer->base_cpu_va = buf->cpu_va;
37 writer->base_gpu_va = buf->gpu_va;
38 writer->buf = buf;
39 writer->num_src = 0;
40 writer->num_dst = 0;
41
42 /* Buffer does not have enough space to write */
43 if (buf->size < size) {
44 writer->status = VPE_STATUS_BUFFER_OVERFLOW;
45 return;
46 }
47
48 cmd_space = (uint32_t *)(uintptr_t)writer->buf->cpu_va;
49 *cmd_space++ = VPE_PLANE_CFG_CMD_HEADER(subop, nps0, npd0, nps1, npd1);
50
51 writer->buf->cpu_va += size;
52 writer->buf->gpu_va += size;
53 writer->buf->size -= size;
54 }
55
56 /** fill the value to the embedded buffer. */
plane_desc_writer_add_source(struct plane_desc_writer * writer,struct plane_desc_src * src,bool is_plane0)57 void plane_desc_writer_add_source(
58 struct plane_desc_writer *writer, struct plane_desc_src *src, bool is_plane0)
59 {
60 uint32_t *cmd_space, *cmd_start;
61 uint32_t num_wd = is_plane0 ? 6 : 5;
62 uint64_t size = num_wd * sizeof(uint32_t);
63
64 if (writer->status != VPE_STATUS_OK)
65 return;
66
67 /* Buffer does not have enough space to write */
68 if (writer->buf->size < size) {
69 writer->status = VPE_STATUS_BUFFER_OVERFLOW;
70 return;
71 }
72 cmd_start = cmd_space = (uint32_t *)(uintptr_t)writer->buf->cpu_va;
73
74 if (is_plane0) {
75 *cmd_space++ = VPEC_FIELD_VALUE(VPE_PLANE_CFG_TMZ, src->tmz) |
76 VPEC_FIELD_VALUE(VPE_PLANE_CFG_SWIZZLE_MODE, src->swizzle) |
77 VPEC_FIELD_VALUE(VPE_PLANE_CFG_ROTATION, src->rotation);
78 writer->num_src++;
79 }
80
81 VPE_ASSERT(!(src->base_addr_lo & 0xFF));
82
83 *cmd_space++ = src->base_addr_lo;
84 *cmd_space++ = src->base_addr_hi;
85
86 *cmd_space++ =
87 VPEC_FIELD_VALUE(VPE_PLANE_CFG_PITCH, src->pitch - 1); // 1-based number of element
88 *cmd_space++ = VPEC_FIELD_VALUE(VPE_PLANE_CFG_VIEWPORT_X, src->viewport_x) |
89 VPEC_FIELD_VALUE(VPE_PLANE_CFG_VIEWPORT_Y, src->viewport_y);
90
91 *cmd_space++ = VPEC_FIELD_VALUE(VPE_PLANE_CFG_VIEWPORT_WIDTH, src->viewport_w - 1) |
92 VPEC_FIELD_VALUE(VPE_PLANE_CFG_VIEWPORT_HEIGHT, src->viewport_h - 1) |
93 VPEC_FIELD_VALUE(VPE_PLANE_CFG_VIEWPORT_ELEMENT_SIZE, src->elem_size);
94
95 writer->buf->cpu_va += size;
96 writer->buf->gpu_va += size;
97 writer->buf->size -= size;
98 }
99
100 /** fill the value to the embedded buffer. */
plane_desc_writer_add_destination(struct plane_desc_writer * writer,struct plane_desc_dst * dst,bool is_plane0)101 void plane_desc_writer_add_destination(
102 struct plane_desc_writer *writer, struct plane_desc_dst *dst, bool is_plane0)
103 {
104 uint32_t *cmd_space, *cmd_start;
105 uint32_t num_wd = is_plane0 ? 6 : 5;
106 uint64_t size = num_wd * sizeof(uint32_t);
107
108 if (writer->status != VPE_STATUS_OK)
109 return;
110
111 /* Buffer does not have enough space to write */
112 if (writer->buf->size < size) {
113 writer->status = VPE_STATUS_BUFFER_OVERFLOW;
114 return;
115 }
116
117 cmd_start = cmd_space = (uint32_t *)(uintptr_t)writer->buf->cpu_va;
118
119 if (is_plane0) {
120 *cmd_space++ = VPEC_FIELD_VALUE(VPE_PLANE_CFG_TMZ, dst->tmz) |
121 VPEC_FIELD_VALUE(VPE_PLANE_CFG_SWIZZLE_MODE, dst->swizzle) |
122 VPEC_FIELD_VALUE(VPE_PLANE_CFG_MIRROR, dst->mirror);
123 writer->num_dst++;
124 }
125
126 VPE_ASSERT(!(dst->base_addr_lo & 0xFF));
127
128 *cmd_space++ = dst->base_addr_lo;
129 *cmd_space++ = dst->base_addr_hi;
130
131 *cmd_space++ =
132 VPEC_FIELD_VALUE(VPE_PLANE_CFG_PITCH, dst->pitch - 1); // 1-based number of element
133 *cmd_space++ = VPEC_FIELD_VALUE(VPE_PLANE_CFG_VIEWPORT_X, dst->viewport_x) |
134 VPEC_FIELD_VALUE(VPE_PLANE_CFG_VIEWPORT_Y, dst->viewport_y);
135
136 *cmd_space++ = VPEC_FIELD_VALUE(VPE_PLANE_CFG_VIEWPORT_WIDTH, dst->viewport_w - 1) |
137 VPEC_FIELD_VALUE(VPE_PLANE_CFG_VIEWPORT_HEIGHT, dst->viewport_h - 1) |
138 VPEC_FIELD_VALUE(VPE_PLANE_CFG_VIEWPORT_ELEMENT_SIZE, dst->elem_size);
139
140 writer->buf->cpu_va += size;
141 writer->buf->gpu_va += size;
142 writer->buf->size -= size;
143 }
144