1 /* 2 ************************************************************************************************************************ 3 * 4 * Copyright (C) 2007-2022 Advanced Micro Devices, Inc. All rights reserved. 5 * SPDX-License-Identifier: MIT 6 * 7 ***********************************************************************************************************************/ 8 9 /** 10 ************************************************************************************************************************ 11 * @file gfx10addrlib.h 12 * @brief Contains the Gfx10Lib class definition. 13 ************************************************************************************************************************ 14 */ 15 16 #ifndef __GFX10_ADDR_LIB_H__ 17 #define __GFX10_ADDR_LIB_H__ 18 19 #include "addrlib2.h" 20 #include "coord.h" 21 #include "gfx10SwizzlePattern.h" 22 23 namespace Addr 24 { 25 namespace V2 26 { 27 28 /** 29 ************************************************************************************************************************ 30 * @brief GFX10 specific settings structure. 31 ************************************************************************************************************************ 32 */ 33 struct Gfx10ChipSettings 34 { 35 struct 36 { 37 UINT_32 reserved1 : 32; 38 39 // Misc configuration bits 40 UINT_32 isDcn20 : 1; // If using DCN2.0 41 UINT_32 supportRbPlus : 1; 42 UINT_32 dsMipmapHtileFix : 1; 43 UINT_32 dccUnsup3DSwDis : 1; 44 UINT_32 : 4; 45 UINT_32 reserved2 : 24; 46 }; 47 }; 48 49 /** 50 ************************************************************************************************************************ 51 * @brief GFX10 data surface type. 52 ************************************************************************************************************************ 53 */ 54 enum Gfx10DataType 55 { 56 Gfx10DataColor, 57 Gfx10DataDepthStencil, 58 Gfx10DataFmask 59 }; 60 61 const UINT_32 Gfx10LinearSwModeMask = (1u << ADDR_SW_LINEAR); 62 63 const UINT_32 Gfx10Blk256BSwModeMask = (1u << ADDR_SW_256B_S) | 64 (1u << ADDR_SW_256B_D); 65 66 const UINT_32 Gfx10Blk4KBSwModeMask = (1u << ADDR_SW_4KB_S) | 67 (1u << ADDR_SW_4KB_D) | 68 (1u << ADDR_SW_4KB_S_X) | 69 (1u << ADDR_SW_4KB_D_X); 70 71 const UINT_32 Gfx10Blk64KBSwModeMask = (1u << ADDR_SW_64KB_S) | 72 (1u << ADDR_SW_64KB_D) | 73 (1u << ADDR_SW_64KB_S_T) | 74 (1u << ADDR_SW_64KB_D_T) | 75 (1u << ADDR_SW_64KB_Z_X) | 76 (1u << ADDR_SW_64KB_S_X) | 77 (1u << ADDR_SW_64KB_D_X) | 78 (1u << ADDR_SW_64KB_R_X); 79 80 const UINT_32 Gfx10BlkVarSwModeMask = (1u << ADDR_SW_VAR_Z_X) | 81 (1u << ADDR_SW_VAR_R_X); 82 83 const UINT_32 Gfx10ZSwModeMask = (1u << ADDR_SW_64KB_Z_X) | 84 (1u << ADDR_SW_VAR_Z_X); 85 86 const UINT_32 Gfx10StandardSwModeMask = (1u << ADDR_SW_256B_S) | 87 (1u << ADDR_SW_4KB_S) | 88 (1u << ADDR_SW_64KB_S) | 89 (1u << ADDR_SW_64KB_S_T) | 90 (1u << ADDR_SW_4KB_S_X) | 91 (1u << ADDR_SW_64KB_S_X); 92 93 const UINT_32 Gfx10DisplaySwModeMask = (1u << ADDR_SW_256B_D) | 94 (1u << ADDR_SW_4KB_D) | 95 (1u << ADDR_SW_64KB_D) | 96 (1u << ADDR_SW_64KB_D_T) | 97 (1u << ADDR_SW_4KB_D_X) | 98 (1u << ADDR_SW_64KB_D_X); 99 100 const UINT_32 Gfx10RenderSwModeMask = (1u << ADDR_SW_64KB_R_X) | 101 (1u << ADDR_SW_VAR_R_X); 102 103 const UINT_32 Gfx10XSwModeMask = (1u << ADDR_SW_4KB_S_X) | 104 (1u << ADDR_SW_4KB_D_X) | 105 (1u << ADDR_SW_64KB_Z_X) | 106 (1u << ADDR_SW_64KB_S_X) | 107 (1u << ADDR_SW_64KB_D_X) | 108 (1u << ADDR_SW_64KB_R_X) | 109 Gfx10BlkVarSwModeMask; 110 111 const UINT_32 Gfx10TSwModeMask = (1u << ADDR_SW_64KB_S_T) | 112 (1u << ADDR_SW_64KB_D_T); 113 114 const UINT_32 Gfx10XorSwModeMask = Gfx10XSwModeMask | 115 Gfx10TSwModeMask; 116 117 const UINT_32 Gfx10Rsrc1dSwModeMask = Gfx10LinearSwModeMask | 118 Gfx10RenderSwModeMask | 119 Gfx10ZSwModeMask; 120 121 const UINT_32 Gfx10Rsrc2dSwModeMask = Gfx10LinearSwModeMask | 122 Gfx10Blk256BSwModeMask | 123 Gfx10Blk4KBSwModeMask | 124 Gfx10Blk64KBSwModeMask | 125 Gfx10BlkVarSwModeMask; 126 127 const UINT_32 Gfx10Rsrc3dSwModeMask = (1u << ADDR_SW_LINEAR) | 128 (1u << ADDR_SW_4KB_S) | 129 (1u << ADDR_SW_64KB_S) | 130 (1u << ADDR_SW_64KB_S_T) | 131 (1u << ADDR_SW_4KB_S_X) | 132 (1u << ADDR_SW_64KB_Z_X) | 133 (1u << ADDR_SW_64KB_S_X) | 134 (1u << ADDR_SW_64KB_D_X) | 135 (1u << ADDR_SW_64KB_R_X) | 136 Gfx10BlkVarSwModeMask; 137 138 const UINT_32 Gfx10Rsrc2dPrtSwModeMask = (Gfx10Blk4KBSwModeMask | Gfx10Blk64KBSwModeMask) & ~Gfx10XSwModeMask; 139 140 const UINT_32 Gfx10Rsrc3dPrtSwModeMask = Gfx10Rsrc2dPrtSwModeMask & ~Gfx10DisplaySwModeMask; 141 142 const UINT_32 Gfx10Rsrc3dThin64KBSwModeMask = (1u << ADDR_SW_64KB_Z_X) | 143 (1u << ADDR_SW_64KB_R_X); 144 145 146 const UINT_32 Gfx10Rsrc3dThinSwModeMask = Gfx10Rsrc3dThin64KBSwModeMask | 147 Gfx10BlkVarSwModeMask; 148 149 const UINT_32 Gfx10Rsrc3dThickSwModeMask = Gfx10Rsrc3dSwModeMask & ~(Gfx10Rsrc3dThinSwModeMask | Gfx10LinearSwModeMask); 150 151 const UINT_32 Gfx10Rsrc3dThick4KBSwModeMask = Gfx10Rsrc3dThickSwModeMask & Gfx10Blk4KBSwModeMask; 152 153 const UINT_32 Gfx10Rsrc3dThick64KBSwModeMask = Gfx10Rsrc3dThickSwModeMask & Gfx10Blk64KBSwModeMask; 154 155 const UINT_32 Gfx10MsaaSwModeMask = (Gfx10ZSwModeMask | 156 Gfx10RenderSwModeMask) 157 ; 158 159 const UINT_32 Dcn20NonBpp64SwModeMask = (1u << ADDR_SW_LINEAR) | 160 (1u << ADDR_SW_4KB_S) | 161 (1u << ADDR_SW_64KB_S) | 162 (1u << ADDR_SW_64KB_S_T) | 163 (1u << ADDR_SW_4KB_S_X) | 164 (1u << ADDR_SW_64KB_S_X) | 165 (1u << ADDR_SW_64KB_R_X); 166 167 const UINT_32 Dcn20Bpp64SwModeMask = (1u << ADDR_SW_4KB_D) | 168 (1u << ADDR_SW_64KB_D) | 169 (1u << ADDR_SW_64KB_D_T) | 170 (1u << ADDR_SW_4KB_D_X) | 171 (1u << ADDR_SW_64KB_D_X) | 172 Dcn20NonBpp64SwModeMask; 173 174 const UINT_32 Dcn21NonBpp64SwModeMask = (1u << ADDR_SW_LINEAR) | 175 (1u << ADDR_SW_64KB_S) | 176 (1u << ADDR_SW_64KB_S_T) | 177 (1u << ADDR_SW_64KB_S_X) | 178 (1u << ADDR_SW_64KB_R_X); 179 180 const UINT_32 Dcn21Bpp64SwModeMask = (1u << ADDR_SW_64KB_D) | 181 (1u << ADDR_SW_64KB_D_T) | 182 (1u << ADDR_SW_64KB_D_X) | 183 Dcn21NonBpp64SwModeMask; 184 185 /** 186 ************************************************************************************************************************ 187 * @brief This class is the GFX10 specific address library 188 * function set. 189 ************************************************************************************************************************ 190 */ 191 class Gfx10Lib : public Lib 192 { 193 public: 194 /// Creates Gfx10Lib object CreateObj(const Client * pClient)195 static Addr::Lib* CreateObj(const Client* pClient) 196 { 197 VOID* pMem = Object::ClientAlloc(sizeof(Gfx10Lib), pClient); 198 return (pMem != NULL) ? new (pMem) Gfx10Lib(pClient) : NULL; 199 } 200 201 protected: 202 Gfx10Lib(const Client* pClient); 203 virtual ~Gfx10Lib(); 204 HwlIsStandardSwizzle(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)205 virtual BOOL_32 HwlIsStandardSwizzle( 206 AddrResourceType resourceType, 207 AddrSwizzleMode swizzleMode) const 208 { 209 return m_swizzleModeTable[swizzleMode].isStd; 210 } 211 HwlIsDisplaySwizzle(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)212 virtual BOOL_32 HwlIsDisplaySwizzle( 213 AddrResourceType resourceType, 214 AddrSwizzleMode swizzleMode) const 215 { 216 return m_swizzleModeTable[swizzleMode].isDisp; 217 } 218 HwlIsThin(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)219 virtual BOOL_32 HwlIsThin( 220 AddrResourceType resourceType, 221 AddrSwizzleMode swizzleMode) const 222 { 223 return ((IsTex1d(resourceType) == TRUE) || 224 (IsTex2d(resourceType) == TRUE) || 225 ((IsTex3d(resourceType) == TRUE) && 226 (m_swizzleModeTable[swizzleMode].isStd == FALSE) && 227 (m_swizzleModeTable[swizzleMode].isDisp == FALSE))); 228 } 229 HwlIsThick(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)230 virtual BOOL_32 HwlIsThick( 231 AddrResourceType resourceType, 232 AddrSwizzleMode swizzleMode) const 233 { 234 return ((IsTex3d(resourceType) == TRUE) && 235 (m_swizzleModeTable[swizzleMode].isStd || m_swizzleModeTable[swizzleMode].isDisp)); 236 } 237 238 virtual ADDR_E_RETURNCODE HwlComputeHtileInfo( 239 const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn, 240 ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const; 241 242 virtual ADDR_E_RETURNCODE HwlComputeCmaskInfo( 243 const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn, 244 ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut) const; 245 246 virtual ADDR_E_RETURNCODE HwlComputeDccInfo( 247 const ADDR2_COMPUTE_DCCINFO_INPUT* pIn, 248 ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const; 249 250 virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord( 251 const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, 252 ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut); 253 254 virtual ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord( 255 const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, 256 ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut); 257 258 virtual ADDR_E_RETURNCODE HwlComputeHtileCoordFromAddr( 259 const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, 260 ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut); 261 262 virtual ADDR_E_RETURNCODE HwlSupportComputeDccAddrFromCoord( 263 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn); 264 265 virtual VOID HwlComputeDccAddrFromCoord( 266 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn, 267 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut); 268 269 virtual UINT_32 HwlGetEquationIndex( 270 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 271 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 272 HwlGetEquationTableInfo(const ADDR_EQUATION ** ppEquationTable)273 virtual UINT_32 HwlGetEquationTableInfo(const ADDR_EQUATION** ppEquationTable) const 274 { 275 *ppEquationTable = m_equationTable; 276 277 return m_numEquations; 278 } 279 280 virtual ADDR_E_RETURNCODE HwlComputePipeBankXor( 281 const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn, 282 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut) const; 283 284 virtual ADDR_E_RETURNCODE HwlComputeSlicePipeBankXor( 285 const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn, 286 ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut) const; 287 288 virtual ADDR_E_RETURNCODE HwlComputeSubResourceOffsetForSwizzlePattern( 289 const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn, 290 ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut) const; 291 292 virtual ADDR_E_RETURNCODE HwlComputeNonBlockCompressedView( 293 const ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT* pIn, 294 ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT* pOut) const; 295 296 virtual ADDR_E_RETURNCODE HwlGetPreferredSurfaceSetting( 297 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn, 298 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const; 299 300 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoSanityCheck( 301 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 302 303 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoTiled( 304 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 305 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 306 307 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoLinear( 308 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 309 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 310 311 virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoordTiled( 312 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 313 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 314 315 virtual UINT_32 HwlComputeMaxBaseAlignments() const; 316 317 virtual UINT_32 HwlComputeMaxMetaBaseAlignments() const; 318 319 virtual BOOL_32 HwlInitGlobalParams(const ADDR_CREATE_INPUT* pCreateIn); 320 321 virtual ChipFamily HwlConvertChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision); 322 323 private: 324 // Initialize equation table 325 VOID InitEquationTable(); 326 327 ADDR_E_RETURNCODE ComputeSurfaceInfoMacroTiled( 328 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 329 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 330 331 ADDR_E_RETURNCODE ComputeSurfaceInfoMicroTiled( 332 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 333 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 334 335 ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordMacroTiled( 336 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 337 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 338 339 ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordMicroTiled( 340 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 341 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 342 343 UINT_32 ComputeOffsetFromSwizzlePattern( 344 const UINT_64* pPattern, 345 UINT_32 numBits, 346 UINT_32 x, 347 UINT_32 y, 348 UINT_32 z, 349 UINT_32 s) const; 350 351 UINT_32 ComputeOffsetFromEquation( 352 const ADDR_EQUATION* pEq, 353 UINT_32 x, 354 UINT_32 y, 355 UINT_32 z) const; 356 357 ADDR_E_RETURNCODE ComputeStereoInfo( 358 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 359 UINT_32* pAlignY, 360 UINT_32* pRightXor) const; 361 362 static void GetMipSize( 363 UINT_32 mip0Width, 364 UINT_32 mip0Height, 365 UINT_32 mip0Depth, 366 UINT_32 mipId, 367 UINT_32* pMipWidth, 368 UINT_32* pMipHeight, 369 UINT_32* pMipDepth = NULL) 370 { 371 *pMipWidth = ShiftCeil(Max(mip0Width, 1u), mipId); 372 *pMipHeight = ShiftCeil(Max(mip0Height, 1u), mipId); 373 374 if (pMipDepth != NULL) 375 { 376 *pMipDepth = ShiftCeil(Max(mip0Depth, 1u), mipId); 377 } 378 } 379 380 const ADDR_SW_PATINFO* GetSwizzlePatternInfo( 381 AddrSwizzleMode swizzleMode, 382 AddrResourceType resourceType, 383 UINT_32 log2Elem, 384 UINT_32 numFrag) const; 385 386 /** 387 * Will use the indices, "nibbles", to build an index equation inside pSwizzle 388 * 389 * @param pPatInfo Pointer to a patInfo. Contains indices mapping to the 2D nibble arrays which will be used to build an index equation. 390 * @param pSwizzle Array to write the index equation to. 391 */ GetSwizzlePatternFromPatternInfo(const ADDR_SW_PATINFO * pPatInfo,ADDR_BIT_SETTING (& pSwizzle)[20])392 VOID GetSwizzlePatternFromPatternInfo( 393 const ADDR_SW_PATINFO* pPatInfo, 394 ADDR_BIT_SETTING (&pSwizzle)[20]) const 395 { 396 memcpy(pSwizzle, 397 GFX10_SW_PATTERN_NIBBLE01[pPatInfo->nibble01Idx], 398 sizeof(GFX10_SW_PATTERN_NIBBLE01[pPatInfo->nibble01Idx])); 399 400 memcpy(&pSwizzle[8], 401 GFX10_SW_PATTERN_NIBBLE2[pPatInfo->nibble2Idx], 402 sizeof(GFX10_SW_PATTERN_NIBBLE2[pPatInfo->nibble2Idx])); 403 404 memcpy(&pSwizzle[12], 405 GFX10_SW_PATTERN_NIBBLE3[pPatInfo->nibble3Idx], 406 sizeof(GFX10_SW_PATTERN_NIBBLE3[pPatInfo->nibble3Idx])); 407 408 memcpy(&pSwizzle[16], 409 GFX10_SW_PATTERN_NIBBLE4[pPatInfo->nibble4Idx], 410 sizeof(GFX10_SW_PATTERN_NIBBLE4[pPatInfo->nibble4Idx])); 411 } 412 413 VOID ConvertSwizzlePatternToEquation( 414 UINT_32 elemLog2, 415 AddrResourceType rsrcType, 416 AddrSwizzleMode swMode, 417 const ADDR_SW_PATINFO* pPatInfo, 418 ADDR_EQUATION* pEquation) const; 419 420 static INT_32 GetMetaElementSizeLog2(Gfx10DataType dataType); 421 422 static INT_32 GetMetaCacheSizeLog2(Gfx10DataType dataType); 423 424 void GetBlk256SizeLog2( 425 AddrResourceType resourceType, 426 AddrSwizzleMode swizzleMode, 427 UINT_32 elemLog2, 428 UINT_32 numSamplesLog2, 429 Dim3d* pBlock) const; 430 431 void GetCompressedBlockSizeLog2( 432 Gfx10DataType dataType, 433 AddrResourceType resourceType, 434 AddrSwizzleMode swizzleMode, 435 UINT_32 elemLog2, 436 UINT_32 numSamplesLog2, 437 Dim3d* pBlock) const; 438 439 INT_32 GetMetaOverlapLog2( 440 Gfx10DataType dataType, 441 AddrResourceType resourceType, 442 AddrSwizzleMode swizzleMode, 443 UINT_32 elemLog2, 444 UINT_32 numSamplesLog2) const; 445 446 INT_32 Get3DMetaOverlapLog2( 447 AddrResourceType resourceType, 448 AddrSwizzleMode swizzleMode, 449 UINT_32 elemLog2) const; 450 451 UINT_32 GetMetaBlkSize( 452 Gfx10DataType dataType, 453 AddrResourceType resourceType, 454 AddrSwizzleMode swizzleMode, 455 UINT_32 elemLog2, 456 UINT_32 numSamplesLog2, 457 BOOL_32 pipeAlign, 458 Dim3d* pBlock) const; 459 460 INT_32 GetPipeRotateAmount( 461 AddrResourceType resourceType, 462 AddrSwizzleMode swizzleMode) const; 463 GetEffectiveNumPipes()464 INT_32 GetEffectiveNumPipes() const 465 { 466 return ((m_settings.supportRbPlus == FALSE) || 467 ((m_numSaLog2 + 1) >= m_pipesLog2)) ? m_pipesLog2 : m_numSaLog2 + 1; 468 } 469 IsRbAligned(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)470 BOOL_32 IsRbAligned( 471 AddrResourceType resourceType, 472 AddrSwizzleMode swizzleMode) const 473 { 474 const BOOL_32 isRtopt = IsRtOptSwizzle(swizzleMode); 475 const BOOL_32 isZ = IsZOrderSwizzle(swizzleMode); 476 const BOOL_32 isDisplay = IsDisplaySwizzle(swizzleMode); 477 478 return (IsTex2d(resourceType) && (isRtopt || isZ)) || 479 (IsTex3d(resourceType) && isDisplay); 480 481 } 482 483 UINT_32 GetValidDisplaySwizzleModes(UINT_32 bpp) const; 484 485 BOOL_32 IsValidDisplaySwizzleMode(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 486 487 UINT_32 GetMaxNumMipsInTail(UINT_32 blockSizeLog2, BOOL_32 isThin) const; 488 GetAllowedBlockSet(ADDR2_SWMODE_SET allowedSwModeSet,AddrResourceType rsrcType)489 static ADDR2_BLOCK_SET GetAllowedBlockSet(ADDR2_SWMODE_SET allowedSwModeSet, AddrResourceType rsrcType) 490 { 491 ADDR2_BLOCK_SET allowedBlockSet = {}; 492 493 allowedBlockSet.micro = (allowedSwModeSet.value & Gfx10Blk256BSwModeMask) ? TRUE : FALSE; 494 allowedBlockSet.linear = (allowedSwModeSet.value & Gfx10LinearSwModeMask) ? TRUE : FALSE; 495 allowedBlockSet.var = (allowedSwModeSet.value & Gfx10BlkVarSwModeMask) ? TRUE : FALSE; 496 497 if (rsrcType == ADDR_RSRC_TEX_3D) 498 { 499 allowedBlockSet.macroThick4KB = (allowedSwModeSet.value & Gfx10Rsrc3dThick4KBSwModeMask) ? TRUE : FALSE; 500 allowedBlockSet.macroThin64KB = (allowedSwModeSet.value & Gfx10Rsrc3dThin64KBSwModeMask) ? TRUE : FALSE; 501 allowedBlockSet.macroThick64KB = (allowedSwModeSet.value & Gfx10Rsrc3dThick64KBSwModeMask) ? TRUE : FALSE; 502 } 503 else 504 { 505 allowedBlockSet.macroThin4KB = (allowedSwModeSet.value & Gfx10Blk4KBSwModeMask) ? TRUE : FALSE; 506 allowedBlockSet.macroThin64KB = (allowedSwModeSet.value & Gfx10Blk64KBSwModeMask) ? TRUE : FALSE; 507 } 508 509 return allowedBlockSet; 510 } 511 GetAllowedSwSet(ADDR2_SWMODE_SET allowedSwModeSet)512 static ADDR2_SWTYPE_SET GetAllowedSwSet(ADDR2_SWMODE_SET allowedSwModeSet) 513 { 514 ADDR2_SWTYPE_SET allowedSwSet = {}; 515 516 allowedSwSet.sw_Z = (allowedSwModeSet.value & Gfx10ZSwModeMask) ? TRUE : FALSE; 517 allowedSwSet.sw_S = (allowedSwModeSet.value & Gfx10StandardSwModeMask) ? TRUE : FALSE; 518 allowedSwSet.sw_D = (allowedSwModeSet.value & Gfx10DisplaySwModeMask) ? TRUE : FALSE; 519 allowedSwSet.sw_R = (allowedSwModeSet.value & Gfx10RenderSwModeMask) ? TRUE : FALSE; 520 521 return allowedSwSet; 522 } 523 IsInMipTail(Dim3d mipTailDim,UINT_32 maxNumMipsInTail,UINT_32 mipWidth,UINT_32 mipHeight,UINT_32 numMipsToTheEnd)524 BOOL_32 IsInMipTail( 525 Dim3d mipTailDim, 526 UINT_32 maxNumMipsInTail, 527 UINT_32 mipWidth, 528 UINT_32 mipHeight, 529 UINT_32 numMipsToTheEnd) const 530 { 531 BOOL_32 inTail = ((mipWidth <= mipTailDim.w) && 532 (mipHeight <= mipTailDim.h) && 533 (numMipsToTheEnd <= maxNumMipsInTail)); 534 535 return inTail; 536 } 537 GetBankXorBits(UINT_32 blockBits)538 UINT_32 GetBankXorBits(UINT_32 blockBits) const 539 { 540 return (blockBits > m_pipeInterleaveLog2 + m_pipesLog2 + ColumnBits) ? 541 Min(blockBits - m_pipeInterleaveLog2 - m_pipesLog2 - ColumnBits, BankBits) : 0; 542 } 543 544 BOOL_32 ValidateNonSwModeParams(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 545 BOOL_32 ValidateSwModeParams(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 546 547 static const UINT_32 ColumnBits = 2; 548 static const UINT_32 BankBits = 4; 549 static const UINT_32 UnalignedDccType = 3; 550 551 static const Dim3d Block256_3d[MaxNumOfBpp]; 552 static const Dim3d Block64K_Log2_3d[MaxNumOfBpp]; 553 static const Dim3d Block4K_Log2_3d[MaxNumOfBpp]; 554 555 static const SwizzleModeFlags SwizzleModeTable[ADDR_SW_MAX_TYPE]; 556 557 // Number of packers log2 558 UINT_32 m_numPkrLog2; 559 // Number of shader array log2 560 UINT_32 m_numSaLog2; 561 562 Gfx10ChipSettings m_settings; 563 564 UINT_32 m_colorBaseIndex; 565 UINT_32 m_xmaskBaseIndex; 566 UINT_32 m_htileBaseIndex; 567 UINT_32 m_dccBaseIndex; 568 }; 569 570 } // V2 571 } // Addr 572 573 #endif 574 575