1 /*
2 * Copyright © 2023, VideoLAN and dav1d authors
3 * Copyright © 2023, Loongson Technology Corporation Limited
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 *
9 * 1. Redistributions of source code must retain the above copyright notice, this
10 * list of conditions and the following disclaimer.
11 *
12 * 2. Redistributions in binary form must reproduce the above copyright notice,
13 * this list of conditions and the following disclaimer in the documentation
14 * and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
20 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #ifndef DAV1D_SRC_LOONGARCH_ITX_H
29 #define DAV1D_SRC_LOONGARCH_ITX_H
30
31 #include "src/cpu.h"
32 #include "src/itx.h"
33
34 decl_itx_fn(BF(dav1d_inv_txfm_add_wht_wht_4x4, lsx));
35 decl_itx_fn(BF(dav1d_inv_txfm_add_dct_dct_4x4, lsx));
36 decl_itx_fn(BF(dav1d_inv_txfm_add_identity_identity_4x4, lsx));
37 decl_itx_fn(BF(dav1d_inv_txfm_add_adst_dct_4x4, lsx));
38 decl_itx_fn(BF(dav1d_inv_txfm_add_dct_adst_4x4, lsx));
39 decl_itx_fn(BF(dav1d_inv_txfm_add_adst_adst_4x4, lsx));
40 decl_itx_fn(BF(dav1d_inv_txfm_add_dct_flipadst_4x4, lsx));
41 decl_itx_fn(BF(dav1d_inv_txfm_add_flipadst_adst_4x4, lsx));
42 decl_itx_fn(BF(dav1d_inv_txfm_add_adst_flipadst_4x4, lsx));
43 decl_itx_fn(BF(dav1d_inv_txfm_add_flipadst_dct_4x4, lsx));
44 decl_itx_fn(BF(dav1d_inv_txfm_add_flipadst_flipadst_4x4, lsx));
45 decl_itx_fn(BF(dav1d_inv_txfm_add_dct_identity_4x4, lsx));
46 decl_itx_fn(BF(dav1d_inv_txfm_add_identity_dct_4x4, lsx));
47 decl_itx_fn(BF(dav1d_inv_txfm_add_flipadst_identity_4x4, lsx));
48 decl_itx_fn(BF(dav1d_inv_txfm_add_identity_flipadst_4x4, lsx));
49 decl_itx_fn(BF(dav1d_inv_txfm_add_identity_adst_4x4, lsx));
50 decl_itx_fn(BF(dav1d_inv_txfm_add_adst_identity_4x4, lsx));
51
52 decl_itx_fn(BF(dav1d_inv_txfm_add_dct_dct_4x8, lsx));
53
54 decl_itx_fn(BF(dav1d_inv_txfm_add_dct_dct_8x4, lsx));
55 decl_itx_fn(BF(dav1d_inv_txfm_add_identity_identity_8x4, lsx));
56 decl_itx_fn(BF(dav1d_inv_txfm_add_adst_dct_8x4, lsx));
57 decl_itx_fn(BF(dav1d_inv_txfm_add_dct_adst_8x4, lsx));
58 decl_itx_fn(BF(dav1d_inv_txfm_add_adst_adst_8x4, lsx));
59 decl_itx_fn(BF(dav1d_inv_txfm_add_flipadst_adst_8x4, lsx));
60 decl_itx_fn(BF(dav1d_inv_txfm_add_adst_flipadst_8x4, lsx));
61 decl_itx_fn(BF(dav1d_inv_txfm_add_flipadst_dct_8x4, lsx));
62 decl_itx_fn(BF(dav1d_inv_txfm_add_dct_flipadst_8x4, lsx));
63 decl_itx_fn(BF(dav1d_inv_txfm_add_flipadst_flipadst_8x4, lsx));
64 decl_itx_fn(BF(dav1d_inv_txfm_add_dct_identity_8x4, lsx));
65 decl_itx_fn(BF(dav1d_inv_txfm_add_identity_dct_8x4, lsx));
66 decl_itx_fn(BF(dav1d_inv_txfm_add_flipadst_identity_8x4, lsx));
67 decl_itx_fn(BF(dav1d_inv_txfm_add_identity_flipadst_8x4, lsx));
68 decl_itx_fn(BF(dav1d_inv_txfm_add_adst_identity_8x4, lsx));
69 decl_itx_fn(BF(dav1d_inv_txfm_add_identity_adst_8x4, lsx));
70
71 decl_itx_fn(BF(dav1d_inv_txfm_add_dct_dct_8x8, lsx));
72 decl_itx_fn(BF(dav1d_inv_txfm_add_identity_identity_8x8, lsx));
73 decl_itx_fn(BF(dav1d_inv_txfm_add_adst_dct_8x8, lsx));
74 decl_itx_fn(BF(dav1d_inv_txfm_add_dct_adst_8x8, lsx));
75 decl_itx_fn(BF(dav1d_inv_txfm_add_adst_adst_8x8, lsx));
76 decl_itx_fn(BF(dav1d_inv_txfm_add_flipadst_adst_8x8, lsx));
77 decl_itx_fn(BF(dav1d_inv_txfm_add_adst_flipadst_8x8, lsx));
78 decl_itx_fn(BF(dav1d_inv_txfm_add_flipadst_dct_8x8, lsx));
79 decl_itx_fn(BF(dav1d_inv_txfm_add_dct_flipadst_8x8, lsx));
80 decl_itx_fn(BF(dav1d_inv_txfm_add_identity_adst_8x8, lsx));
81 decl_itx_fn(BF(dav1d_inv_txfm_add_flipadst_identity_8x8, lsx));
82 decl_itx_fn(BF(dav1d_inv_txfm_add_dct_identity_8x8, lsx));
83 decl_itx_fn(BF(dav1d_inv_txfm_add_identity_dct_8x8, lsx));
84 decl_itx_fn(BF(dav1d_inv_txfm_add_identity_flipadst_8x8, lsx));
85 decl_itx_fn(BF(dav1d_inv_txfm_add_adst_identity_8x8, lsx));
86 decl_itx_fn(BF(dav1d_inv_txfm_add_flipadst_flipadst_8x8, lsx));
87
88 decl_itx_fn(BF(dav1d_inv_txfm_add_dct_dct_8x16, lsx));
89 decl_itx_fn(BF(dav1d_inv_txfm_add_identity_identity_8x16, lsx));
90 decl_itx_fn(BF(dav1d_inv_txfm_add_adst_dct_8x16, lsx));
91 decl_itx_fn(BF(dav1d_inv_txfm_add_dct_adst_8x16, lsx));
92
93 decl_itx_fn(BF(dav1d_inv_txfm_add_dct_dct_16x8, lsx));
94 decl_itx_fn(BF(dav1d_inv_txfm_add_adst_dct_16x8, lsx));
95
96 decl_itx_fn(BF(dav1d_inv_txfm_add_dct_dct_16x16, lsx));
97 decl_itx_fn(BF(dav1d_inv_txfm_add_adst_adst_16x16, lsx));
98 decl_itx_fn(BF(dav1d_inv_txfm_add_adst_dct_16x16, lsx));
99 decl_itx_fn(BF(dav1d_inv_txfm_add_dct_adst_16x16, lsx));
100 decl_itx_fn(BF(dav1d_inv_txfm_add_flipadst_dct_16x16, lsx));
101 decl_itx_fn(BF(dav1d_inv_txfm_add_dct_flipadst_16x16, lsx));
102
103 decl_itx_fn(BF(dav1d_inv_txfm_add_dct_dct_8x32, lsx));
104 decl_itx_fn(BF(dav1d_inv_txfm_add_dct_dct_32x32, lsx));
105
106 decl_itx_fn(BF(dav1d_inv_txfm_add_dct_dct_32x32, lsx));
107
108 decl_itx_fn(BF(dav1d_inv_txfm_add_dct_dct_64x64, lsx));
109
itx_dsp_init_loongarch(Dav1dInvTxfmDSPContext * const c,int bpc)110 static ALWAYS_INLINE void itx_dsp_init_loongarch(Dav1dInvTxfmDSPContext *const c, int bpc) {
111 #if BITDEPTH == 8
112 const unsigned flags = dav1d_get_cpu_flags();
113
114 if (!(flags & DAV1D_LOONGARCH_CPU_FLAG_LSX)) return;
115
116 if (BITDEPTH != 8 ) return;
117
118 c->itxfm_add[TX_4X4][WHT_WHT] = dav1d_inv_txfm_add_wht_wht_4x4_8bpc_lsx;
119 c->itxfm_add[TX_4X4][DCT_DCT] = dav1d_inv_txfm_add_dct_dct_4x4_8bpc_lsx;
120 c->itxfm_add[TX_4X4][IDTX] = dav1d_inv_txfm_add_identity_identity_4x4_8bpc_lsx;
121 c->itxfm_add[TX_4X4][DCT_ADST] = dav1d_inv_txfm_add_adst_dct_4x4_8bpc_lsx;
122 c->itxfm_add[TX_4X4][ADST_DCT] = dav1d_inv_txfm_add_dct_adst_4x4_8bpc_lsx;
123 c->itxfm_add[TX_4X4][ADST_ADST] = dav1d_inv_txfm_add_adst_adst_4x4_8bpc_lsx;
124 c->itxfm_add[TX_4X4][FLIPADST_DCT] = dav1d_inv_txfm_add_dct_flipadst_4x4_8bpc_lsx;
125 c->itxfm_add[TX_4X4][ADST_FLIPADST] = dav1d_inv_txfm_add_flipadst_adst_4x4_8bpc_lsx;
126 c->itxfm_add[TX_4X4][FLIPADST_ADST] = dav1d_inv_txfm_add_adst_flipadst_4x4_8bpc_lsx;
127 c->itxfm_add[TX_4X4][DCT_FLIPADST] = dav1d_inv_txfm_add_flipadst_dct_4x4_8bpc_lsx;
128 c->itxfm_add[TX_4X4][FLIPADST_FLIPADST] = dav1d_inv_txfm_add_flipadst_flipadst_4x4_8bpc_lsx;
129 c->itxfm_add[TX_4X4][H_DCT] = dav1d_inv_txfm_add_dct_identity_4x4_8bpc_lsx;
130 c->itxfm_add[TX_4X4][V_DCT] = dav1d_inv_txfm_add_identity_dct_4x4_8bpc_lsx;
131 c->itxfm_add[TX_4X4][H_FLIPADST] = dav1d_inv_txfm_add_flipadst_identity_4x4_8bpc_lsx;
132 c->itxfm_add[TX_4X4][V_FLIPADST] = dav1d_inv_txfm_add_identity_flipadst_4x4_8bpc_lsx;
133 c->itxfm_add[TX_4X4][V_ADST] = dav1d_inv_txfm_add_identity_adst_4x4_8bpc_lsx;
134 c->itxfm_add[TX_4X4][H_ADST] = dav1d_inv_txfm_add_adst_identity_4x4_8bpc_lsx;
135
136 c->itxfm_add[RTX_4X8][DCT_DCT] = dav1d_inv_txfm_add_dct_dct_4x8_8bpc_lsx;
137
138 c->itxfm_add[RTX_8X4][DCT_DCT] = dav1d_inv_txfm_add_dct_dct_8x4_8bpc_lsx;
139 c->itxfm_add[RTX_8X4][IDTX] = dav1d_inv_txfm_add_identity_identity_8x4_8bpc_lsx;
140 c->itxfm_add[RTX_8X4][DCT_ADST] = dav1d_inv_txfm_add_adst_dct_8x4_8bpc_lsx;
141 c->itxfm_add[RTX_8X4][ADST_DCT] = dav1d_inv_txfm_add_dct_adst_8x4_8bpc_lsx;
142 c->itxfm_add[RTX_8X4][ADST_ADST] = dav1d_inv_txfm_add_adst_adst_8x4_8bpc_lsx;
143 c->itxfm_add[RTX_8X4][ADST_FLIPADST] = dav1d_inv_txfm_add_flipadst_adst_8x4_8bpc_lsx;
144 c->itxfm_add[RTX_8X4][FLIPADST_ADST] = dav1d_inv_txfm_add_adst_flipadst_8x4_8bpc_lsx;
145 c->itxfm_add[RTX_8X4][DCT_FLIPADST] = dav1d_inv_txfm_add_flipadst_dct_8x4_8bpc_lsx;
146 c->itxfm_add[RTX_8X4][FLIPADST_DCT] = dav1d_inv_txfm_add_dct_flipadst_8x4_8bpc_lsx;
147 c->itxfm_add[RTX_8X4][FLIPADST_FLIPADST] = dav1d_inv_txfm_add_flipadst_flipadst_8x4_8bpc_lsx;
148 c->itxfm_add[RTX_8X4][H_DCT] = dav1d_inv_txfm_add_dct_identity_8x4_8bpc_lsx;
149 c->itxfm_add[RTX_8X4][V_DCT] = dav1d_inv_txfm_add_identity_dct_8x4_8bpc_lsx;
150 c->itxfm_add[RTX_8X4][H_FLIPADST] = dav1d_inv_txfm_add_flipadst_identity_8x4_8bpc_lsx;
151 c->itxfm_add[RTX_8X4][V_FLIPADST] = dav1d_inv_txfm_add_identity_flipadst_8x4_8bpc_lsx;
152 c->itxfm_add[RTX_8X4][H_ADST] = dav1d_inv_txfm_add_adst_identity_8x4_8bpc_lsx;
153 c->itxfm_add[RTX_8X4][V_ADST] = dav1d_inv_txfm_add_identity_adst_8x4_8bpc_lsx;
154
155 c->itxfm_add[TX_8X8][DCT_DCT] = dav1d_inv_txfm_add_dct_dct_8x8_8bpc_lsx;
156 c->itxfm_add[TX_8X8][IDTX] = dav1d_inv_txfm_add_identity_identity_8x8_8bpc_lsx;
157 c->itxfm_add[TX_8X8][DCT_ADST] = dav1d_inv_txfm_add_adst_dct_8x8_8bpc_lsx;
158 c->itxfm_add[TX_8X8][ADST_DCT] = dav1d_inv_txfm_add_dct_adst_8x8_8bpc_lsx;
159 c->itxfm_add[TX_8X8][ADST_ADST] = dav1d_inv_txfm_add_adst_adst_8x8_8bpc_lsx;
160 c->itxfm_add[TX_8X8][ADST_FLIPADST] = dav1d_inv_txfm_add_flipadst_adst_8x8_8bpc_lsx;
161 c->itxfm_add[TX_8X8][FLIPADST_ADST] = dav1d_inv_txfm_add_adst_flipadst_8x8_8bpc_lsx;
162 c->itxfm_add[TX_8X8][DCT_FLIPADST] = dav1d_inv_txfm_add_flipadst_dct_8x8_8bpc_lsx;
163 c->itxfm_add[TX_8X8][FLIPADST_DCT] = dav1d_inv_txfm_add_dct_flipadst_8x8_8bpc_lsx;
164 c->itxfm_add[TX_8X8][FLIPADST_FLIPADST] = dav1d_inv_txfm_add_flipadst_flipadst_8x8_8bpc_lsx;
165 c->itxfm_add[TX_8X8][H_DCT] = dav1d_inv_txfm_add_dct_identity_8x8_8bpc_lsx;
166 c->itxfm_add[TX_8X8][V_DCT] = dav1d_inv_txfm_add_identity_dct_8x8_8bpc_lsx;
167 c->itxfm_add[TX_8X8][H_FLIPADST] = dav1d_inv_txfm_add_flipadst_identity_8x8_8bpc_lsx;
168 c->itxfm_add[TX_8X8][V_FLIPADST] = dav1d_inv_txfm_add_identity_flipadst_8x8_8bpc_lsx;
169 c->itxfm_add[TX_8X8][H_ADST] = dav1d_inv_txfm_add_adst_identity_8x8_8bpc_lsx;
170 c->itxfm_add[TX_8X8][V_ADST] = dav1d_inv_txfm_add_identity_adst_8x8_8bpc_lsx;
171
172 c->itxfm_add[RTX_8X16][DCT_DCT] = dav1d_inv_txfm_add_dct_dct_8x16_8bpc_lsx;
173 c->itxfm_add[RTX_8X16][IDTX] = dav1d_inv_txfm_add_identity_identity_8x16_8bpc_lsx;
174 c->itxfm_add[RTX_8X16][DCT_ADST] = dav1d_inv_txfm_add_adst_dct_8x16_8bpc_lsx;
175 c->itxfm_add[RTX_8X16][ADST_DCT] = dav1d_inv_txfm_add_dct_adst_8x16_8bpc_lsx;
176
177 c->itxfm_add[RTX_16X8][DCT_DCT] = dav1d_inv_txfm_add_dct_dct_16x8_8bpc_lsx;
178 c->itxfm_add[RTX_16X8][DCT_ADST] = dav1d_inv_txfm_add_adst_dct_16x8_8bpc_lsx;
179
180 c->itxfm_add[TX_16X16][DCT_DCT] = dav1d_inv_txfm_add_dct_dct_16x16_8bpc_lsx;
181 c->itxfm_add[TX_16X16][ADST_ADST] = dav1d_inv_txfm_add_adst_adst_16x16_8bpc_lsx;
182 c->itxfm_add[TX_16X16][DCT_ADST] = dav1d_inv_txfm_add_adst_dct_16x16_8bpc_lsx;
183 c->itxfm_add[TX_16X16][ADST_DCT] = dav1d_inv_txfm_add_dct_adst_16x16_8bpc_lsx;
184 c->itxfm_add[TX_16X16][DCT_FLIPADST] = dav1d_inv_txfm_add_flipadst_dct_16x16_8bpc_lsx;
185 c->itxfm_add[TX_16X16][FLIPADST_DCT] = dav1d_inv_txfm_add_dct_flipadst_16x16_8bpc_lsx;
186
187 c->itxfm_add[RTX_8X32][DCT_DCT] = dav1d_inv_txfm_add_dct_dct_8x32_8bpc_lsx;
188
189 c->itxfm_add[TX_32X32][DCT_DCT] = dav1d_inv_txfm_add_dct_dct_32x32_8bpc_lsx;
190
191 c->itxfm_add[TX_64X64][DCT_DCT] = dav1d_inv_txfm_add_dct_dct_64x64_8bpc_lsx;
192 #endif
193 }
194
195 #endif /* DAV1D_SRC_LOONGARCH_ITX_H */
196