1 /*
2 ************************************************************************************************************************
3 *
4 * Copyright (C) 2007-2022 Advanced Micro Devices, Inc. All rights reserved.
5 * SPDX-License-Identifier: MIT
6 *
7 ***********************************************************************************************************************/
8
9 /**
10 ****************************************************************************************************
11 * @file siaddrlib.cpp
12 * @brief Contains the implementation for the SiLib class.
13 ****************************************************************************************************
14 */
15
16 #include "siaddrlib.h"
17 #include "si_gb_reg.h"
18
19 #include "amdgpu_asic_addr.h"
20
21 ////////////////////////////////////////////////////////////////////////////////////////////////////
22 ////////////////////////////////////////////////////////////////////////////////////////////////////
23 namespace Addr
24 {
25
26 /**
27 ****************************************************************************************************
28 * SiHwlInit
29 *
30 * @brief
31 * Creates an SiLib object.
32 *
33 * @return
34 * Returns an SiLib object pointer.
35 ****************************************************************************************************
36 */
SiHwlInit(const Client * pClient)37 Lib* SiHwlInit(const Client* pClient)
38 {
39 return V1::SiLib::CreateObj(pClient);
40 }
41
42 namespace V1
43 {
44
45 // We don't support MSAA for equation
46 const BOOL_32 SiLib::m_EquationSupport[SiLib::TileTableSize][SiLib::MaxNumElementBytes] =
47 {
48 {TRUE, TRUE, TRUE, FALSE, FALSE}, // 0, non-AA compressed depth or any stencil
49 {FALSE, FALSE, FALSE, FALSE, FALSE}, // 1, 2xAA/4xAA compressed depth with or without stencil
50 {FALSE, FALSE, FALSE, FALSE, FALSE}, // 2, 8xAA compressed depth with or without stencil
51 {FALSE, TRUE, FALSE, FALSE, FALSE}, // 3, 16 bpp depth PRT (non-MSAA), don't support uncompressed depth
52 {TRUE, TRUE, TRUE, FALSE, FALSE}, // 4, 1D depth
53 {FALSE, FALSE, FALSE, FALSE, FALSE}, // 5, 16 bpp depth PRT (4xMSAA)
54 {FALSE, FALSE, TRUE, FALSE, FALSE}, // 6, 32 bpp depth PRT (non-MSAA)
55 {FALSE, FALSE, FALSE, FALSE, FALSE}, // 7, 32 bpp depth PRT (4xMSAA)
56 {TRUE, TRUE, TRUE, TRUE, TRUE }, // 8, Linear
57 {TRUE, TRUE, TRUE, TRUE, TRUE }, // 9, 1D display
58 {TRUE, FALSE, FALSE, FALSE, FALSE}, // 10, 8 bpp color (displayable)
59 {FALSE, TRUE, FALSE, FALSE, FALSE}, // 11, 16 bpp color (displayable)
60 {FALSE, FALSE, TRUE, TRUE, FALSE}, // 12, 32/64 bpp color (displayable)
61 {TRUE, TRUE, TRUE, TRUE, TRUE }, // 13, 1D thin
62 {TRUE, FALSE, FALSE, FALSE, FALSE}, // 14, 8 bpp color non-displayable
63 {FALSE, TRUE, FALSE, FALSE, FALSE}, // 15, 16 bpp color non-displayable
64 {FALSE, FALSE, TRUE, FALSE, FALSE}, // 16, 32 bpp color non-displayable
65 {FALSE, FALSE, FALSE, TRUE, TRUE }, // 17, 64/128 bpp color non-displayable
66 {TRUE, TRUE, TRUE, TRUE, TRUE }, // 18, 1D THICK
67 {FALSE, FALSE, FALSE, FALSE, FALSE}, // 19, 2D XTHICK
68 {FALSE, FALSE, FALSE, FALSE, FALSE}, // 20, 2D THICK
69 {TRUE, FALSE, FALSE, FALSE, FALSE}, // 21, 8 bpp 2D PRTs (non-MSAA)
70 {FALSE, TRUE, FALSE, FALSE, FALSE}, // 22, 16 bpp 2D PRTs (non-MSAA)
71 {FALSE, FALSE, TRUE, FALSE, FALSE}, // 23, 32 bpp 2D PRTs (non-MSAA)
72 {FALSE, FALSE, FALSE, TRUE, FALSE}, // 24, 64 bpp 2D PRTs (non-MSAA)
73 {FALSE, FALSE, FALSE, FALSE, TRUE }, // 25, 128bpp 2D PRTs (non-MSAA)
74 {FALSE, FALSE, FALSE, FALSE, FALSE}, // 26, none
75 {FALSE, FALSE, FALSE, FALSE, FALSE}, // 27, none
76 {FALSE, FALSE, FALSE, FALSE, FALSE}, // 28, none
77 {FALSE, FALSE, FALSE, FALSE, FALSE}, // 29, none
78 {FALSE, FALSE, FALSE, FALSE, FALSE}, // 30, 64bpp 2D PRTs (4xMSAA)
79 {FALSE, FALSE, FALSE, FALSE, FALSE}, // 31, none
80 };
81
82 /**
83 ****************************************************************************************************
84 * SiLib::SiLib
85 *
86 * @brief
87 * Constructor
88 *
89 ****************************************************************************************************
90 */
SiLib(const Client * pClient)91 SiLib::SiLib(const Client* pClient)
92 :
93 EgBasedLib(pClient),
94 m_noOfEntries(0),
95 m_numEquations(0)
96 {
97 memset(&m_settings, 0, sizeof(m_settings));
98 }
99
100 /**
101 ****************************************************************************************************
102 * SiLib::~SiLib
103 *
104 * @brief
105 * Destructor
106 ****************************************************************************************************
107 */
~SiLib()108 SiLib::~SiLib()
109 {
110 }
111
112 /**
113 ****************************************************************************************************
114 * SiLib::HwlGetPipes
115 *
116 * @brief
117 * Get number pipes
118 * @return
119 * num pipes
120 ****************************************************************************************************
121 */
HwlGetPipes(const ADDR_TILEINFO * pTileInfo) const122 UINT_32 SiLib::HwlGetPipes(
123 const ADDR_TILEINFO* pTileInfo ///< [in] Tile info
124 ) const
125 {
126 UINT_32 numPipes;
127
128 if (pTileInfo)
129 {
130 numPipes = GetPipePerSurf(pTileInfo->pipeConfig);
131 }
132 else
133 {
134 ADDR_ASSERT_ALWAYS();
135 numPipes = m_pipes; // Suppose we should still have a global pipes
136 }
137
138 return numPipes;
139 }
140
141 /**
142 ****************************************************************************************************
143 * SiLib::GetPipePerSurf
144 * @brief
145 * get pipe num base on inputing tileinfo->pipeconfig
146 * @return
147 * pipe number
148 ****************************************************************************************************
149 */
GetPipePerSurf(AddrPipeCfg pipeConfig) const150 UINT_32 SiLib::GetPipePerSurf(
151 AddrPipeCfg pipeConfig ///< [in] pipe config
152 ) const
153 {
154 UINT_32 numPipes = 0;
155
156 switch (pipeConfig)
157 {
158 case ADDR_PIPECFG_P2:
159 numPipes = 2;
160 break;
161 case ADDR_PIPECFG_P4_8x16:
162 case ADDR_PIPECFG_P4_16x16:
163 case ADDR_PIPECFG_P4_16x32:
164 case ADDR_PIPECFG_P4_32x32:
165 numPipes = 4;
166 break;
167 case ADDR_PIPECFG_P8_16x16_8x16:
168 case ADDR_PIPECFG_P8_16x32_8x16:
169 case ADDR_PIPECFG_P8_32x32_8x16:
170 case ADDR_PIPECFG_P8_16x32_16x16:
171 case ADDR_PIPECFG_P8_32x32_16x16:
172 case ADDR_PIPECFG_P8_32x32_16x32:
173 case ADDR_PIPECFG_P8_32x64_32x32:
174 numPipes = 8;
175 break;
176 case ADDR_PIPECFG_P16_32x32_8x16:
177 case ADDR_PIPECFG_P16_32x32_16x16:
178 numPipes = 16;
179 break;
180 default:
181 ADDR_ASSERT(!"Invalid pipe config");
182 numPipes = m_pipes;
183 }
184 return numPipes;
185 }
186
187 /**
188 ****************************************************************************************************
189 * SiLib::ComputeBankEquation
190 *
191 * @brief
192 * Compute bank equation
193 *
194 * @return
195 * If equation can be computed
196 ****************************************************************************************************
197 */
ComputeBankEquation(UINT_32 log2BytesPP,UINT_32 threshX,UINT_32 threshY,ADDR_TILEINFO * pTileInfo,ADDR_EQUATION * pEquation) const198 ADDR_E_RETURNCODE SiLib::ComputeBankEquation(
199 UINT_32 log2BytesPP, ///< [in] log2 of bytes per pixel
200 UINT_32 threshX, ///< [in] threshold for x channel
201 UINT_32 threshY, ///< [in] threshold for y channel
202 ADDR_TILEINFO* pTileInfo, ///< [in] tile info
203 ADDR_EQUATION* pEquation ///< [out] bank equation
204 ) const
205 {
206 ADDR_E_RETURNCODE retCode = ADDR_OK;
207
208 UINT_32 pipes = HwlGetPipes(pTileInfo);
209 UINT_32 bankXStart = 3 + Log2(pipes) + Log2(pTileInfo->bankWidth);
210 UINT_32 bankYStart = 3 + Log2(pTileInfo->bankHeight);
211
212 ADDR_CHANNEL_SETTING x3 = InitChannel(1, 0, log2BytesPP + bankXStart);
213 ADDR_CHANNEL_SETTING x4 = InitChannel(1, 0, log2BytesPP + bankXStart + 1);
214 ADDR_CHANNEL_SETTING x5 = InitChannel(1, 0, log2BytesPP + bankXStart + 2);
215 ADDR_CHANNEL_SETTING x6 = InitChannel(1, 0, log2BytesPP + bankXStart + 3);
216 ADDR_CHANNEL_SETTING y3 = InitChannel(1, 1, bankYStart);
217 ADDR_CHANNEL_SETTING y4 = InitChannel(1, 1, bankYStart + 1);
218 ADDR_CHANNEL_SETTING y5 = InitChannel(1, 1, bankYStart + 2);
219 ADDR_CHANNEL_SETTING y6 = InitChannel(1, 1, bankYStart + 3);
220
221 x3.value = (threshX > bankXStart) ? x3.value : 0;
222 x4.value = (threshX > bankXStart + 1) ? x4.value : 0;
223 x5.value = (threshX > bankXStart + 2) ? x5.value : 0;
224 x6.value = (threshX > bankXStart + 3) ? x6.value : 0;
225 y3.value = (threshY > bankYStart) ? y3.value : 0;
226 y4.value = (threshY > bankYStart + 1) ? y4.value : 0;
227 y5.value = (threshY > bankYStart + 2) ? y5.value : 0;
228 y6.value = (threshY > bankYStart + 3) ? y6.value : 0;
229
230 switch (pTileInfo->banks)
231 {
232 case 16:
233 if (pTileInfo->macroAspectRatio == 1)
234 {
235 pEquation->addr[0] = y6;
236 pEquation->xor1[0] = x3;
237 pEquation->addr[1] = y5;
238 pEquation->xor1[1] = y6;
239 pEquation->xor2[1] = x4;
240 pEquation->addr[2] = y4;
241 pEquation->xor1[2] = x5;
242 pEquation->addr[3] = y3;
243 pEquation->xor1[3] = x6;
244 }
245 else if (pTileInfo->macroAspectRatio == 2)
246 {
247 pEquation->addr[0] = x3;
248 pEquation->xor1[0] = y6;
249 pEquation->addr[1] = y5;
250 pEquation->xor1[1] = y6;
251 pEquation->xor2[1] = x4;
252 pEquation->addr[2] = y4;
253 pEquation->xor1[2] = x5;
254 pEquation->addr[3] = y3;
255 pEquation->xor1[3] = x6;
256 }
257 else if (pTileInfo->macroAspectRatio == 4)
258 {
259 pEquation->addr[0] = x3;
260 pEquation->xor1[0] = y6;
261 pEquation->addr[1] = x4;
262 pEquation->xor1[1] = y5;
263 pEquation->xor2[1] = y6;
264 pEquation->addr[2] = y4;
265 pEquation->xor1[2] = x5;
266 pEquation->addr[3] = y3;
267 pEquation->xor1[3] = x6;
268 }
269 else if (pTileInfo->macroAspectRatio == 8)
270 {
271 pEquation->addr[0] = x3;
272 pEquation->xor1[0] = y6;
273 pEquation->addr[1] = x4;
274 pEquation->xor1[1] = y5;
275 pEquation->xor2[1] = y6;
276 pEquation->addr[2] = x5;
277 pEquation->xor1[2] = y4;
278 pEquation->addr[3] = y3;
279 pEquation->xor1[3] = x6;
280 }
281 else
282 {
283 ADDR_ASSERT_ALWAYS();
284 }
285 pEquation->numBits = 4;
286 break;
287 case 8:
288 if (pTileInfo->macroAspectRatio == 1)
289 {
290 pEquation->addr[0] = y5;
291 pEquation->xor1[0] = x3;
292 pEquation->addr[1] = y4;
293 pEquation->xor1[1] = y5;
294 pEquation->xor2[1] = x4;
295 pEquation->addr[2] = y3;
296 pEquation->xor1[2] = x5;
297 }
298 else if (pTileInfo->macroAspectRatio == 2)
299 {
300 pEquation->addr[0] = x3;
301 pEquation->xor1[0] = y5;
302 pEquation->addr[1] = y4;
303 pEquation->xor1[1] = y5;
304 pEquation->xor2[1] = x4;
305 pEquation->addr[2] = y3;
306 pEquation->xor1[2] = x5;
307 }
308 else if (pTileInfo->macroAspectRatio == 4)
309 {
310 pEquation->addr[0] = x3;
311 pEquation->xor1[0] = y5;
312 pEquation->addr[1] = x4;
313 pEquation->xor1[1] = y4;
314 pEquation->xor2[1] = y5;
315 pEquation->addr[2] = y3;
316 pEquation->xor1[2] = x5;
317 }
318 else
319 {
320 ADDR_ASSERT_ALWAYS();
321 }
322 pEquation->numBits = 3;
323 break;
324 case 4:
325 if (pTileInfo->macroAspectRatio == 1)
326 {
327 pEquation->addr[0] = y4;
328 pEquation->xor1[0] = x3;
329 pEquation->addr[1] = y3;
330 pEquation->xor1[1] = x4;
331 }
332 else if (pTileInfo->macroAspectRatio == 2)
333 {
334 pEquation->addr[0] = x3;
335 pEquation->xor1[0] = y4;
336 pEquation->addr[1] = y3;
337 pEquation->xor1[1] = x4;
338 }
339 else
340 {
341 pEquation->addr[0] = x3;
342 pEquation->xor1[0] = y4;
343 pEquation->addr[1] = x4;
344 pEquation->xor1[1] = y3;
345 }
346 pEquation->numBits = 2;
347 break;
348 case 2:
349 if (pTileInfo->macroAspectRatio == 1)
350 {
351 pEquation->addr[0] = y3;
352 pEquation->xor1[0] = x3;
353 }
354 else
355 {
356 pEquation->addr[0] = x3;
357 pEquation->xor1[0] = y3;
358 }
359 pEquation->numBits = 1;
360 break;
361 default:
362 pEquation->numBits = 0;
363 retCode = ADDR_NOTSUPPORTED;
364 ADDR_ASSERT_ALWAYS();
365 break;
366 }
367
368 for (UINT_32 i = 0; i < pEquation->numBits; i++)
369 {
370 if (pEquation->addr[i].value == 0)
371 {
372 if (pEquation->xor1[i].value == 0)
373 {
374 // 00X -> X00
375 pEquation->addr[i].value = pEquation->xor2[i].value;
376 pEquation->xor2[i].value = 0;
377 }
378 else
379 {
380 pEquation->addr[i].value = pEquation->xor1[i].value;
381
382 if (pEquation->xor2[i].value != 0)
383 {
384 // 0XY -> XY0
385 pEquation->xor1[i].value = pEquation->xor2[i].value;
386 pEquation->xor2[i].value = 0;
387 }
388 else
389 {
390 // 0X0 -> X00
391 pEquation->xor1[i].value = 0;
392 }
393 }
394 }
395 else if (pEquation->xor1[i].value == 0)
396 {
397 if (pEquation->xor2[i].value != 0)
398 {
399 // X0Y -> XY0
400 pEquation->xor1[i].value = pEquation->xor2[i].value;
401 pEquation->xor2[i].value = 0;
402 }
403 }
404 }
405 FillEqBitComponents(pEquation);
406
407 if ((pTileInfo->bankWidth == 1) &&
408 ((pTileInfo->pipeConfig == ADDR_PIPECFG_P4_32x32) ||
409 (pTileInfo->pipeConfig == ADDR_PIPECFG_P8_32x64_32x32)))
410 {
411 retCode = ADDR_NOTSUPPORTED;
412 }
413
414 return retCode;
415 }
416
417 /**
418 ****************************************************************************************************
419 * SiLib::ComputePipeEquation
420 *
421 * @brief
422 * Compute pipe equation
423 *
424 * @return
425 * If equation can be computed
426 ****************************************************************************************************
427 */
ComputePipeEquation(UINT_32 log2BytesPP,UINT_32 threshX,UINT_32 threshY,ADDR_TILEINFO * pTileInfo,ADDR_EQUATION * pEquation) const428 ADDR_E_RETURNCODE SiLib::ComputePipeEquation(
429 UINT_32 log2BytesPP, ///< [in] Log2 of bytes per pixel
430 UINT_32 threshX, ///< [in] Threshold for X channel
431 UINT_32 threshY, ///< [in] Threshold for Y channel
432 ADDR_TILEINFO* pTileInfo, ///< [in] Tile info
433 ADDR_EQUATION* pEquation ///< [out] Pipe configure
434 ) const
435 {
436 ADDR_E_RETURNCODE retCode = ADDR_OK;
437
438 ADDR_CHANNEL_SETTING* pAddr = pEquation->addr;
439 ADDR_CHANNEL_SETTING* pXor1 = pEquation->xor1;
440 ADDR_CHANNEL_SETTING* pXor2 = pEquation->xor2;
441
442 ADDR_CHANNEL_SETTING x3 = InitChannel(1, 0, 3 + log2BytesPP);
443 ADDR_CHANNEL_SETTING x4 = InitChannel(1, 0, 4 + log2BytesPP);
444 ADDR_CHANNEL_SETTING x5 = InitChannel(1, 0, 5 + log2BytesPP);
445 ADDR_CHANNEL_SETTING x6 = InitChannel(1, 0, 6 + log2BytesPP);
446 ADDR_CHANNEL_SETTING y3 = InitChannel(1, 1, 3);
447 ADDR_CHANNEL_SETTING y4 = InitChannel(1, 1, 4);
448 ADDR_CHANNEL_SETTING y5 = InitChannel(1, 1, 5);
449 ADDR_CHANNEL_SETTING y6 = InitChannel(1, 1, 6);
450
451 x3.value = (threshX > 3) ? x3.value : 0;
452 x4.value = (threshX > 4) ? x4.value : 0;
453 x5.value = (threshX > 5) ? x5.value : 0;
454 x6.value = (threshX > 6) ? x6.value : 0;
455 y3.value = (threshY > 3) ? y3.value : 0;
456 y4.value = (threshY > 4) ? y4.value : 0;
457 y5.value = (threshY > 5) ? y5.value : 0;
458 y6.value = (threshY > 6) ? y6.value : 0;
459
460 switch (pTileInfo->pipeConfig)
461 {
462 case ADDR_PIPECFG_P2:
463 pAddr[0] = x3;
464 pXor1[0] = y3;
465 pEquation->numBits = 1;
466 break;
467 case ADDR_PIPECFG_P4_8x16:
468 pAddr[0] = x4;
469 pXor1[0] = y3;
470 pAddr[1] = x3;
471 pXor1[1] = y4;
472 pEquation->numBits = 2;
473 break;
474 case ADDR_PIPECFG_P4_16x16:
475 pAddr[0] = x3;
476 pXor1[0] = y3;
477 pXor2[0] = x4;
478 pAddr[1] = x4;
479 pXor1[1] = y4;
480 pEquation->numBits = 2;
481 break;
482 case ADDR_PIPECFG_P4_16x32:
483 pAddr[0] = x3;
484 pXor1[0] = y3;
485 pXor2[0] = x4;
486 pAddr[1] = x4;
487 pXor1[1] = y5;
488 pEquation->numBits = 2;
489 break;
490 case ADDR_PIPECFG_P4_32x32:
491 pAddr[0] = x3;
492 pXor1[0] = y3;
493 pXor2[0] = x5;
494 pAddr[1] = x5;
495 pXor1[1] = y5;
496 pEquation->numBits = 2;
497 break;
498 case ADDR_PIPECFG_P8_16x16_8x16:
499 pAddr[0] = x4;
500 pXor1[0] = y3;
501 pXor2[0] = x5;
502 pAddr[1] = x3;
503 pXor1[1] = y5;
504 pEquation->numBits = 3;
505 break;
506 case ADDR_PIPECFG_P8_16x32_8x16:
507 pAddr[0] = x4;
508 pXor1[0] = y3;
509 pXor2[0] = x5;
510 pAddr[1] = x3;
511 pXor1[1] = y4;
512 pAddr[2] = x4;
513 pXor1[2] = y5;
514 pEquation->numBits = 3;
515 break;
516 case ADDR_PIPECFG_P8_16x32_16x16:
517 pAddr[0] = x3;
518 pXor1[0] = y3;
519 pXor2[0] = x4;
520 pAddr[1] = x5;
521 pXor1[1] = y4;
522 pAddr[2] = x4;
523 pXor1[2] = y5;
524 pEquation->numBits = 3;
525 break;
526 case ADDR_PIPECFG_P8_32x32_8x16:
527 pAddr[0] = x4;
528 pXor1[0] = y3;
529 pXor2[0] = x5;
530 pAddr[1] = x3;
531 pXor1[1] = y4;
532 pAddr[2] = x5;
533 pXor1[2] = y5;
534 pEquation->numBits = 3;
535 break;
536 case ADDR_PIPECFG_P8_32x32_16x16:
537 pAddr[0] = x3;
538 pXor1[0] = y3;
539 pXor2[0] = x4;
540 pAddr[1] = x4;
541 pXor1[1] = y4;
542 pAddr[2] = x5;
543 pXor1[2] = y5;
544 pEquation->numBits = 3;
545 break;
546 case ADDR_PIPECFG_P8_32x32_16x32:
547 pAddr[0] = x3;
548 pXor1[0] = y3;
549 pXor2[0] = x4;
550 pAddr[1] = x4;
551 pXor1[1] = y6;
552 pAddr[2] = x5;
553 pXor1[2] = y5;
554 pEquation->numBits = 3;
555 break;
556 case ADDR_PIPECFG_P8_32x64_32x32:
557 pAddr[0] = x3;
558 pXor1[0] = y3;
559 pXor2[0] = x5;
560 pAddr[1] = x6;
561 pXor1[1] = y5;
562 pAddr[2] = x5;
563 pXor1[2] = y6;
564 pEquation->numBits = 3;
565 break;
566 case ADDR_PIPECFG_P16_32x32_8x16:
567 pAddr[0] = x4;
568 pXor1[0] = y3;
569 pAddr[1] = x3;
570 pXor1[1] = y4;
571 pAddr[2] = x5;
572 pXor1[2] = y6;
573 pAddr[3] = x6;
574 pXor1[3] = y5;
575 pEquation->numBits = 4;
576 break;
577 case ADDR_PIPECFG_P16_32x32_16x16:
578 pAddr[0] = x3;
579 pXor1[0] = y3;
580 pXor2[0] = x4;
581 pAddr[1] = x4;
582 pXor1[1] = y4;
583 pAddr[2] = x5;
584 pXor1[2] = y6;
585 pAddr[3] = x6;
586 pXor1[3] = y5;
587 pEquation->numBits = 4;
588 break;
589 default:
590 ADDR_UNHANDLED_CASE();
591 pEquation->numBits = 0;
592 retCode = ADDR_NOTSUPPORTED;
593 break;
594 }
595
596 if (m_settings.isVegaM && (pEquation->numBits == 4))
597 {
598 ADDR_CHANNEL_SETTING addeMsb = pAddr[0];
599 ADDR_CHANNEL_SETTING xor1Msb = pXor1[0];
600 ADDR_CHANNEL_SETTING xor2Msb = pXor2[0];
601
602 pAddr[0] = pAddr[1];
603 pXor1[0] = pXor1[1];
604 pXor2[0] = pXor2[1];
605
606 pAddr[1] = pAddr[2];
607 pXor1[1] = pXor1[2];
608 pXor2[1] = pXor2[2];
609
610 pAddr[2] = pAddr[3];
611 pXor1[2] = pXor1[3];
612 pXor2[2] = pXor2[3];
613
614 pAddr[3] = addeMsb;
615 pXor1[3] = xor1Msb;
616 pXor2[3] = xor2Msb;
617 }
618
619 for (UINT_32 i = 0; i < pEquation->numBits; i++)
620 {
621 if (pAddr[i].value == 0)
622 {
623 if (pXor1[i].value == 0)
624 {
625 pAddr[i].value = pXor2[i].value;
626 }
627 else
628 {
629 pAddr[i].value = pXor1[i].value;
630 pXor1[i].value = 0;
631 }
632 }
633 }
634
635 return retCode;
636 }
637
638 /**
639 ****************************************************************************************************
640 * SiLib::ComputePipeFromCoord
641 *
642 * @brief
643 * Compute pipe number from coordinates
644 * @return
645 * Pipe number
646 ****************************************************************************************************
647 */
ComputePipeFromCoord(UINT_32 x,UINT_32 y,UINT_32 slice,AddrTileMode tileMode,UINT_32 pipeSwizzle,BOOL_32 ignoreSE,ADDR_TILEINFO * pTileInfo) const648 UINT_32 SiLib::ComputePipeFromCoord(
649 UINT_32 x, ///< [in] x coordinate
650 UINT_32 y, ///< [in] y coordinate
651 UINT_32 slice, ///< [in] slice index
652 AddrTileMode tileMode, ///< [in] tile mode
653 UINT_32 pipeSwizzle, ///< [in] pipe swizzle
654 BOOL_32 ignoreSE, ///< [in] TRUE if shader engines are ignored
655 ADDR_TILEINFO* pTileInfo ///< [in] Tile info
656 ) const
657 {
658 UINT_32 pipe;
659 UINT_32 pipeBit0 = 0;
660 UINT_32 pipeBit1 = 0;
661 UINT_32 pipeBit2 = 0;
662 UINT_32 pipeBit3 = 0;
663 UINT_32 sliceRotation;
664 UINT_32 numPipes = 0;
665
666 UINT_32 tx = x / MicroTileWidth;
667 UINT_32 ty = y / MicroTileHeight;
668 UINT_32 x3 = _BIT(tx,0);
669 UINT_32 x4 = _BIT(tx,1);
670 UINT_32 x5 = _BIT(tx,2);
671 UINT_32 x6 = _BIT(tx,3);
672 UINT_32 y3 = _BIT(ty,0);
673 UINT_32 y4 = _BIT(ty,1);
674 UINT_32 y5 = _BIT(ty,2);
675 UINT_32 y6 = _BIT(ty,3);
676
677 switch (pTileInfo->pipeConfig)
678 {
679 case ADDR_PIPECFG_P2:
680 pipeBit0 = x3 ^ y3;
681 numPipes = 2;
682 break;
683 case ADDR_PIPECFG_P4_8x16:
684 pipeBit0 = x4 ^ y3;
685 pipeBit1 = x3 ^ y4;
686 numPipes = 4;
687 break;
688 case ADDR_PIPECFG_P4_16x16:
689 pipeBit0 = x3 ^ y3 ^ x4;
690 pipeBit1 = x4 ^ y4;
691 numPipes = 4;
692 break;
693 case ADDR_PIPECFG_P4_16x32:
694 pipeBit0 = x3 ^ y3 ^ x4;
695 pipeBit1 = x4 ^ y5;
696 numPipes = 4;
697 break;
698 case ADDR_PIPECFG_P4_32x32:
699 pipeBit0 = x3 ^ y3 ^ x5;
700 pipeBit1 = x5 ^ y5;
701 numPipes = 4;
702 break;
703 case ADDR_PIPECFG_P8_16x16_8x16:
704 pipeBit0 = x4 ^ y3 ^ x5;
705 pipeBit1 = x3 ^ y5;
706 numPipes = 8;
707 break;
708 case ADDR_PIPECFG_P8_16x32_8x16:
709 pipeBit0 = x4 ^ y3 ^ x5;
710 pipeBit1 = x3 ^ y4;
711 pipeBit2 = x4 ^ y5;
712 numPipes = 8;
713 break;
714 case ADDR_PIPECFG_P8_16x32_16x16:
715 pipeBit0 = x3 ^ y3 ^ x4;
716 pipeBit1 = x5 ^ y4;
717 pipeBit2 = x4 ^ y5;
718 numPipes = 8;
719 break;
720 case ADDR_PIPECFG_P8_32x32_8x16:
721 pipeBit0 = x4 ^ y3 ^ x5;
722 pipeBit1 = x3 ^ y4;
723 pipeBit2 = x5 ^ y5;
724 numPipes = 8;
725 break;
726 case ADDR_PIPECFG_P8_32x32_16x16:
727 pipeBit0 = x3 ^ y3 ^ x4;
728 pipeBit1 = x4 ^ y4;
729 pipeBit2 = x5 ^ y5;
730 numPipes = 8;
731 break;
732 case ADDR_PIPECFG_P8_32x32_16x32:
733 pipeBit0 = x3 ^ y3 ^ x4;
734 pipeBit1 = x4 ^ y6;
735 pipeBit2 = x5 ^ y5;
736 numPipes = 8;
737 break;
738 case ADDR_PIPECFG_P8_32x64_32x32:
739 pipeBit0 = x3 ^ y3 ^ x5;
740 pipeBit1 = x6 ^ y5;
741 pipeBit2 = x5 ^ y6;
742 numPipes = 8;
743 break;
744 case ADDR_PIPECFG_P16_32x32_8x16:
745 pipeBit0 = x4 ^ y3;
746 pipeBit1 = x3 ^ y4;
747 pipeBit2 = x5 ^ y6;
748 pipeBit3 = x6 ^ y5;
749 numPipes = 16;
750 break;
751 case ADDR_PIPECFG_P16_32x32_16x16:
752 pipeBit0 = x3 ^ y3 ^ x4;
753 pipeBit1 = x4 ^ y4;
754 pipeBit2 = x5 ^ y6;
755 pipeBit3 = x6 ^ y5;
756 numPipes = 16;
757 break;
758 default:
759 ADDR_UNHANDLED_CASE();
760 break;
761 }
762
763 if (m_settings.isVegaM && (numPipes == 16))
764 {
765 UINT_32 pipeMsb = pipeBit0;
766 pipeBit0 = pipeBit1;
767 pipeBit1 = pipeBit2;
768 pipeBit2 = pipeBit3;
769 pipeBit3 = pipeMsb;
770 }
771
772 pipe = pipeBit0 | (pipeBit1 << 1) | (pipeBit2 << 2) | (pipeBit3 << 3);
773
774 UINT_32 microTileThickness = Thickness(tileMode);
775
776 //
777 // Apply pipe rotation for the slice.
778 //
779 switch (tileMode)
780 {
781 case ADDR_TM_3D_TILED_THIN1: //fall through thin
782 case ADDR_TM_3D_TILED_THICK: //fall through thick
783 case ADDR_TM_3D_TILED_XTHICK:
784 sliceRotation =
785 Max(1, static_cast<INT_32>(numPipes / 2) - 1) * (slice / microTileThickness);
786 break;
787 default:
788 sliceRotation = 0;
789 break;
790 }
791 pipeSwizzle += sliceRotation;
792 pipeSwizzle &= (numPipes - 1);
793
794 pipe = pipe ^ pipeSwizzle;
795
796 return pipe;
797 }
798
799 /**
800 ****************************************************************************************************
801 * SiLib::ComputeTileCoordFromPipeAndElemIdx
802 *
803 * @brief
804 * Compute (x,y) of a tile within a macro tile from address
805 * @return
806 * Pipe number
807 ****************************************************************************************************
808 */
ComputeTileCoordFromPipeAndElemIdx(UINT_32 elemIdx,UINT_32 pipe,AddrPipeCfg pipeCfg,UINT_32 pitchInMacroTile,UINT_32 x,UINT_32 y,UINT_32 * pX,UINT_32 * pY) const809 VOID SiLib::ComputeTileCoordFromPipeAndElemIdx(
810 UINT_32 elemIdx, ///< [in] per pipe element index within a macro tile
811 UINT_32 pipe, ///< [in] pipe index
812 AddrPipeCfg pipeCfg, ///< [in] pipe config
813 UINT_32 pitchInMacroTile, ///< [in] surface pitch in macro tile
814 UINT_32 x, ///< [in] x coordinate of the (0,0) tile in a macro tile
815 UINT_32 y, ///< [in] y coordinate of the (0,0) tile in a macro tile
816 UINT_32* pX, ///< [out] x coordinate
817 UINT_32* pY ///< [out] y coordinate
818 ) const
819 {
820 UINT_32 pipebit0 = _BIT(pipe,0);
821 UINT_32 pipebit1 = _BIT(pipe,1);
822 UINT_32 pipebit2 = _BIT(pipe,2);
823 UINT_32 pipebit3 = _BIT(pipe,3);
824 UINT_32 elemIdx0 = _BIT(elemIdx,0);
825 UINT_32 elemIdx1 = _BIT(elemIdx,1);
826 UINT_32 elemIdx2 = _BIT(elemIdx,2);
827 UINT_32 x3 = 0;
828 UINT_32 x4 = 0;
829 UINT_32 x5 = 0;
830 UINT_32 x6 = 0;
831 UINT_32 y3 = 0;
832 UINT_32 y4 = 0;
833 UINT_32 y5 = 0;
834 UINT_32 y6 = 0;
835
836 switch(pipeCfg)
837 {
838 case ADDR_PIPECFG_P2:
839 x4 = elemIdx2;
840 y4 = elemIdx1 ^ x4;
841 y3 = elemIdx0 ^ x4;
842 x3 = pipebit0 ^ y3;
843 *pY = Bits2Number(2, y4, y3);
844 *pX = Bits2Number(2, x4, x3);
845 break;
846 case ADDR_PIPECFG_P4_8x16:
847 x4 = elemIdx1;
848 y4 = elemIdx0 ^ x4;
849 x3 = pipebit1 ^ y4;
850 y3 = pipebit0 ^ x4;
851 *pY = Bits2Number(2, y4, y3);
852 *pX = Bits2Number(2, x4, x3);
853 break;
854 case ADDR_PIPECFG_P4_16x16:
855 x4 = elemIdx1;
856 y3 = elemIdx0 ^ x4;
857 y4 = pipebit1 ^ x4;
858 x3 = pipebit0 ^ y3 ^ x4;
859 *pY = Bits2Number(2, y4, y3);
860 *pX = Bits2Number(2, x4, x3);
861 break;
862 case ADDR_PIPECFG_P4_16x32:
863 x3 = elemIdx0 ^ pipebit0;
864 y5 = _BIT(y,5);
865 x4 = pipebit1 ^ y5;
866 y3 = pipebit0 ^ x3 ^ x4;
867 y4 = elemIdx1 ^ x4;
868 *pY = Bits2Number(2, y4, y3);
869 *pX = Bits2Number(2, x4, x3);
870 break;
871 case ADDR_PIPECFG_P4_32x32:
872 x4 = elemIdx2;
873 y3 = elemIdx0 ^ x4;
874 y4 = elemIdx1 ^ x4;
875 if((pitchInMacroTile % 2) == 0)
876 { //even
877 y5 = _BIT(y,5);
878 x5 = pipebit1 ^ y5;
879 x3 = pipebit0 ^ y3 ^ x5;
880 *pY = Bits2Number(2, y4, y3);
881 *pX = Bits2Number(3, x5, x4, x3);
882 }
883 else
884 { //odd
885 x5 = _BIT(x,5);
886 x3 = pipebit0 ^ y3 ^ x5;
887 *pY = Bits2Number(2, y4, y3);
888 *pX = Bits2Number(2, x4, x3);
889 }
890 break;
891 case ADDR_PIPECFG_P8_16x16_8x16:
892 x4 = elemIdx0;
893 y5 = _BIT(y,5);
894 x5 = _BIT(x,5);
895 x3 = pipebit1 ^ y5;
896 y4 = pipebit2 ^ x4;
897 y3 = pipebit0 ^ x5 ^ x4;
898 *pY = Bits2Number(2, y4, y3);
899 *pX = Bits2Number(2, x4, x3);
900 break;
901 case ADDR_PIPECFG_P8_16x32_8x16:
902 x3 = elemIdx0;
903 y4 = pipebit1 ^ x3;
904 y5 = _BIT(y,5);
905 x5 = _BIT(x,5);
906 x4 = pipebit2 ^ y5;
907 y3 = pipebit0 ^ x4 ^ x5;
908 *pY = Bits2Number(2, y4, y3);
909 *pX = Bits2Number(2, x4, x3);
910 break;
911 case ADDR_PIPECFG_P8_32x32_8x16:
912 x4 = elemIdx1;
913 y4 = elemIdx0 ^ x4;
914 x3 = pipebit1 ^ y4;
915 if((pitchInMacroTile % 2) == 0)
916 { //even
917 y5 = _BIT(y,5);
918 x5 = _BIT(x,5);
919 x5 = pipebit2 ^ y5;
920 y3 = pipebit0 ^ x4 ^ x5;
921 *pY = Bits2Number(2, y4, y3);
922 *pX = Bits2Number(3, x5, x4, x3);
923 }
924 else
925 { //odd
926 x5 = _BIT(x,5);
927 y3 = pipebit0 ^ x4 ^ x5;
928 *pY = Bits2Number(2, y4, y3);
929 *pX = Bits2Number(2, x4, x3);
930 }
931 break;
932 case ADDR_PIPECFG_P8_16x32_16x16:
933 x3 = elemIdx0;
934 x5 = _BIT(x,5);
935 y5 = _BIT(y,5);
936 x4 = pipebit2 ^ y5;
937 y4 = pipebit1 ^ x5;
938 y3 = pipebit0 ^ x3 ^ x4;
939 *pY = Bits2Number(2, y4, y3);
940 *pX = Bits2Number(2, x4, x3);
941 break;
942 case ADDR_PIPECFG_P8_32x32_16x16:
943 x4 = elemIdx1;
944 y3 = elemIdx0 ^ x4;
945 x3 = y3^x4^pipebit0;
946 y4 = pipebit1 ^ x4;
947 if((pitchInMacroTile % 2) == 0)
948 { //even
949 y5 = _BIT(y,5);
950 x5 = pipebit2 ^ y5;
951 *pY = Bits2Number(2, y4, y3);
952 *pX = Bits2Number(3, x5, x4, x3);
953 }
954 else
955 { //odd
956 *pY = Bits2Number(2, y4, y3);
957 *pX = Bits2Number(2, x4, x3);
958 }
959 break;
960 case ADDR_PIPECFG_P8_32x32_16x32:
961 if((pitchInMacroTile % 2) == 0)
962 { //even
963 y5 = _BIT(y,5);
964 y6 = _BIT(y,6);
965 x4 = pipebit1 ^ y6;
966 y3 = elemIdx0 ^ x4;
967 y4 = elemIdx1 ^ x4;
968 x3 = pipebit0 ^ y3 ^ x4;
969 x5 = pipebit2 ^ y5;
970 *pY = Bits2Number(2, y4, y3);
971 *pX = Bits2Number(3, x5, x4, x3);
972 }
973 else
974 { //odd
975 y6 = _BIT(y,6);
976 x4 = pipebit1 ^ y6;
977 y3 = elemIdx0 ^ x4;
978 y4 = elemIdx1 ^ x4;
979 x3 = pipebit0 ^ y3 ^ x4;
980 *pY = Bits2Number(2, y4, y3);
981 *pX = Bits2Number(2, x4, x3);
982 }
983 break;
984 case ADDR_PIPECFG_P8_32x64_32x32:
985 x4 = elemIdx2;
986 y3 = elemIdx0 ^ x4;
987 y4 = elemIdx1 ^ x4;
988 if((pitchInMacroTile % 4) == 0)
989 { //multiple of 4
990 y5 = _BIT(y,5);
991 y6 = _BIT(y,6);
992 x5 = pipebit2 ^ y6;
993 x6 = pipebit1 ^ y5;
994 x3 = pipebit0 ^ y3 ^ x5;
995 *pY = Bits2Number(2, y4, y3);
996 *pX = Bits2Number(4, x6, x5, x4, x3);
997 }
998 else
999 {
1000 y6 = _BIT(y,6);
1001 x5 = pipebit2 ^ y6;
1002 x3 = pipebit0 ^ y3 ^ x5;
1003 *pY = Bits2Number(2, y4, y3);
1004 *pX = Bits2Number(3, x5, x4, x3);
1005 }
1006 break;
1007 case ADDR_PIPECFG_P16_32x32_8x16:
1008 x4 = elemIdx1;
1009 y4 = elemIdx0 ^ x4;
1010 y3 = pipebit0 ^ x4;
1011 x3 = pipebit1 ^ y4;
1012 if((pitchInMacroTile % 4) == 0)
1013 { //multiple of 4
1014 y5 = _BIT(y,5);
1015 y6 = _BIT(y,6);
1016 x5 = pipebit2 ^ y6;
1017 x6 = pipebit3 ^ y5;
1018 *pY = Bits2Number(2, y4, y3);
1019 *pX = Bits2Number(4, x6, x5,x4, x3);
1020 }
1021 else
1022 {
1023 y6 = _BIT(y,6);
1024 x5 = pipebit2 ^ y6;
1025 *pY = Bits2Number(2, y4, y3);
1026 *pX = Bits2Number(3, x5, x4, x3);
1027 }
1028 break;
1029 case ADDR_PIPECFG_P16_32x32_16x16:
1030 x4 = elemIdx1;
1031 y3 = elemIdx0 ^ x4;
1032 y4 = pipebit1 ^ x4;
1033 x3 = pipebit0 ^ y3 ^ x4;
1034 if((pitchInMacroTile % 4) == 0)
1035 { //multiple of 4
1036 y5 = _BIT(y,5);
1037 y6 = _BIT(y,6);
1038 x5 = pipebit2 ^ y6;
1039 x6 = pipebit3 ^ y5;
1040 *pY = Bits2Number(2, y4, y3);
1041 *pX = Bits2Number(4, x6, x5, x4, x3);
1042 }
1043 else
1044 {
1045 y6 = _BIT(y,6);
1046 x5 = pipebit2 ^ y6;
1047 *pY = Bits2Number(2, y4, y3);
1048 *pX = Bits2Number(3, x5, x4, x3);
1049 }
1050 break;
1051 default:
1052 ADDR_UNHANDLED_CASE();
1053 }
1054 }
1055
1056 /**
1057 ****************************************************************************************************
1058 * SiLib::TileCoordToMaskElementIndex
1059 *
1060 * @brief
1061 * Compute element index from coordinates in tiles
1062 * @return
1063 * Element index
1064 ****************************************************************************************************
1065 */
TileCoordToMaskElementIndex(UINT_32 tx,UINT_32 ty,AddrPipeCfg pipeConfig,UINT_32 * macroShift,UINT_32 * elemIdxBits) const1066 UINT_32 SiLib::TileCoordToMaskElementIndex(
1067 UINT_32 tx, ///< [in] x coord, in Tiles
1068 UINT_32 ty, ///< [in] y coord, in Tiles
1069 AddrPipeCfg pipeConfig, ///< [in] pipe config
1070 UINT_32* macroShift, ///< [out] macro shift
1071 UINT_32* elemIdxBits ///< [out] tile offset bits
1072 ) const
1073 {
1074 UINT_32 elemIdx = 0;
1075 UINT_32 elemIdx0, elemIdx1, elemIdx2;
1076 UINT_32 tx0, tx1;
1077 UINT_32 ty0, ty1;
1078
1079 tx0 = _BIT(tx,0);
1080 tx1 = _BIT(tx,1);
1081 ty0 = _BIT(ty,0);
1082 ty1 = _BIT(ty,1);
1083
1084 switch(pipeConfig)
1085 {
1086 case ADDR_PIPECFG_P2:
1087 *macroShift = 3;
1088 *elemIdxBits =3;
1089 elemIdx2 = tx1;
1090 elemIdx1 = tx1 ^ ty1;
1091 elemIdx0 = tx1 ^ ty0;
1092 elemIdx = Bits2Number(3,elemIdx2,elemIdx1,elemIdx0);
1093 break;
1094 case ADDR_PIPECFG_P4_8x16:
1095 *macroShift = 2;
1096 *elemIdxBits =2;
1097 elemIdx1 = tx1;
1098 elemIdx0 = tx1 ^ ty1;
1099 elemIdx = Bits2Number(2,elemIdx1,elemIdx0);
1100 break;
1101 case ADDR_PIPECFG_P4_16x16:
1102 *macroShift = 2;
1103 *elemIdxBits =2;
1104 elemIdx0 = tx1^ty0;
1105 elemIdx1 = tx1;
1106 elemIdx = Bits2Number(2, elemIdx1, elemIdx0);
1107 break;
1108 case ADDR_PIPECFG_P4_16x32:
1109 *macroShift = 2;
1110 *elemIdxBits =2;
1111 elemIdx0 = tx1^ty0;
1112 elemIdx1 = tx1^ty1;
1113 elemIdx = Bits2Number(2, elemIdx1, elemIdx0);
1114 break;
1115 case ADDR_PIPECFG_P4_32x32:
1116 *macroShift = 2;
1117 *elemIdxBits =3;
1118 elemIdx0 = tx1^ty0;
1119 elemIdx1 = tx1^ty1;
1120 elemIdx2 = tx1;
1121 elemIdx = Bits2Number(3, elemIdx2, elemIdx1, elemIdx0);
1122 break;
1123 case ADDR_PIPECFG_P8_16x16_8x16:
1124 *macroShift = 1;
1125 *elemIdxBits =1;
1126 elemIdx0 = tx1;
1127 elemIdx = elemIdx0;
1128 break;
1129 case ADDR_PIPECFG_P8_16x32_8x16:
1130 *macroShift = 1;
1131 *elemIdxBits =1;
1132 elemIdx0 = tx0;
1133 elemIdx = elemIdx0;
1134 break;
1135 case ADDR_PIPECFG_P8_32x32_8x16:
1136 *macroShift = 1;
1137 *elemIdxBits =2;
1138 elemIdx1 = tx1;
1139 elemIdx0 = tx1^ty1;
1140 elemIdx = Bits2Number(2, elemIdx1, elemIdx0);
1141 break;
1142 case ADDR_PIPECFG_P8_16x32_16x16:
1143 *macroShift = 1;
1144 *elemIdxBits =1;
1145 elemIdx0 = tx0;
1146 elemIdx = elemIdx0;
1147 break;
1148 case ADDR_PIPECFG_P8_32x32_16x16:
1149 *macroShift = 1;
1150 *elemIdxBits =2;
1151 elemIdx0 = tx1^ty0;
1152 elemIdx1 = tx1;
1153 elemIdx = Bits2Number(2, elemIdx1, elemIdx0);
1154 break;
1155 case ADDR_PIPECFG_P8_32x32_16x32:
1156 *macroShift = 1;
1157 *elemIdxBits =2;
1158 elemIdx0 = tx1^ty0;
1159 elemIdx1 = tx1^ty1;
1160 elemIdx = Bits2Number(2, elemIdx1, elemIdx0);
1161 break;
1162 case ADDR_PIPECFG_P8_32x64_32x32:
1163 *macroShift = 1;
1164 *elemIdxBits =3;
1165 elemIdx0 = tx1^ty0;
1166 elemIdx1 = tx1^ty1;
1167 elemIdx2 = tx1;
1168 elemIdx = Bits2Number(3, elemIdx2, elemIdx1, elemIdx0);
1169 break;
1170 case ADDR_PIPECFG_P16_32x32_8x16:
1171 *macroShift = 0;
1172 *elemIdxBits =2;
1173 elemIdx0 = tx1^ty1;
1174 elemIdx1 = tx1;
1175 elemIdx = Bits2Number(2, elemIdx1, elemIdx0);
1176 break;
1177 case ADDR_PIPECFG_P16_32x32_16x16:
1178 *macroShift = 0;
1179 *elemIdxBits =2;
1180 elemIdx0 = tx1^ty0;
1181 elemIdx1 = tx1;
1182 elemIdx = Bits2Number(2, elemIdx1, elemIdx0);
1183 break;
1184 default:
1185 ADDR_UNHANDLED_CASE();
1186 break;
1187 }
1188
1189 return elemIdx;
1190 }
1191
1192 /**
1193 ****************************************************************************************************
1194 * SiLib::HwlComputeTileDataWidthAndHeightLinear
1195 *
1196 * @brief
1197 * Compute the squared cache shape for per-tile data (CMASK and HTILE) for linear layout
1198 *
1199 * @return
1200 * N/A
1201 *
1202 * @note
1203 * MacroWidth and macroHeight are measured in pixels
1204 ****************************************************************************************************
1205 */
HwlComputeTileDataWidthAndHeightLinear(UINT_32 * pMacroWidth,UINT_32 * pMacroHeight,UINT_32 bpp,ADDR_TILEINFO * pTileInfo) const1206 VOID SiLib::HwlComputeTileDataWidthAndHeightLinear(
1207 UINT_32* pMacroWidth, ///< [out] macro tile width
1208 UINT_32* pMacroHeight, ///< [out] macro tile height
1209 UINT_32 bpp, ///< [in] bits per pixel
1210 ADDR_TILEINFO* pTileInfo ///< [in] tile info
1211 ) const
1212 {
1213 ADDR_ASSERT(pTileInfo != NULL);
1214 UINT_32 macroWidth;
1215 UINT_32 macroHeight;
1216
1217 /// In linear mode, the htile or cmask buffer must be padded out to 4 tiles
1218 /// but for P8_32x64_32x32, it must be padded out to 8 tiles
1219 /// Actually there are more pipe configs which need 8-tile padding but SI family
1220 /// has a bug which is fixed in CI family
1221 if ((pTileInfo->pipeConfig == ADDR_PIPECFG_P8_32x64_32x32) ||
1222 (pTileInfo->pipeConfig == ADDR_PIPECFG_P16_32x32_8x16) ||
1223 (pTileInfo->pipeConfig == ADDR_PIPECFG_P8_32x32_16x16))
1224 {
1225 macroWidth = 8*MicroTileWidth;
1226 macroHeight = 8*MicroTileHeight;
1227 }
1228 else
1229 {
1230 macroWidth = 4*MicroTileWidth;
1231 macroHeight = 4*MicroTileHeight;
1232 }
1233
1234 *pMacroWidth = macroWidth;
1235 *pMacroHeight = macroHeight;
1236 }
1237
1238 /**
1239 ****************************************************************************************************
1240 * SiLib::HwlComputeHtileBytes
1241 *
1242 * @brief
1243 * Compute htile size in bytes
1244 *
1245 * @return
1246 * Htile size in bytes
1247 ****************************************************************************************************
1248 */
HwlComputeHtileBytes(UINT_32 pitch,UINT_32 height,UINT_32 bpp,BOOL_32 isLinear,UINT_32 numSlices,UINT_64 * pSliceBytes,UINT_32 baseAlign) const1249 UINT_64 SiLib::HwlComputeHtileBytes(
1250 UINT_32 pitch, ///< [in] pitch
1251 UINT_32 height, ///< [in] height
1252 UINT_32 bpp, ///< [in] bits per pixel
1253 BOOL_32 isLinear, ///< [in] if it is linear mode
1254 UINT_32 numSlices, ///< [in] number of slices
1255 UINT_64* pSliceBytes, ///< [out] bytes per slice
1256 UINT_32 baseAlign ///< [in] base alignments
1257 ) const
1258 {
1259 return ComputeHtileBytes(pitch, height, bpp, isLinear, numSlices, pSliceBytes, baseAlign);
1260 }
1261
1262 /**
1263 ****************************************************************************************************
1264 * SiLib::HwlComputeXmaskAddrFromCoord
1265 *
1266 * @brief
1267 * Compute address from coordinates for htile/cmask
1268 * @return
1269 * Byte address
1270 ****************************************************************************************************
1271 */
HwlComputeXmaskAddrFromCoord(UINT_32 pitch,UINT_32 height,UINT_32 x,UINT_32 y,UINT_32 slice,UINT_32 numSlices,UINT_32 factor,BOOL_32 isLinear,BOOL_32 isWidth8,BOOL_32 isHeight8,ADDR_TILEINFO * pTileInfo,UINT_32 * pBitPosition) const1272 UINT_64 SiLib::HwlComputeXmaskAddrFromCoord(
1273 UINT_32 pitch, ///< [in] pitch
1274 UINT_32 height, ///< [in] height
1275 UINT_32 x, ///< [in] x coord
1276 UINT_32 y, ///< [in] y coord
1277 UINT_32 slice, ///< [in] slice/depth index
1278 UINT_32 numSlices, ///< [in] number of slices
1279 UINT_32 factor, ///< [in] factor that indicates cmask(2) or htile(1)
1280 BOOL_32 isLinear, ///< [in] linear or tiled HTILE layout
1281 BOOL_32 isWidth8, ///< [in] TRUE if width is 8, FALSE means 4. It's register value
1282 BOOL_32 isHeight8, ///< [in] TRUE if width is 8, FALSE means 4. It's register value
1283 ADDR_TILEINFO* pTileInfo, ///< [in] Tile info
1284 UINT_32* pBitPosition ///< [out] bit position inside a byte
1285 ) const
1286 {
1287 UINT_32 tx = x / MicroTileWidth;
1288 UINT_32 ty = y / MicroTileHeight;
1289 UINT_32 newPitch;
1290 UINT_32 newHeight;
1291 UINT_64 totalBytes;
1292 UINT_32 macroWidth;
1293 UINT_32 macroHeight;
1294 UINT_64 pSliceBytes;
1295 UINT_32 pBaseAlign;
1296 UINT_32 tileNumPerPipe;
1297 UINT_32 elemBits;
1298
1299 if (factor == 2) //CMASK
1300 {
1301 ADDR_CMASK_FLAGS flags = {{0}};
1302
1303 tileNumPerPipe = 256;
1304
1305 ComputeCmaskInfo(flags,
1306 pitch,
1307 height,
1308 numSlices,
1309 isLinear,
1310 pTileInfo,
1311 &newPitch,
1312 &newHeight,
1313 &totalBytes,
1314 ¯oWidth,
1315 ¯oHeight);
1316 elemBits = CmaskElemBits;
1317 }
1318 else //HTile
1319 {
1320 ADDR_HTILE_FLAGS flags = {{0}};
1321
1322 tileNumPerPipe = 512;
1323
1324 ComputeHtileInfo(flags,
1325 pitch,
1326 height,
1327 numSlices,
1328 isLinear,
1329 TRUE,
1330 TRUE,
1331 pTileInfo,
1332 &newPitch,
1333 &newHeight,
1334 &totalBytes,
1335 ¯oWidth,
1336 ¯oHeight,
1337 &pSliceBytes,
1338 &pBaseAlign);
1339 elemBits = 32;
1340 }
1341
1342 const UINT_32 pitchInTile = newPitch / MicroTileWidth;
1343 const UINT_32 heightInTile = newHeight / MicroTileWidth;
1344 UINT_64 macroOffset; // Per pipe starting offset of the macro tile in which this tile lies.
1345 UINT_64 microNumber; // Per pipe starting offset of the macro tile in which this tile lies.
1346 UINT_32 microX;
1347 UINT_32 microY;
1348 UINT_64 microOffset;
1349 UINT_32 microShift;
1350 UINT_64 totalOffset;
1351 UINT_32 elemIdxBits;
1352 UINT_32 elemIdx =
1353 TileCoordToMaskElementIndex(tx, ty, pTileInfo->pipeConfig, µShift, &elemIdxBits);
1354
1355 UINT_32 numPipes = HwlGetPipes(pTileInfo);
1356
1357 if (isLinear)
1358 { //linear addressing
1359 // Linear addressing is extremelly wasting memory if slice > 1, since each pipe has the full
1360 // slice memory foot print instead of divided by numPipes.
1361 microX = tx / 4; // Macro Tile is 4x4
1362 microY = ty / 4 ;
1363 microNumber = static_cast<UINT_64>(microX + microY * (pitchInTile / 4)) << microShift;
1364
1365 UINT_32 sliceBits = pitchInTile * heightInTile;
1366
1367 // do htile single slice alignment if the flag is true
1368 if (m_configFlags.useHtileSliceAlign && (factor == 1)) //Htile
1369 {
1370 sliceBits = PowTwoAlign(sliceBits, BITS_TO_BYTES(HtileCacheBits) * numPipes / elemBits);
1371 }
1372 macroOffset = slice * (sliceBits / numPipes) * elemBits ;
1373 }
1374 else
1375 { //tiled addressing
1376 const UINT_32 macroWidthInTile = macroWidth / MicroTileWidth; // Now in unit of Tiles
1377 const UINT_32 macroHeightInTile = macroHeight / MicroTileHeight;
1378 const UINT_32 pitchInCL = pitchInTile / macroWidthInTile;
1379 const UINT_32 heightInCL = heightInTile / macroHeightInTile;
1380
1381 const UINT_32 macroX = x / macroWidth;
1382 const UINT_32 macroY = y / macroHeight;
1383 const UINT_32 macroNumber = macroX + macroY * pitchInCL + slice * pitchInCL * heightInCL;
1384
1385 // Per pipe starting offset of the cache line in which this tile lies.
1386 microX = (x % macroWidth) / MicroTileWidth / 4; // Macro Tile is 4x4
1387 microY = (y % macroHeight) / MicroTileHeight / 4 ;
1388 microNumber = static_cast<UINT_64>(microX + microY * (macroWidth / MicroTileWidth / 4)) << microShift;
1389
1390 macroOffset = macroNumber * tileNumPerPipe * elemBits;
1391 }
1392
1393 if(elemIdxBits == microShift)
1394 {
1395 microNumber += elemIdx;
1396 }
1397 else
1398 {
1399 microNumber >>= elemIdxBits;
1400 microNumber <<= elemIdxBits;
1401 microNumber += elemIdx;
1402 }
1403
1404 microOffset = elemBits * microNumber;
1405 totalOffset = microOffset + macroOffset;
1406
1407 UINT_32 pipe = ComputePipeFromCoord(x, y, 0, ADDR_TM_2D_TILED_THIN1, 0, FALSE, pTileInfo);
1408 UINT_64 addrInBits = totalOffset % (m_pipeInterleaveBytes * 8) +
1409 pipe * (m_pipeInterleaveBytes * 8) +
1410 totalOffset / (m_pipeInterleaveBytes * 8) * (m_pipeInterleaveBytes * 8) * numPipes;
1411 *pBitPosition = static_cast<UINT_32>(addrInBits) % 8;
1412 UINT_64 addr = addrInBits / 8;
1413
1414 return addr;
1415 }
1416
1417 /**
1418 ****************************************************************************************************
1419 * SiLib::HwlComputeXmaskCoordFromAddr
1420 *
1421 * @brief
1422 * Compute the coord from an address of a cmask/htile
1423 *
1424 * @return
1425 * N/A
1426 *
1427 * @note
1428 * This method is reused by htile, so rename to Xmask
1429 ****************************************************************************************************
1430 */
HwlComputeXmaskCoordFromAddr(UINT_64 addr,UINT_32 bitPosition,UINT_32 pitch,UINT_32 height,UINT_32 numSlices,UINT_32 factor,BOOL_32 isLinear,BOOL_32 isWidth8,BOOL_32 isHeight8,ADDR_TILEINFO * pTileInfo,UINT_32 * pX,UINT_32 * pY,UINT_32 * pSlice) const1431 VOID SiLib::HwlComputeXmaskCoordFromAddr(
1432 UINT_64 addr, ///< [in] address
1433 UINT_32 bitPosition, ///< [in] bitPosition in a byte
1434 UINT_32 pitch, ///< [in] pitch
1435 UINT_32 height, ///< [in] height
1436 UINT_32 numSlices, ///< [in] number of slices
1437 UINT_32 factor, ///< [in] factor that indicates cmask or htile
1438 BOOL_32 isLinear, ///< [in] linear or tiled HTILE layout
1439 BOOL_32 isWidth8, ///< [in] Not used by SI
1440 BOOL_32 isHeight8, ///< [in] Not used by SI
1441 ADDR_TILEINFO* pTileInfo, ///< [in] Tile info
1442 UINT_32* pX, ///< [out] x coord
1443 UINT_32* pY, ///< [out] y coord
1444 UINT_32* pSlice ///< [out] slice index
1445 ) const
1446 {
1447 UINT_32 newPitch;
1448 UINT_32 newHeight;
1449 UINT_64 totalBytes;
1450 UINT_32 clWidth;
1451 UINT_32 clHeight;
1452 UINT_32 tileNumPerPipe;
1453 UINT_64 sliceBytes;
1454
1455 *pX = 0;
1456 *pY = 0;
1457 *pSlice = 0;
1458
1459 if (factor == 2) //CMASK
1460 {
1461 ADDR_CMASK_FLAGS flags = {{0}};
1462
1463 tileNumPerPipe = 256;
1464
1465 ComputeCmaskInfo(flags,
1466 pitch,
1467 height,
1468 numSlices,
1469 isLinear,
1470 pTileInfo,
1471 &newPitch,
1472 &newHeight,
1473 &totalBytes,
1474 &clWidth,
1475 &clHeight);
1476 }
1477 else //HTile
1478 {
1479 ADDR_HTILE_FLAGS flags = {{0}};
1480
1481 tileNumPerPipe = 512;
1482
1483 ComputeHtileInfo(flags,
1484 pitch,
1485 height,
1486 numSlices,
1487 isLinear,
1488 TRUE,
1489 TRUE,
1490 pTileInfo,
1491 &newPitch,
1492 &newHeight,
1493 &totalBytes,
1494 &clWidth,
1495 &clHeight,
1496 &sliceBytes);
1497 }
1498
1499 const UINT_32 pitchInTile = newPitch / MicroTileWidth;
1500 const UINT_32 heightInTile = newHeight / MicroTileWidth;
1501 const UINT_32 pitchInMacroTile = pitchInTile / 4;
1502 UINT_32 macroShift;
1503 UINT_32 elemIdxBits;
1504 // get macroShift and elemIdxBits
1505 TileCoordToMaskElementIndex(0, 0, pTileInfo->pipeConfig, ¯oShift, &elemIdxBits);
1506
1507 const UINT_32 numPipes = HwlGetPipes(pTileInfo);
1508 const UINT_32 pipe = (UINT_32)((addr / m_pipeInterleaveBytes) % numPipes);
1509 // per pipe
1510 UINT_64 localOffset = (addr % m_pipeInterleaveBytes) +
1511 (addr / m_pipeInterleaveBytes / numPipes)* m_pipeInterleaveBytes;
1512
1513 UINT_32 tileIndex;
1514 if (factor == 2) //CMASK
1515 {
1516 tileIndex = (UINT_32)(localOffset * 2 + (bitPosition != 0));
1517 }
1518 else
1519 {
1520 tileIndex = (UINT_32)(localOffset / 4);
1521 }
1522
1523 UINT_32 macroOffset;
1524 if (isLinear)
1525 {
1526 UINT_32 sliceSizeInTile = pitchInTile * heightInTile;
1527
1528 // do htile single slice alignment if the flag is true
1529 if (m_configFlags.useHtileSliceAlign && (factor == 1)) //Htile
1530 {
1531 sliceSizeInTile = PowTwoAlign(sliceSizeInTile, static_cast<UINT_32>(sliceBytes) / 64);
1532 }
1533 *pSlice = tileIndex / (sliceSizeInTile / numPipes);
1534 macroOffset = tileIndex % (sliceSizeInTile / numPipes);
1535 }
1536 else
1537 {
1538 const UINT_32 clWidthInTile = clWidth / MicroTileWidth; // Now in unit of Tiles
1539 const UINT_32 clHeightInTile = clHeight / MicroTileHeight;
1540 const UINT_32 pitchInCL = pitchInTile / clWidthInTile;
1541 const UINT_32 heightInCL = heightInTile / clHeightInTile;
1542 const UINT_32 clIndex = tileIndex / tileNumPerPipe;
1543
1544 UINT_32 clX = clIndex % pitchInCL;
1545 UINT_32 clY = (clIndex % (heightInCL * pitchInCL)) / pitchInCL;
1546
1547 *pX = clX * clWidthInTile * MicroTileWidth;
1548 *pY = clY * clHeightInTile * MicroTileHeight;
1549 *pSlice = clIndex / (heightInCL * pitchInCL);
1550
1551 macroOffset = tileIndex % tileNumPerPipe;
1552 }
1553
1554 UINT_32 elemIdx = macroOffset & 7;
1555 macroOffset >>= elemIdxBits;
1556
1557 if (elemIdxBits != macroShift)
1558 {
1559 macroOffset <<= (elemIdxBits - macroShift);
1560
1561 UINT_32 pipebit1 = _BIT(pipe,1);
1562 UINT_32 pipebit2 = _BIT(pipe,2);
1563 UINT_32 pipebit3 = _BIT(pipe,3);
1564 if (pitchInMacroTile % 2)
1565 { //odd
1566 switch (pTileInfo->pipeConfig)
1567 {
1568 case ADDR_PIPECFG_P4_32x32:
1569 macroOffset |= pipebit1;
1570 break;
1571 case ADDR_PIPECFG_P8_32x32_8x16:
1572 case ADDR_PIPECFG_P8_32x32_16x16:
1573 case ADDR_PIPECFG_P8_32x32_16x32:
1574 macroOffset |= pipebit2;
1575 break;
1576 default:
1577 break;
1578 }
1579
1580 }
1581
1582 if (pitchInMacroTile % 4)
1583 {
1584 if (pTileInfo->pipeConfig == ADDR_PIPECFG_P8_32x64_32x32)
1585 {
1586 macroOffset |= (pipebit1<<1);
1587 }
1588 if ((pTileInfo->pipeConfig == ADDR_PIPECFG_P16_32x32_8x16) ||
1589 (pTileInfo->pipeConfig == ADDR_PIPECFG_P16_32x32_16x16)
1590 )
1591 {
1592 macroOffset |= (pipebit3<<1);
1593 }
1594 }
1595 }
1596
1597 UINT_32 macroX;
1598 UINT_32 macroY;
1599
1600 if (isLinear)
1601 {
1602 macroX = macroOffset % pitchInMacroTile;
1603 macroY = macroOffset / pitchInMacroTile;
1604 }
1605 else
1606 {
1607 const UINT_32 clWidthInMacroTile = clWidth / (MicroTileWidth * 4);
1608 macroX = macroOffset % clWidthInMacroTile;
1609 macroY = macroOffset / clWidthInMacroTile;
1610 }
1611
1612 *pX += macroX * 4 * MicroTileWidth;
1613 *pY += macroY * 4 * MicroTileHeight;
1614
1615 UINT_32 microX;
1616 UINT_32 microY;
1617 ComputeTileCoordFromPipeAndElemIdx(elemIdx, pipe, pTileInfo->pipeConfig, pitchInMacroTile,
1618 *pX, *pY, µX, µY);
1619
1620 *pX += microX * MicroTileWidth;
1621 *pY += microY * MicroTileWidth;
1622 }
1623
1624 /**
1625 ****************************************************************************************************
1626 * SiLib::HwlGetPitchAlignmentLinear
1627 * @brief
1628 * Get pitch alignment
1629 * @return
1630 * pitch alignment
1631 ****************************************************************************************************
1632 */
HwlGetPitchAlignmentLinear(UINT_32 bpp,ADDR_SURFACE_FLAGS flags) const1633 UINT_32 SiLib::HwlGetPitchAlignmentLinear(
1634 UINT_32 bpp, ///< [in] bits per pixel
1635 ADDR_SURFACE_FLAGS flags ///< [in] surface flags
1636 ) const
1637 {
1638 UINT_32 pitchAlign;
1639
1640 // Interleaved access requires a 256B aligned pitch, so fall back to pre-SI alignment
1641 if (flags.interleaved)
1642 {
1643 pitchAlign = Max(64u, m_pipeInterleaveBytes / BITS_TO_BYTES(bpp));
1644
1645 }
1646 else
1647 {
1648 pitchAlign = Max(8u, 64 / BITS_TO_BYTES(bpp));
1649 }
1650
1651 return pitchAlign;
1652 }
1653
1654 /**
1655 ****************************************************************************************************
1656 * SiLib::HwlGetSizeAdjustmentLinear
1657 *
1658 * @brief
1659 * Adjust linear surface pitch and slice size
1660 *
1661 * @return
1662 * Logical slice size in bytes
1663 ****************************************************************************************************
1664 */
HwlGetSizeAdjustmentLinear(AddrTileMode tileMode,UINT_32 bpp,UINT_32 numSamples,UINT_32 baseAlign,UINT_32 pitchAlign,UINT_32 * pPitch,UINT_32 * pHeight,UINT_32 * pHeightAlign) const1665 UINT_64 SiLib::HwlGetSizeAdjustmentLinear(
1666 AddrTileMode tileMode, ///< [in] tile mode
1667 UINT_32 bpp, ///< [in] bits per pixel
1668 UINT_32 numSamples, ///< [in] number of samples
1669 UINT_32 baseAlign, ///< [in] base alignment
1670 UINT_32 pitchAlign, ///< [in] pitch alignment
1671 UINT_32* pPitch, ///< [in,out] pointer to pitch
1672 UINT_32* pHeight, ///< [in,out] pointer to height
1673 UINT_32* pHeightAlign ///< [in,out] pointer to height align
1674 ) const
1675 {
1676 UINT_64 sliceSize;
1677 if (tileMode == ADDR_TM_LINEAR_GENERAL)
1678 {
1679 sliceSize = BITS_TO_BYTES(static_cast<UINT_64>(*pPitch) * (*pHeight) * bpp * numSamples);
1680 }
1681 else
1682 {
1683 UINT_32 pitch = *pPitch;
1684 UINT_32 height = *pHeight;
1685
1686 UINT_32 pixelsPerPipeInterleave = m_pipeInterleaveBytes / BITS_TO_BYTES(bpp);
1687 UINT_32 sliceAlignInPixel = pixelsPerPipeInterleave < 64 ? 64 : pixelsPerPipeInterleave;
1688
1689 // numSamples should be 1 in real cases (no MSAA for linear but TGL may pass non 1 value)
1690 UINT_64 pixelPerSlice = static_cast<UINT_64>(pitch) * height * numSamples;
1691
1692 while (pixelPerSlice % sliceAlignInPixel)
1693 {
1694 pitch += pitchAlign;
1695 pixelPerSlice = static_cast<UINT_64>(pitch) * height * numSamples;
1696 }
1697
1698 *pPitch = pitch;
1699
1700 UINT_32 heightAlign = 1;
1701
1702 while ((pitch * heightAlign) % sliceAlignInPixel)
1703 {
1704 heightAlign++;
1705 }
1706
1707 *pHeightAlign = heightAlign;
1708
1709 sliceSize = BITS_TO_BYTES(pixelPerSlice * bpp);
1710 }
1711
1712 return sliceSize;
1713 }
1714
1715 /**
1716 ****************************************************************************************************
1717 * SiLib::HwlPreHandleBaseLvl3xPitch
1718 *
1719 * @brief
1720 * Pre-handler of 3x pitch (96 bit) adjustment
1721 *
1722 * @return
1723 * Expected pitch
1724 ****************************************************************************************************
1725 */
HwlPreHandleBaseLvl3xPitch(const ADDR_COMPUTE_SURFACE_INFO_INPUT * pIn,UINT_32 expPitch) const1726 UINT_32 SiLib::HwlPreHandleBaseLvl3xPitch(
1727 const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, ///< [in] input
1728 UINT_32 expPitch ///< [in] pitch
1729 ) const
1730 {
1731 ADDR_ASSERT(pIn->width == expPitch);
1732
1733 // From SI, if pow2Pad is 1 the pitch is expanded 3x first, then padded to pow2, so nothing to
1734 // do here
1735 if (pIn->flags.pow2Pad == FALSE)
1736 {
1737 Addr::V1::Lib::HwlPreHandleBaseLvl3xPitch(pIn, expPitch);
1738 }
1739 else
1740 {
1741 ADDR_ASSERT(IsPow2(expPitch));
1742 }
1743
1744 return expPitch;
1745 }
1746
1747 /**
1748 ****************************************************************************************************
1749 * SiLib::HwlPostHandleBaseLvl3xPitch
1750 *
1751 * @brief
1752 * Post-handler of 3x pitch adjustment
1753 *
1754 * @return
1755 * Expected pitch
1756 ****************************************************************************************************
1757 */
HwlPostHandleBaseLvl3xPitch(const ADDR_COMPUTE_SURFACE_INFO_INPUT * pIn,UINT_32 expPitch) const1758 UINT_32 SiLib::HwlPostHandleBaseLvl3xPitch(
1759 const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, ///< [in] input
1760 UINT_32 expPitch ///< [in] pitch
1761 ) const
1762 {
1763 /**
1764 * @note The pitch will be divided by 3 in the end so the value will look odd but h/w should
1765 * be able to compute a correct pitch from it as h/w address library is doing the job.
1766 */
1767 // From SI, the pitch is expanded 3x first, then padded to pow2, so no special handler here
1768 if (pIn->flags.pow2Pad == FALSE)
1769 {
1770 Addr::V1::Lib::HwlPostHandleBaseLvl3xPitch(pIn, expPitch);
1771 }
1772
1773 return expPitch;
1774 }
1775
1776 /**
1777 ****************************************************************************************************
1778 * SiLib::HwlGetPitchAlignmentMicroTiled
1779 *
1780 * @brief
1781 * Compute 1D tiled surface pitch alignment
1782 *
1783 * @return
1784 * pitch alignment
1785 ****************************************************************************************************
1786 */
HwlGetPitchAlignmentMicroTiled(AddrTileMode tileMode,UINT_32 bpp,ADDR_SURFACE_FLAGS flags,UINT_32 numSamples) const1787 UINT_32 SiLib::HwlGetPitchAlignmentMicroTiled(
1788 AddrTileMode tileMode, ///< [in] tile mode
1789 UINT_32 bpp, ///< [in] bits per pixel
1790 ADDR_SURFACE_FLAGS flags, ///< [in] surface flags
1791 UINT_32 numSamples ///< [in] number of samples
1792 ) const
1793 {
1794 UINT_32 pitchAlign;
1795
1796 if (flags.qbStereo)
1797 {
1798 pitchAlign = EgBasedLib::HwlGetPitchAlignmentMicroTiled(tileMode,bpp,flags,numSamples);
1799 }
1800 else
1801 {
1802 pitchAlign = 8;
1803 }
1804
1805 return pitchAlign;
1806 }
1807
1808 /**
1809 ****************************************************************************************************
1810 * SiLib::HwlGetSizeAdjustmentMicroTiled
1811 *
1812 * @brief
1813 * Adjust 1D tiled surface pitch and slice size
1814 *
1815 * @return
1816 * Logical slice size in bytes
1817 ****************************************************************************************************
1818 */
HwlGetSizeAdjustmentMicroTiled(UINT_32 thickness,UINT_32 bpp,ADDR_SURFACE_FLAGS flags,UINT_32 numSamples,UINT_32 baseAlign,UINT_32 pitchAlign,UINT_32 * pPitch,UINT_32 * pHeight) const1819 UINT_64 SiLib::HwlGetSizeAdjustmentMicroTiled(
1820 UINT_32 thickness, ///< [in] thickness
1821 UINT_32 bpp, ///< [in] bits per pixel
1822 ADDR_SURFACE_FLAGS flags, ///< [in] surface flags
1823 UINT_32 numSamples, ///< [in] number of samples
1824 UINT_32 baseAlign, ///< [in] base alignment
1825 UINT_32 pitchAlign, ///< [in] pitch alignment
1826 UINT_32* pPitch, ///< [in,out] pointer to pitch
1827 UINT_32* pHeight ///< [in,out] pointer to height
1828 ) const
1829 {
1830 UINT_64 logicalSliceSize;
1831 UINT_64 physicalSliceSize;
1832
1833 UINT_32 pitch = *pPitch;
1834 UINT_32 height = *pHeight;
1835
1836 // Logical slice: pitch * height * bpp * numSamples (no 1D MSAA so actually numSamples == 1)
1837 logicalSliceSize = BITS_TO_BYTES(static_cast<UINT_64>(pitch) * height * bpp * numSamples);
1838
1839 // Physical slice: multiplied by thickness
1840 physicalSliceSize = logicalSliceSize * thickness;
1841
1842 // Pitch alignment is always 8, so if slice size is not padded to base alignment
1843 // (pipe_interleave_size), we need to increase pitch
1844 while ((physicalSliceSize % baseAlign) != 0)
1845 {
1846 pitch += pitchAlign;
1847
1848 logicalSliceSize = BITS_TO_BYTES(static_cast<UINT_64>(pitch) * height * bpp * numSamples);
1849
1850 physicalSliceSize = logicalSliceSize * thickness;
1851 }
1852
1853 #if !ALT_TEST
1854 //
1855 // Special workaround for depth/stencil buffer, use 8 bpp to align depth buffer again since
1856 // the stencil plane may have larger pitch if the slice size is smaller than base alignment.
1857 //
1858 // Note: this actually does not work for mipmap but mipmap depth texture is not really
1859 // sampled with mipmap.
1860 //
1861 if (flags.depth && (flags.noStencil == FALSE))
1862 {
1863 ADDR_ASSERT(numSamples == 1);
1864
1865 UINT_64 logicalSiceSizeStencil = static_cast<UINT_64>(pitch) * height; // 1 byte stencil
1866
1867 while ((logicalSiceSizeStencil % baseAlign) != 0)
1868 {
1869 pitch += pitchAlign; // Stencil plane's pitch alignment is the same as depth plane's
1870
1871 logicalSiceSizeStencil = static_cast<UINT_64>(pitch) * height;
1872 }
1873
1874 if (pitch != *pPitch)
1875 {
1876 // If this is a mipmap, this padded one cannot be sampled as a whole mipmap!
1877 logicalSliceSize = logicalSiceSizeStencil * BITS_TO_BYTES(bpp);
1878 }
1879 }
1880 #endif
1881 *pPitch = pitch;
1882
1883 // No adjust for pHeight
1884
1885 return logicalSliceSize;
1886 }
1887
1888 /**
1889 ****************************************************************************************************
1890 * SiLib::HwlConvertChipFamily
1891 *
1892 * @brief
1893 * Convert familyID defined in atiid.h to ChipFamily and set m_chipFamily/m_chipRevision
1894 * @return
1895 * ChipFamily
1896 ****************************************************************************************************
1897 */
HwlConvertChipFamily(UINT_32 uChipFamily,UINT_32 uChipRevision)1898 ChipFamily SiLib::HwlConvertChipFamily(
1899 UINT_32 uChipFamily, ///< [in] chip family defined in atiih.h
1900 UINT_32 uChipRevision) ///< [in] chip revision defined in "asic_family"_id.h
1901 {
1902 ChipFamily family = ADDR_CHIP_FAMILY_SI;
1903
1904 switch (uChipFamily)
1905 {
1906 case FAMILY_SI:
1907 m_settings.isSouthernIsland = 1;
1908 m_settings.isTahiti = ASICREV_IS_TAHITI_P(uChipRevision);
1909 m_settings.isPitCairn = ASICREV_IS_PITCAIRN_PM(uChipRevision);
1910 m_settings.isCapeVerde = ASICREV_IS_CAPEVERDE_M(uChipRevision);
1911 m_settings.isOland = ASICREV_IS_OLAND_M(uChipRevision);
1912 m_settings.isHainan = ASICREV_IS_HAINAN_V(uChipRevision);
1913 break;
1914 default:
1915 ADDR_ASSERT(!"No Chip found");
1916 break;
1917 }
1918
1919 return family;
1920 }
1921
1922 /**
1923 ****************************************************************************************************
1924 * SiLib::HwlSetupTileInfo
1925 *
1926 * @brief
1927 * Setup default value of tile info for SI
1928 ****************************************************************************************************
1929 */
HwlSetupTileInfo(AddrTileMode tileMode,ADDR_SURFACE_FLAGS flags,UINT_32 bpp,UINT_32 pitch,UINT_32 height,UINT_32 numSamples,ADDR_TILEINFO * pTileInfoIn,ADDR_TILEINFO * pTileInfoOut,AddrTileType inTileType,ADDR_COMPUTE_SURFACE_INFO_OUTPUT * pOut) const1930 VOID SiLib::HwlSetupTileInfo(
1931 AddrTileMode tileMode, ///< [in] Tile mode
1932 ADDR_SURFACE_FLAGS flags, ///< [in] Surface type flags
1933 UINT_32 bpp, ///< [in] Bits per pixel
1934 UINT_32 pitch, ///< [in] Pitch in pixels
1935 UINT_32 height, ///< [in] Height in pixels
1936 UINT_32 numSamples, ///< [in] Number of samples
1937 ADDR_TILEINFO* pTileInfoIn, ///< [in] Tile info input: NULL for default
1938 ADDR_TILEINFO* pTileInfoOut, ///< [out] Tile info output
1939 AddrTileType inTileType, ///< [in] Tile type
1940 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [out] Output
1941 ) const
1942 {
1943 UINT_32 thickness = Thickness(tileMode);
1944 ADDR_TILEINFO* pTileInfo = pTileInfoOut;
1945 INT index = TileIndexInvalid;
1946
1947 // Fail-safe code
1948 if (IsLinear(tileMode) == FALSE)
1949 {
1950 // 128 bpp/thick tiling must be non-displayable.
1951 // Fmask reuse color buffer's entry but bank-height field can be from another entry
1952 // To simplify the logic, fmask entry should be picked from non-displayable ones
1953 if (bpp == 128 || thickness > 1 || flags.fmask || flags.prt)
1954 {
1955 inTileType = ADDR_NON_DISPLAYABLE;
1956 }
1957
1958 if (flags.depth || flags.stencil)
1959 {
1960 inTileType = ADDR_DEPTH_SAMPLE_ORDER;
1961 }
1962 }
1963
1964 // Partial valid fields are not allowed for SI.
1965 if (IsTileInfoAllZero(pTileInfo))
1966 {
1967 if (IsMacroTiled(tileMode))
1968 {
1969 if (flags.prt)
1970 {
1971 if (numSamples == 1)
1972 {
1973 if (flags.depth)
1974 {
1975 switch (bpp)
1976 {
1977 case 16:
1978 index = 3;
1979 break;
1980 case 32:
1981 index = 6;
1982 break;
1983 default:
1984 ADDR_ASSERT_ALWAYS();
1985 break;
1986 }
1987 }
1988 else
1989 {
1990 switch (bpp)
1991 {
1992 case 8:
1993 index = 21;
1994 break;
1995 case 16:
1996 index = 22;
1997 break;
1998 case 32:
1999 index = 23;
2000 break;
2001 case 64:
2002 index = 24;
2003 break;
2004 case 128:
2005 index = 25;
2006 break;
2007 default:
2008 break;
2009 }
2010
2011 if (thickness > 1)
2012 {
2013 ADDR_ASSERT(bpp != 128);
2014 index += 5;
2015 }
2016 }
2017 }
2018 else
2019 {
2020 ADDR_ASSERT(numSamples == 4);
2021
2022 if (flags.depth)
2023 {
2024 switch (bpp)
2025 {
2026 case 16:
2027 index = 5;
2028 break;
2029 case 32:
2030 index = 7;
2031 break;
2032 default:
2033 ADDR_ASSERT_ALWAYS();
2034 break;
2035 }
2036 }
2037 else
2038 {
2039 switch (bpp)
2040 {
2041 case 8:
2042 index = 23;
2043 break;
2044 case 16:
2045 index = 24;
2046 break;
2047 case 32:
2048 index = 25;
2049 break;
2050 case 64:
2051 index = 30;
2052 break;
2053 default:
2054 ADDR_ASSERT_ALWAYS();
2055 break;
2056 }
2057 }
2058 }
2059 }//end of PRT part
2060 // See table entries 0-7
2061 else if (flags.depth || flags.stencil)
2062 {
2063 if (flags.compressZ)
2064 {
2065 if (flags.stencil)
2066 {
2067 index = 0;
2068 }
2069 else
2070 {
2071 // optimal tile index for compressed depth/stencil.
2072 switch (numSamples)
2073 {
2074 case 1:
2075 index = 0;
2076 break;
2077 case 2:
2078 case 4:
2079 index = 1;
2080 break;
2081 case 8:
2082 index = 2;
2083 break;
2084 default:
2085 break;
2086 }
2087 }
2088 }
2089 else // unCompressZ
2090 {
2091 index = 3;
2092 }
2093 }
2094 else //non PRT & non Depth & non Stencil
2095 {
2096 // See table entries 9-12
2097 if (inTileType == ADDR_DISPLAYABLE)
2098 {
2099 switch (bpp)
2100 {
2101 case 8:
2102 index = 10;
2103 break;
2104 case 16:
2105 index = 11;
2106 break;
2107 case 32:
2108 index = 12;
2109 break;
2110 case 64:
2111 index = 12;
2112 break;
2113 default:
2114 break;
2115 }
2116 }
2117 else
2118 {
2119 // See table entries 13-17
2120 if (thickness == 1)
2121 {
2122 if (flags.fmask)
2123 {
2124 UINT_32 fmaskPixelSize = bpp * numSamples;
2125
2126 switch (fmaskPixelSize)
2127 {
2128 case 8:
2129 index = 14;
2130 break;
2131 case 16:
2132 index = 15;
2133 break;
2134 case 32:
2135 index = 16;
2136 break;
2137 case 64:
2138 index = 17;
2139 break;
2140 default:
2141 ADDR_ASSERT_ALWAYS();
2142 }
2143 }
2144 else
2145 {
2146 switch (bpp)
2147 {
2148 case 8:
2149 index = 14;
2150 break;
2151 case 16:
2152 index = 15;
2153 break;
2154 case 32:
2155 index = 16;
2156 break;
2157 case 64:
2158 index = 17;
2159 break;
2160 case 128:
2161 index = 17;
2162 break;
2163 default:
2164 break;
2165 }
2166 }
2167 }
2168 else // thick tiling - entries 18-20
2169 {
2170 switch (thickness)
2171 {
2172 case 4:
2173 index = 20;
2174 break;
2175 case 8:
2176 index = 19;
2177 break;
2178 default:
2179 break;
2180 }
2181 }
2182 }
2183 }
2184 }
2185 else
2186 {
2187 if (tileMode == ADDR_TM_LINEAR_ALIGNED)
2188 {
2189 index = 8;
2190 }
2191 else if (tileMode == ADDR_TM_LINEAR_GENERAL)
2192 {
2193 index = TileIndexLinearGeneral;
2194 }
2195 else
2196 {
2197 if (flags.depth || flags.stencil)
2198 {
2199 index = 4;
2200 }
2201 else if (inTileType == ADDR_DISPLAYABLE)
2202 {
2203 index = 9;
2204 }
2205 else if (thickness == 1)
2206 {
2207 index = 13;
2208 }
2209 else
2210 {
2211 index = 18;
2212 }
2213 }
2214 }
2215
2216 if (index >= 0 && index <= 31)
2217 {
2218 *pTileInfo = m_tileTable[index].info;
2219 pOut->tileType = m_tileTable[index].type;
2220 }
2221
2222 if (index == TileIndexLinearGeneral)
2223 {
2224 *pTileInfo = m_tileTable[8].info;
2225 pOut->tileType = m_tileTable[8].type;
2226 }
2227 }
2228 else
2229 {
2230 if (pTileInfoIn)
2231 {
2232 if (flags.stencil && pTileInfoIn->tileSplitBytes == 0)
2233 {
2234 // Stencil always uses index 0
2235 *pTileInfo = m_tileTable[0].info;
2236 }
2237 }
2238 // Pass through tile type
2239 pOut->tileType = inTileType;
2240 }
2241
2242 pOut->tileIndex = index;
2243 pOut->prtTileIndex = flags.prt;
2244 }
2245
2246 /**
2247 ****************************************************************************************************
2248 * SiLib::DecodeGbRegs
2249 *
2250 * @brief
2251 * Decodes GB_ADDR_CONFIG and noOfBanks/noOfRanks
2252 *
2253 * @return
2254 * TRUE if all settings are valid
2255 *
2256 ****************************************************************************************************
2257 */
DecodeGbRegs(const ADDR_REGISTER_VALUE * pRegValue)2258 BOOL_32 SiLib::DecodeGbRegs(
2259 const ADDR_REGISTER_VALUE* pRegValue) ///< [in] create input
2260 {
2261 GB_ADDR_CONFIG reg;
2262 BOOL_32 valid = TRUE;
2263
2264 reg.val = pRegValue->gbAddrConfig;
2265
2266 switch (reg.f.pipe_interleave_size)
2267 {
2268 case ADDR_CONFIG_PIPE_INTERLEAVE_256B:
2269 m_pipeInterleaveBytes = ADDR_PIPEINTERLEAVE_256B;
2270 break;
2271 case ADDR_CONFIG_PIPE_INTERLEAVE_512B:
2272 m_pipeInterleaveBytes = ADDR_PIPEINTERLEAVE_512B;
2273 break;
2274 default:
2275 valid = FALSE;
2276 ADDR_UNHANDLED_CASE();
2277 break;
2278 }
2279
2280 switch (reg.f.row_size)
2281 {
2282 case ADDR_CONFIG_1KB_ROW:
2283 m_rowSize = ADDR_ROWSIZE_1KB;
2284 break;
2285 case ADDR_CONFIG_2KB_ROW:
2286 m_rowSize = ADDR_ROWSIZE_2KB;
2287 break;
2288 case ADDR_CONFIG_4KB_ROW:
2289 m_rowSize = ADDR_ROWSIZE_4KB;
2290 break;
2291 default:
2292 valid = FALSE;
2293 ADDR_UNHANDLED_CASE();
2294 break;
2295 }
2296
2297 switch (pRegValue->noOfBanks)
2298 {
2299 case 0:
2300 m_banks = 4;
2301 break;
2302 case 1:
2303 m_banks = 8;
2304 break;
2305 case 2:
2306 m_banks = 16;
2307 break;
2308 default:
2309 valid = FALSE;
2310 ADDR_UNHANDLED_CASE();
2311 break;
2312 }
2313
2314 switch (pRegValue->noOfRanks)
2315 {
2316 case 0:
2317 m_ranks = 1;
2318 break;
2319 case 1:
2320 m_ranks = 2;
2321 break;
2322 default:
2323 valid = FALSE;
2324 ADDR_UNHANDLED_CASE();
2325 break;
2326 }
2327
2328 m_logicalBanks = m_banks * m_ranks;
2329
2330 ADDR_ASSERT(m_logicalBanks <= 16);
2331
2332 return valid;
2333 }
2334
2335 /**
2336 ****************************************************************************************************
2337 * SiLib::HwlInitGlobalParams
2338 *
2339 * @brief
2340 * Initializes global parameters
2341 *
2342 * @return
2343 * TRUE if all settings are valid
2344 *
2345 ****************************************************************************************************
2346 */
HwlInitGlobalParams(const ADDR_CREATE_INPUT * pCreateIn)2347 BOOL_32 SiLib::HwlInitGlobalParams(
2348 const ADDR_CREATE_INPUT* pCreateIn) ///< [in] create input
2349 {
2350 BOOL_32 valid = TRUE;
2351 const ADDR_REGISTER_VALUE* pRegValue = &pCreateIn->regValue;
2352
2353 valid = DecodeGbRegs(pRegValue);
2354
2355 if (valid)
2356 {
2357 if (m_settings.isTahiti || m_settings.isPitCairn)
2358 {
2359 m_pipes = 8;
2360 }
2361 else if (m_settings.isCapeVerde || m_settings.isOland)
2362 {
2363 m_pipes = 4;
2364 }
2365 else
2366 {
2367 // Hainan is 2-pipe (m_settings.isHainan == 1)
2368 m_pipes = 2;
2369 }
2370
2371 valid = InitTileSettingTable(pRegValue->pTileConfig, pRegValue->noOfEntries);
2372
2373 if (valid)
2374 {
2375 InitEquationTable();
2376 }
2377
2378 m_maxSamples = 16;
2379 }
2380
2381 return valid;
2382 }
2383
2384 /**
2385 ****************************************************************************************************
2386 * SiLib::HwlConvertTileInfoToHW
2387 * @brief
2388 * Entry of si's ConvertTileInfoToHW
2389 * @return
2390 * ADDR_E_RETURNCODE
2391 ****************************************************************************************************
2392 */
HwlConvertTileInfoToHW(const ADDR_CONVERT_TILEINFOTOHW_INPUT * pIn,ADDR_CONVERT_TILEINFOTOHW_OUTPUT * pOut) const2393 ADDR_E_RETURNCODE SiLib::HwlConvertTileInfoToHW(
2394 const ADDR_CONVERT_TILEINFOTOHW_INPUT* pIn, ///< [in] input structure
2395 ADDR_CONVERT_TILEINFOTOHW_OUTPUT* pOut ///< [out] output structure
2396 ) const
2397 {
2398 ADDR_E_RETURNCODE retCode = ADDR_OK;
2399
2400 retCode = EgBasedLib::HwlConvertTileInfoToHW(pIn, pOut);
2401
2402 if (retCode == ADDR_OK)
2403 {
2404 if (pIn->reverse == FALSE)
2405 {
2406 if (pIn->pTileInfo->pipeConfig == ADDR_PIPECFG_INVALID)
2407 {
2408 retCode = ADDR_INVALIDPARAMS;
2409 }
2410 else
2411 {
2412 pOut->pTileInfo->pipeConfig =
2413 static_cast<AddrPipeCfg>(pIn->pTileInfo->pipeConfig - 1);
2414 }
2415 }
2416 else
2417 {
2418 pOut->pTileInfo->pipeConfig =
2419 static_cast<AddrPipeCfg>(pIn->pTileInfo->pipeConfig + 1);
2420 }
2421 }
2422
2423 return retCode;
2424 }
2425
2426 /**
2427 ****************************************************************************************************
2428 * SiLib::HwlComputeXmaskCoordYFrom8Pipe
2429 *
2430 * @brief
2431 * Compute the Y coord which will be added to Xmask Y
2432 * coord.
2433 * @return
2434 * Y coord
2435 ****************************************************************************************************
2436 */
HwlComputeXmaskCoordYFrom8Pipe(UINT_32 pipe,UINT_32 x) const2437 UINT_32 SiLib::HwlComputeXmaskCoordYFrom8Pipe(
2438 UINT_32 pipe, ///< [in] pipe id
2439 UINT_32 x ///< [in] tile coord x, which is original x coord / 8
2440 ) const
2441 {
2442 // This function should never be called since it is 6xx/8xx specfic.
2443 // Keep this empty implementation to avoid any mis-use.
2444 ADDR_ASSERT_ALWAYS();
2445
2446 return 0;
2447 }
2448
2449 /**
2450 ****************************************************************************************************
2451 * SiLib::HwlComputeSurfaceCoord2DFromBankPipe
2452 *
2453 * @brief
2454 * Compute surface x,y coordinates from bank/pipe info
2455 * @return
2456 * N/A
2457 ****************************************************************************************************
2458 */
HwlComputeSurfaceCoord2DFromBankPipe(AddrTileMode tileMode,UINT_32 * pX,UINT_32 * pY,UINT_32 slice,UINT_32 bank,UINT_32 pipe,UINT_32 bankSwizzle,UINT_32 pipeSwizzle,UINT_32 tileSlices,BOOL_32 ignoreSE,ADDR_TILEINFO * pTileInfo) const2459 VOID SiLib::HwlComputeSurfaceCoord2DFromBankPipe(
2460 AddrTileMode tileMode, ///< [in] tile mode
2461 UINT_32* pX, ///< [in,out] x coordinate
2462 UINT_32* pY, ///< [in,out] y coordinate
2463 UINT_32 slice, ///< [in] slice index
2464 UINT_32 bank, ///< [in] bank number
2465 UINT_32 pipe, ///< [in] pipe number
2466 UINT_32 bankSwizzle,///< [in] bank swizzle
2467 UINT_32 pipeSwizzle,///< [in] pipe swizzle
2468 UINT_32 tileSlices, ///< [in] slices in a micro tile
2469 BOOL_32 ignoreSE, ///< [in] TRUE if shader engines are ignored
2470 ADDR_TILEINFO* pTileInfo ///< [in] bank structure. **All fields to be valid on entry**
2471 ) const
2472 {
2473 UINT_32 xBit;
2474 UINT_32 yBit;
2475 UINT_32 yBit3 = 0;
2476 UINT_32 yBit4 = 0;
2477 UINT_32 yBit5 = 0;
2478 UINT_32 yBit6 = 0;
2479
2480 UINT_32 xBit3 = 0;
2481 UINT_32 xBit4 = 0;
2482 UINT_32 xBit5 = 0;
2483
2484 UINT_32 numPipes = GetPipePerSurf(pTileInfo->pipeConfig);
2485
2486 CoordFromBankPipe xyBits = {0};
2487 ComputeSurfaceCoord2DFromBankPipe(tileMode, *pX, *pY, slice, bank, pipe,
2488 bankSwizzle, pipeSwizzle, tileSlices, pTileInfo,
2489 &xyBits);
2490 yBit3 = xyBits.yBit3;
2491 yBit4 = xyBits.yBit4;
2492 yBit5 = xyBits.yBit5;
2493 yBit6 = xyBits.yBit6;
2494
2495 xBit3 = xyBits.xBit3;
2496 xBit4 = xyBits.xBit4;
2497 xBit5 = xyBits.xBit5;
2498
2499 yBit = xyBits.yBits;
2500
2501 UINT_32 yBitTemp = 0;
2502
2503 if ((pTileInfo->pipeConfig == ADDR_PIPECFG_P4_32x32) ||
2504 (pTileInfo->pipeConfig == ADDR_PIPECFG_P8_32x64_32x32))
2505 {
2506 ADDR_ASSERT(pTileInfo->bankWidth == 1 && pTileInfo->macroAspectRatio > 1);
2507 UINT_32 yBitToCheck = QLog2(pTileInfo->banks) - 1;
2508
2509 ADDR_ASSERT(yBitToCheck <= 3);
2510
2511 yBitTemp = _BIT(yBit, yBitToCheck);
2512
2513 xBit3 = 0;
2514 }
2515
2516 yBit = Bits2Number(4, yBit6, yBit5, yBit4, yBit3);
2517 xBit = Bits2Number(3, xBit5, xBit4, xBit3);
2518
2519 *pY += yBit * pTileInfo->bankHeight * MicroTileHeight;
2520 *pX += xBit * numPipes * pTileInfo->bankWidth * MicroTileWidth;
2521
2522 //calculate the bank and pipe bits in x, y
2523 UINT_32 xTile; //x in micro tile
2524 UINT_32 x3 = 0;
2525 UINT_32 x4 = 0;
2526 UINT_32 x5 = 0;
2527 UINT_32 x6 = 0;
2528 UINT_32 y = *pY;
2529
2530 UINT_32 pipeBit0 = _BIT(pipe,0);
2531 UINT_32 pipeBit1 = _BIT(pipe,1);
2532 UINT_32 pipeBit2 = _BIT(pipe,2);
2533
2534 UINT_32 y3 = _BIT(y, 3);
2535 UINT_32 y4 = _BIT(y, 4);
2536 UINT_32 y5 = _BIT(y, 5);
2537 UINT_32 y6 = _BIT(y, 6);
2538
2539 // bankbit0 after ^x4^x5
2540 UINT_32 bankBit00 = _BIT(bank,0);
2541 UINT_32 bankBit0 = 0;
2542
2543 switch (pTileInfo->pipeConfig)
2544 {
2545 case ADDR_PIPECFG_P2:
2546 x3 = pipeBit0 ^ y3;
2547 break;
2548 case ADDR_PIPECFG_P4_8x16:
2549 x4 = pipeBit0 ^ y3;
2550 x3 = pipeBit0 ^ y4;
2551 break;
2552 case ADDR_PIPECFG_P4_16x16:
2553 x4 = pipeBit1 ^ y4;
2554 x3 = pipeBit0 ^ y3 ^ x4;
2555 break;
2556 case ADDR_PIPECFG_P4_16x32:
2557 x4 = pipeBit1 ^ y4;
2558 x3 = pipeBit0 ^ y3 ^ x4;
2559 break;
2560 case ADDR_PIPECFG_P4_32x32:
2561 x5 = pipeBit1 ^ y5;
2562 x3 = pipeBit0 ^ y3 ^ x5;
2563 bankBit0 = yBitTemp ^ x5;
2564 x4 = bankBit00 ^ x5 ^ bankBit0;
2565 *pX += x5 * 4 * 1 * 8; // x5 * num_pipes * bank_width * 8;
2566 break;
2567 case ADDR_PIPECFG_P8_16x16_8x16:
2568 x3 = pipeBit1 ^ y5;
2569 x4 = pipeBit2 ^ y4;
2570 x5 = pipeBit0 ^ y3 ^ x4;
2571 break;
2572 case ADDR_PIPECFG_P8_16x32_8x16:
2573 x3 = pipeBit1 ^ y4;
2574 x4 = pipeBit2 ^ y5;
2575 x5 = pipeBit0 ^ y3 ^ x4;
2576 break;
2577 case ADDR_PIPECFG_P8_32x32_8x16:
2578 x3 = pipeBit1 ^ y4;
2579 x5 = pipeBit2 ^ y5;
2580 x4 = pipeBit0 ^ y3 ^ x5;
2581 break;
2582 case ADDR_PIPECFG_P8_16x32_16x16:
2583 x4 = pipeBit2 ^ y5;
2584 x5 = pipeBit1 ^ y4;
2585 x3 = pipeBit0 ^ y3 ^ x4;
2586 break;
2587 case ADDR_PIPECFG_P8_32x32_16x16:
2588 x5 = pipeBit2 ^ y5;
2589 x4 = pipeBit1 ^ y4;
2590 x3 = pipeBit0 ^ y3 ^ x4;
2591 break;
2592 case ADDR_PIPECFG_P8_32x32_16x32:
2593 x5 = pipeBit2 ^ y5;
2594 x4 = pipeBit1 ^ y6;
2595 x3 = pipeBit0 ^ y3 ^ x4;
2596 break;
2597 case ADDR_PIPECFG_P8_32x64_32x32:
2598 x6 = pipeBit1 ^ y5;
2599 x5 = pipeBit2 ^ y6;
2600 x3 = pipeBit0 ^ y3 ^ x5;
2601 bankBit0 = yBitTemp ^ x6;
2602 x4 = bankBit00 ^ x5 ^ bankBit0;
2603 *pX += x6 * 8 * 1 * 8; // x6 * num_pipes * bank_width * 8;
2604 break;
2605 default:
2606 ADDR_ASSERT_ALWAYS();
2607 }
2608
2609 xTile = Bits2Number(3, x5, x4, x3);
2610
2611 *pX += xTile << 3;
2612 }
2613
2614 /**
2615 ****************************************************************************************************
2616 * SiLib::HwlPreAdjustBank
2617 *
2618 * @brief
2619 * Adjust bank before calculating address acoording to bank/pipe
2620 * @return
2621 * Adjusted bank
2622 ****************************************************************************************************
2623 */
HwlPreAdjustBank(UINT_32 tileX,UINT_32 bank,ADDR_TILEINFO * pTileInfo) const2624 UINT_32 SiLib::HwlPreAdjustBank(
2625 UINT_32 tileX, ///< [in] x coordinate in unit of tile
2626 UINT_32 bank, ///< [in] bank
2627 ADDR_TILEINFO* pTileInfo ///< [in] tile info
2628 ) const
2629 {
2630 if (((pTileInfo->pipeConfig == ADDR_PIPECFG_P4_32x32) ||
2631 (pTileInfo->pipeConfig == ADDR_PIPECFG_P8_32x64_32x32)) && (pTileInfo->bankWidth == 1))
2632 {
2633 UINT_32 bankBit0 = _BIT(bank, 0);
2634 UINT_32 x4 = _BIT(tileX, 1);
2635 UINT_32 x5 = _BIT(tileX, 2);
2636
2637 bankBit0 = bankBit0 ^ x4 ^ x5;
2638 bank |= bankBit0;
2639
2640 ADDR_ASSERT(pTileInfo->macroAspectRatio > 1);
2641 }
2642
2643 return bank;
2644 }
2645
2646 /**
2647 ****************************************************************************************************
2648 * SiLib::HwlComputeSurfaceInfo
2649 *
2650 * @brief
2651 * Entry of si's ComputeSurfaceInfo
2652 * @return
2653 * ADDR_E_RETURNCODE
2654 ****************************************************************************************************
2655 */
HwlComputeSurfaceInfo(const ADDR_COMPUTE_SURFACE_INFO_INPUT * pIn,ADDR_COMPUTE_SURFACE_INFO_OUTPUT * pOut) const2656 ADDR_E_RETURNCODE SiLib::HwlComputeSurfaceInfo(
2657 const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, ///< [in] input structure
2658 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [out] output structure
2659 ) const
2660 {
2661 pOut->tileIndex = pIn->tileIndex;
2662
2663 ADDR_E_RETURNCODE retCode = EgBasedLib::HwlComputeSurfaceInfo(pIn, pOut);
2664
2665 UINT_32 tileIndex = static_cast<UINT_32>(pOut->tileIndex);
2666
2667 if (((pIn->flags.needEquation == TRUE) ||
2668 (pIn->flags.preferEquation == TRUE)) &&
2669 (pIn->numSamples <= 1) &&
2670 (tileIndex < TileTableSize))
2671 {
2672 static const UINT_32 SiUncompressDepthTileIndex = 3;
2673
2674 if ((pIn->numSlices > 1) &&
2675 (IsMacroTiled(pOut->tileMode) == TRUE) &&
2676 ((m_chipFamily == ADDR_CHIP_FAMILY_SI) ||
2677 (IsPrtTileMode(pOut->tileMode) == FALSE)))
2678 {
2679 pOut->equationIndex = ADDR_INVALID_EQUATION_INDEX;
2680 }
2681 else if ((pIn->flags.prt == FALSE) &&
2682 (m_uncompressDepthEqIndex != 0) &&
2683 (tileIndex == SiUncompressDepthTileIndex))
2684 {
2685 pOut->equationIndex = m_uncompressDepthEqIndex + Log2(pIn->bpp >> 3);
2686 }
2687 else
2688 {
2689
2690 pOut->equationIndex = m_equationLookupTable[Log2(pIn->bpp >> 3)][tileIndex];
2691 }
2692
2693 if (pOut->equationIndex != ADDR_INVALID_EQUATION_INDEX)
2694 {
2695 pOut->blockWidth = m_blockWidth[pOut->equationIndex];
2696
2697 pOut->blockHeight = m_blockHeight[pOut->equationIndex];
2698
2699 pOut->blockSlices = m_blockSlices[pOut->equationIndex];
2700 }
2701 }
2702 else
2703 {
2704 pOut->equationIndex = ADDR_INVALID_EQUATION_INDEX;
2705 }
2706
2707 return retCode;
2708 }
2709
2710 /**
2711 ****************************************************************************************************
2712 * SiLib::HwlComputeMipLevel
2713 * @brief
2714 * Compute MipLevel info (including level 0)
2715 * @return
2716 * TRUE if HWL's handled
2717 ****************************************************************************************************
2718 */
HwlComputeMipLevel(ADDR_COMPUTE_SURFACE_INFO_INPUT * pIn) const2719 BOOL_32 SiLib::HwlComputeMipLevel(
2720 ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn ///< [in,out] Input structure
2721 ) const
2722 {
2723 // basePitch is calculated from level 0 so we only check this for mipLevel > 0
2724 if (pIn->mipLevel > 0)
2725 {
2726 // Note: Don't check expand 3x formats(96 bit) as the basePitch is not pow2 even if
2727 // we explicity set pow2Pad flag. The 3x base pitch is padded to pow2 but after being
2728 // divided by expandX factor (3) - to program texture pitch, the basePitch is never pow2.
2729 if (ElemLib::IsExpand3x(pIn->format) == FALSE)
2730 {
2731 // Sublevel pitches are generated from base level pitch instead of width on SI
2732 // If pow2Pad is 0, we don't assert - as this is not really used for a mip chain
2733 ADDR_ASSERT((pIn->flags.pow2Pad == FALSE) ||
2734 ((pIn->basePitch != 0) && IsPow2(pIn->basePitch)));
2735 }
2736
2737 if (pIn->basePitch != 0)
2738 {
2739 pIn->width = Max(1u, pIn->basePitch >> pIn->mipLevel);
2740 }
2741 }
2742
2743 // pow2Pad is done in PostComputeMipLevel
2744
2745 return TRUE;
2746 }
2747
2748 /**
2749 ****************************************************************************************************
2750 * SiLib::HwlCheckLastMacroTiledLvl
2751 *
2752 * @brief
2753 * Sets pOut->last2DLevel to TRUE if it is
2754 * @note
2755 *
2756 ****************************************************************************************************
2757 */
HwlCheckLastMacroTiledLvl(const ADDR_COMPUTE_SURFACE_INFO_INPUT * pIn,ADDR_COMPUTE_SURFACE_INFO_OUTPUT * pOut) const2758 VOID SiLib::HwlCheckLastMacroTiledLvl(
2759 const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, ///< [in] Input structure
2760 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [in,out] Output structure (used as input, too)
2761 ) const
2762 {
2763 // pow2Pad covers all mipmap cases
2764 if (pIn->flags.pow2Pad)
2765 {
2766 ADDR_ASSERT(IsMacroTiled(pIn->tileMode));
2767
2768 UINT_32 nextPitch;
2769 UINT_32 nextHeight;
2770 UINT_32 nextSlices;
2771
2772 AddrTileMode nextTileMode;
2773
2774 if (pIn->mipLevel == 0 || pIn->basePitch == 0)
2775 {
2776 // Base level or fail-safe case (basePitch == 0)
2777 nextPitch = pOut->pitch >> 1;
2778 }
2779 else
2780 {
2781 // Sub levels
2782 nextPitch = pIn->basePitch >> (pIn->mipLevel + 1);
2783 }
2784
2785 // nextHeight must be shifted from this level's original height rather than a pow2 padded
2786 // one but this requires original height stored somewhere (pOut->height)
2787 ADDR_ASSERT(pOut->height != 0);
2788
2789 // next level's height is just current level's >> 1 in pixels
2790 nextHeight = pOut->height >> 1;
2791 // Special format such as FMT_1 and FMT_32_32_32 can be linear only so we consider block
2792 // compressed foramts
2793 if (ElemLib::IsBlockCompressed(pIn->format))
2794 {
2795 nextHeight = (nextHeight + 3) / 4;
2796 }
2797 nextHeight = NextPow2(nextHeight);
2798
2799 // nextSlices may be 0 if this level's is 1
2800 if (pIn->flags.volume)
2801 {
2802 nextSlices = Max(1u, pIn->numSlices >> 1);
2803 }
2804 else
2805 {
2806 nextSlices = pIn->numSlices;
2807 }
2808
2809 nextTileMode = ComputeSurfaceMipLevelTileMode(pIn->tileMode,
2810 pIn->bpp,
2811 nextPitch,
2812 nextHeight,
2813 nextSlices,
2814 pIn->numSamples,
2815 pOut->blockWidth,
2816 pOut->blockHeight,
2817 pOut->pTileInfo);
2818
2819 pOut->last2DLevel = IsMicroTiled(nextTileMode);
2820 }
2821 }
2822
2823 /**
2824 ****************************************************************************************************
2825 * SiLib::HwlDegradeThickTileMode
2826 *
2827 * @brief
2828 * Degrades valid tile mode for thick modes if needed
2829 *
2830 * @return
2831 * Suitable tile mode
2832 ****************************************************************************************************
2833 */
HwlDegradeThickTileMode(AddrTileMode baseTileMode,UINT_32 numSlices,UINT_32 * pBytesPerTile) const2834 AddrTileMode SiLib::HwlDegradeThickTileMode(
2835 AddrTileMode baseTileMode, ///< base tile mode
2836 UINT_32 numSlices, ///< current number of slices
2837 UINT_32* pBytesPerTile ///< [in,out] pointer to bytes per slice
2838 ) const
2839 {
2840 return EgBasedLib::HwlDegradeThickTileMode(baseTileMode, numSlices, pBytesPerTile);
2841 }
2842
2843 /**
2844 ****************************************************************************************************
2845 * SiLib::HwlTileInfoEqual
2846 *
2847 * @brief
2848 * Return TRUE if all field are equal
2849 * @note
2850 * Only takes care of current HWL's data
2851 ****************************************************************************************************
2852 */
HwlTileInfoEqual(const ADDR_TILEINFO * pLeft,const ADDR_TILEINFO * pRight) const2853 BOOL_32 SiLib::HwlTileInfoEqual(
2854 const ADDR_TILEINFO* pLeft, ///<[in] Left compare operand
2855 const ADDR_TILEINFO* pRight ///<[in] Right compare operand
2856 ) const
2857 {
2858 BOOL_32 equal = FALSE;
2859
2860 if (pLeft->pipeConfig == pRight->pipeConfig)
2861 {
2862 equal = EgBasedLib::HwlTileInfoEqual(pLeft, pRight);
2863 }
2864
2865 return equal;
2866 }
2867
2868 /**
2869 ****************************************************************************************************
2870 * SiLib::GetTileSettings
2871 *
2872 * @brief
2873 * Get tile setting infos by index.
2874 * @return
2875 * Tile setting info.
2876 ****************************************************************************************************
2877 */
GetTileSetting(UINT_32 index) const2878 const TileConfig* SiLib::GetTileSetting(
2879 UINT_32 index ///< [in] Tile index
2880 ) const
2881 {
2882 ADDR_ASSERT(index < m_noOfEntries);
2883 return &m_tileTable[index];
2884 }
2885
2886 /**
2887 ****************************************************************************************************
2888 * SiLib::HwlPostCheckTileIndex
2889 *
2890 * @brief
2891 * Map a tile setting to index if curIndex is invalid, otherwise check if curIndex matches
2892 * tile mode/type/info and change the index if needed
2893 * @return
2894 * Tile index.
2895 ****************************************************************************************************
2896 */
HwlPostCheckTileIndex(const ADDR_TILEINFO * pInfo,AddrTileMode mode,AddrTileType type,INT curIndex) const2897 INT_32 SiLib::HwlPostCheckTileIndex(
2898 const ADDR_TILEINFO* pInfo, ///< [in] Tile Info
2899 AddrTileMode mode, ///< [in] Tile mode
2900 AddrTileType type, ///< [in] Tile type
2901 INT curIndex ///< [in] Current index assigned in HwlSetupTileInfo
2902 ) const
2903 {
2904 INT_32 index = curIndex;
2905
2906 if (mode == ADDR_TM_LINEAR_GENERAL)
2907 {
2908 index = TileIndexLinearGeneral;
2909 }
2910 else
2911 {
2912 BOOL_32 macroTiled = IsMacroTiled(mode);
2913
2914 // We need to find a new index if either of them is true
2915 // 1. curIndex is invalid
2916 // 2. tile mode is changed
2917 // 3. tile info does not match for macro tiled
2918 if ((index == TileIndexInvalid ||
2919 (mode != m_tileTable[index].mode) ||
2920 (macroTiled && (HwlTileInfoEqual(pInfo, &m_tileTable[index].info) == FALSE))))
2921 {
2922 for (index = 0; index < static_cast<INT_32>(m_noOfEntries); index++)
2923 {
2924 if (macroTiled)
2925 {
2926 // macro tile modes need all to match
2927 if (HwlTileInfoEqual(pInfo, &m_tileTable[index].info) &&
2928 (mode == m_tileTable[index].mode) &&
2929 (type == m_tileTable[index].type))
2930 {
2931 break;
2932 }
2933 }
2934 else if (mode == ADDR_TM_LINEAR_ALIGNED)
2935 {
2936 // linear mode only needs tile mode to match
2937 if (mode == m_tileTable[index].mode)
2938 {
2939 break;
2940 }
2941 }
2942 else
2943 {
2944 // micro tile modes only need tile mode and tile type to match
2945 if (mode == m_tileTable[index].mode &&
2946 type == m_tileTable[index].type)
2947 {
2948 break;
2949 }
2950 }
2951 }
2952 }
2953 }
2954
2955 ADDR_ASSERT(index < static_cast<INT_32>(m_noOfEntries));
2956
2957 if (index >= static_cast<INT_32>(m_noOfEntries))
2958 {
2959 index = TileIndexInvalid;
2960 }
2961
2962 return index;
2963 }
2964
2965 /**
2966 ****************************************************************************************************
2967 * SiLib::HwlSetupTileCfg
2968 *
2969 * @brief
2970 * Map tile index to tile setting.
2971 * @return
2972 * ADDR_E_RETURNCODE
2973 ****************************************************************************************************
2974 */
HwlSetupTileCfg(UINT_32 bpp,INT_32 index,INT_32 macroModeIndex,ADDR_TILEINFO * pInfo,AddrTileMode * pMode,AddrTileType * pType) const2975 ADDR_E_RETURNCODE SiLib::HwlSetupTileCfg(
2976 UINT_32 bpp, ///< Bits per pixel
2977 INT_32 index, ///< Tile index
2978 INT_32 macroModeIndex, ///< Index in macro tile mode table(CI)
2979 ADDR_TILEINFO* pInfo, ///< [out] Tile Info
2980 AddrTileMode* pMode, ///< [out] Tile mode
2981 AddrTileType* pType ///< [out] Tile type
2982 ) const
2983 {
2984 ADDR_E_RETURNCODE returnCode = ADDR_OK;
2985
2986 // Global flag to control usage of tileIndex
2987 if (UseTileIndex(index))
2988 {
2989 if (index == TileIndexLinearGeneral)
2990 {
2991 if (pMode)
2992 {
2993 *pMode = ADDR_TM_LINEAR_GENERAL;
2994 }
2995
2996 if (pType)
2997 {
2998 *pType = ADDR_DISPLAYABLE;
2999 }
3000
3001 if (pInfo)
3002 {
3003 pInfo->banks = 2;
3004 pInfo->bankWidth = 1;
3005 pInfo->bankHeight = 1;
3006 pInfo->macroAspectRatio = 1;
3007 pInfo->tileSplitBytes = 64;
3008 pInfo->pipeConfig = ADDR_PIPECFG_P2;
3009 }
3010 }
3011 else if (static_cast<UINT_32>(index) >= m_noOfEntries)
3012 {
3013 returnCode = ADDR_INVALIDPARAMS;
3014 }
3015 else
3016 {
3017 const TileConfig* pCfgTable = GetTileSetting(index);
3018
3019 if (pInfo)
3020 {
3021 *pInfo = pCfgTable->info;
3022 }
3023 else
3024 {
3025 if (IsMacroTiled(pCfgTable->mode))
3026 {
3027 returnCode = ADDR_INVALIDPARAMS;
3028 }
3029 }
3030
3031 if (pMode)
3032 {
3033 *pMode = pCfgTable->mode;
3034 }
3035
3036 if (pType)
3037 {
3038 *pType = pCfgTable->type;
3039 }
3040 }
3041 }
3042
3043 return returnCode;
3044 }
3045
3046 /**
3047 ****************************************************************************************************
3048 * SiLib::ReadGbTileMode
3049 *
3050 * @brief
3051 * Convert GB_TILE_MODE HW value to TileConfig.
3052 * @return
3053 * NA.
3054 ****************************************************************************************************
3055 */
ReadGbTileMode(UINT_32 regValue,TileConfig * pCfg) const3056 VOID SiLib::ReadGbTileMode(
3057 UINT_32 regValue, ///< [in] GB_TILE_MODE register
3058 TileConfig* pCfg ///< [out] output structure
3059 ) const
3060 {
3061 GB_TILE_MODE gbTileMode;
3062 gbTileMode.val = regValue;
3063
3064 pCfg->type = static_cast<AddrTileType>(gbTileMode.f.micro_tile_mode);
3065 pCfg->info.bankHeight = 1 << gbTileMode.f.bank_height;
3066 pCfg->info.bankWidth = 1 << gbTileMode.f.bank_width;
3067 pCfg->info.banks = 1 << (gbTileMode.f.num_banks + 1);
3068 pCfg->info.macroAspectRatio = 1 << gbTileMode.f.macro_tile_aspect;
3069 pCfg->info.tileSplitBytes = 64 << gbTileMode.f.tile_split;
3070 pCfg->info.pipeConfig = static_cast<AddrPipeCfg>(gbTileMode.f.pipe_config + 1);
3071
3072 UINT_32 regArrayMode = gbTileMode.f.array_mode;
3073
3074 pCfg->mode = static_cast<AddrTileMode>(regArrayMode);
3075
3076 if (regArrayMode == 8) //ARRAY_2D_TILED_XTHICK
3077 {
3078 pCfg->mode = ADDR_TM_2D_TILED_XTHICK;
3079 }
3080 else if (regArrayMode >= 14) //ARRAY_3D_TILED_XTHICK
3081 {
3082 pCfg->mode = static_cast<AddrTileMode>(pCfg->mode + 3);
3083 }
3084 }
3085
3086 /**
3087 ****************************************************************************************************
3088 * SiLib::InitTileSettingTable
3089 *
3090 * @brief
3091 * Initialize the ADDR_TILE_CONFIG table.
3092 * @return
3093 * TRUE if tile table is correctly initialized
3094 ****************************************************************************************************
3095 */
InitTileSettingTable(const UINT_32 * pCfg,UINT_32 noOfEntries)3096 BOOL_32 SiLib::InitTileSettingTable(
3097 const UINT_32* pCfg, ///< [in] Pointer to table of tile configs
3098 UINT_32 noOfEntries ///< [in] Numbe of entries in the table above
3099 )
3100 {
3101 BOOL_32 initOk = TRUE;
3102
3103 ADDR_ASSERT(noOfEntries <= TileTableSize);
3104
3105 memset(m_tileTable, 0, sizeof(m_tileTable));
3106
3107 if (noOfEntries != 0)
3108 {
3109 m_noOfEntries = noOfEntries;
3110 }
3111 else
3112 {
3113 m_noOfEntries = TileTableSize;
3114 }
3115
3116 if (pCfg) // From Client
3117 {
3118 for (UINT_32 i = 0; i < m_noOfEntries; i++)
3119 {
3120 ReadGbTileMode(*(pCfg + i), &m_tileTable[i]);
3121 }
3122 }
3123 else
3124 {
3125 ADDR_ASSERT_ALWAYS();
3126 initOk = FALSE;
3127 }
3128
3129 if (initOk)
3130 {
3131 ADDR_ASSERT(m_tileTable[TILEINDEX_LINEAR_ALIGNED].mode == ADDR_TM_LINEAR_ALIGNED);
3132 }
3133
3134 return initOk;
3135 }
3136
3137 /**
3138 ****************************************************************************************************
3139 * SiLib::HwlGetTileIndex
3140 *
3141 * @brief
3142 * Return the virtual/real index for given mode/type/info
3143 * @return
3144 * ADDR_OK if successful.
3145 ****************************************************************************************************
3146 */
HwlGetTileIndex(const ADDR_GET_TILEINDEX_INPUT * pIn,ADDR_GET_TILEINDEX_OUTPUT * pOut) const3147 ADDR_E_RETURNCODE SiLib::HwlGetTileIndex(
3148 const ADDR_GET_TILEINDEX_INPUT* pIn,
3149 ADDR_GET_TILEINDEX_OUTPUT* pOut) const
3150 {
3151 ADDR_E_RETURNCODE returnCode = ADDR_OK;
3152
3153 pOut->index = HwlPostCheckTileIndex(pIn->pTileInfo, pIn->tileMode, pIn->tileType);
3154
3155 return returnCode;
3156 }
3157
3158 /**
3159 ****************************************************************************************************
3160 * SiLib::HwlFmaskPreThunkSurfInfo
3161 *
3162 * @brief
3163 * Some preparation before thunking a ComputeSurfaceInfo call for Fmask
3164 * @return
3165 * ADDR_E_RETURNCODE
3166 ****************************************************************************************************
3167 */
HwlFmaskPreThunkSurfInfo(const ADDR_COMPUTE_FMASK_INFO_INPUT * pFmaskIn,const ADDR_COMPUTE_FMASK_INFO_OUTPUT * pFmaskOut,ADDR_COMPUTE_SURFACE_INFO_INPUT * pSurfIn,ADDR_COMPUTE_SURFACE_INFO_OUTPUT * pSurfOut) const3168 VOID SiLib::HwlFmaskPreThunkSurfInfo(
3169 const ADDR_COMPUTE_FMASK_INFO_INPUT* pFmaskIn, ///< [in] Input of fmask info
3170 const ADDR_COMPUTE_FMASK_INFO_OUTPUT* pFmaskOut, ///< [in] Output of fmask info
3171 ADDR_COMPUTE_SURFACE_INFO_INPUT* pSurfIn, ///< [out] Input of thunked surface info
3172 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pSurfOut ///< [out] Output of thunked surface info
3173 ) const
3174 {
3175 pSurfIn->tileIndex = pFmaskIn->tileIndex;
3176 }
3177
3178 /**
3179 ****************************************************************************************************
3180 * SiLib::HwlFmaskPostThunkSurfInfo
3181 *
3182 * @brief
3183 * Copy hwl extra field after calling thunked ComputeSurfaceInfo
3184 * @return
3185 * ADDR_E_RETURNCODE
3186 ****************************************************************************************************
3187 */
HwlFmaskPostThunkSurfInfo(const ADDR_COMPUTE_SURFACE_INFO_OUTPUT * pSurfOut,ADDR_COMPUTE_FMASK_INFO_OUTPUT * pFmaskOut) const3188 VOID SiLib::HwlFmaskPostThunkSurfInfo(
3189 const ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pSurfOut, ///< [in] Output of surface info
3190 ADDR_COMPUTE_FMASK_INFO_OUTPUT* pFmaskOut ///< [out] Output of fmask info
3191 ) const
3192 {
3193 pFmaskOut->macroModeIndex = TileIndexInvalid;
3194 pFmaskOut->tileIndex = pSurfOut->tileIndex;
3195 }
3196
3197 /**
3198 ****************************************************************************************************
3199 * SiLib::HwlComputeFmaskBits
3200 * @brief
3201 * Computes fmask bits
3202 * @return
3203 * Fmask bits
3204 ****************************************************************************************************
3205 */
HwlComputeFmaskBits(const ADDR_COMPUTE_FMASK_INFO_INPUT * pIn,UINT_32 * pNumSamples) const3206 UINT_32 SiLib::HwlComputeFmaskBits(
3207 const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn,
3208 UINT_32* pNumSamples
3209 ) const
3210 {
3211 UINT_32 numSamples = pIn->numSamples;
3212 UINT_32 numFrags = GetNumFragments(numSamples, pIn->numFrags);
3213 UINT_32 bpp;
3214
3215 if (numFrags != numSamples) // EQAA
3216 {
3217 ADDR_ASSERT(numFrags <= 8);
3218
3219 if (pIn->resolved == FALSE)
3220 {
3221 if (numFrags == 1)
3222 {
3223 bpp = 1;
3224 numSamples = numSamples == 16 ? 16 : 8;
3225 }
3226 else if (numFrags == 2)
3227 {
3228 ADDR_ASSERT(numSamples >= 4);
3229
3230 bpp = 2;
3231 numSamples = numSamples;
3232 }
3233 else if (numFrags == 4)
3234 {
3235 ADDR_ASSERT(numSamples >= 4);
3236
3237 bpp = 4;
3238 numSamples = numSamples;
3239 }
3240 else // numFrags == 8
3241 {
3242 ADDR_ASSERT(numSamples == 16);
3243
3244 bpp = 4;
3245 numSamples = numSamples;
3246 }
3247 }
3248 else
3249 {
3250 if (numFrags == 1)
3251 {
3252 bpp = (numSamples == 16) ? 16 : 8;
3253 numSamples = 1;
3254 }
3255 else if (numFrags == 2)
3256 {
3257 ADDR_ASSERT(numSamples >= 4);
3258
3259 bpp = numSamples*2;
3260 numSamples = 1;
3261 }
3262 else if (numFrags == 4)
3263 {
3264 ADDR_ASSERT(numSamples >= 4);
3265
3266 bpp = numSamples*4;
3267 numSamples = 1;
3268 }
3269 else // numFrags == 8
3270 {
3271 ADDR_ASSERT(numSamples >= 16);
3272
3273 bpp = 16*4;
3274 numSamples = 1;
3275 }
3276 }
3277 }
3278 else // Normal AA
3279 {
3280 if (pIn->resolved == FALSE)
3281 {
3282 bpp = ComputeFmaskNumPlanesFromNumSamples(numSamples);
3283 numSamples = numSamples == 2 ? 8 : numSamples;
3284 }
3285 else
3286 {
3287 // The same as 8XX
3288 bpp = ComputeFmaskResolvedBppFromNumSamples(numSamples);
3289 numSamples = 1; // 1x sample
3290 }
3291 }
3292
3293 SafeAssign(pNumSamples, numSamples);
3294
3295 return bpp;
3296 }
3297
3298 /**
3299 ****************************************************************************************************
3300 * SiLib::HwlOptimizeTileMode
3301 *
3302 * @brief
3303 * Optimize tile mode on SI
3304 *
3305 * @return
3306 * N/A
3307 *
3308 ****************************************************************************************************
3309 */
HwlOptimizeTileMode(ADDR_COMPUTE_SURFACE_INFO_INPUT * pInOut) const3310 VOID SiLib::HwlOptimizeTileMode(
3311 ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut ///< [in,out] input output structure
3312 ) const
3313 {
3314 AddrTileMode tileMode = pInOut->tileMode;
3315
3316 if ((pInOut->flags.needEquation == TRUE) &&
3317 (IsMacroTiled(tileMode) == TRUE) &&
3318 (pInOut->numSamples <= 1))
3319 {
3320 UINT_32 thickness = Thickness(tileMode);
3321
3322 if (thickness > 1)
3323 {
3324 tileMode = ADDR_TM_1D_TILED_THICK;
3325 }
3326 else if (pInOut->numSlices > 1)
3327 {
3328 tileMode = ADDR_TM_1D_TILED_THIN1;
3329 }
3330 else
3331 {
3332 tileMode = ADDR_TM_2D_TILED_THIN1;
3333 }
3334 }
3335
3336 if (tileMode != pInOut->tileMode)
3337 {
3338 pInOut->tileMode = tileMode;
3339 }
3340 }
3341
3342 /**
3343 ****************************************************************************************************
3344 * SiLib::HwlOverrideTileMode
3345 *
3346 * @brief
3347 * Override tile modes (for PRT only, avoid client passes in an invalid PRT mode for SI.
3348 *
3349 * @return
3350 * N/A
3351 *
3352 ****************************************************************************************************
3353 */
HwlOverrideTileMode(ADDR_COMPUTE_SURFACE_INFO_INPUT * pInOut) const3354 VOID SiLib::HwlOverrideTileMode(
3355 ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut ///< [in,out] input output structure
3356 ) const
3357 {
3358 AddrTileMode tileMode = pInOut->tileMode;
3359
3360 switch (tileMode)
3361 {
3362 case ADDR_TM_PRT_TILED_THIN1:
3363 tileMode = ADDR_TM_2D_TILED_THIN1;
3364 break;
3365
3366 case ADDR_TM_PRT_TILED_THICK:
3367 tileMode = ADDR_TM_2D_TILED_THICK;
3368 break;
3369
3370 case ADDR_TM_PRT_2D_TILED_THICK:
3371 tileMode = ADDR_TM_2D_TILED_THICK;
3372 break;
3373
3374 case ADDR_TM_PRT_3D_TILED_THICK:
3375 tileMode = ADDR_TM_3D_TILED_THICK;
3376 break;
3377
3378 default:
3379 break;
3380 }
3381
3382 if (tileMode != pInOut->tileMode)
3383 {
3384 pInOut->tileMode = tileMode;
3385 // Only PRT tile modes are overridden for now. Revisit this once new modes are added above.
3386 pInOut->flags.prt = TRUE;
3387 }
3388 }
3389
3390 /**
3391 ****************************************************************************************************
3392 * SiLib::HwlSetPrtTileMode
3393 *
3394 * @brief
3395 * Set prt tile modes.
3396 *
3397 * @return
3398 * N/A
3399 *
3400 ****************************************************************************************************
3401 */
HwlSetPrtTileMode(ADDR_COMPUTE_SURFACE_INFO_INPUT * pInOut) const3402 VOID SiLib::HwlSetPrtTileMode(
3403 ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut ///< [in,out] input output structure
3404 ) const
3405 {
3406 pInOut->tileMode = ADDR_TM_2D_TILED_THIN1;
3407 pInOut->tileType = (pInOut->tileType == ADDR_DEPTH_SAMPLE_ORDER) ?
3408 ADDR_DEPTH_SAMPLE_ORDER : ADDR_NON_DISPLAYABLE;
3409 pInOut->flags.prt = TRUE;
3410 }
3411
3412 /**
3413 ****************************************************************************************************
3414 * SiLib::HwlSelectTileMode
3415 *
3416 * @brief
3417 * Select tile modes.
3418 *
3419 * @return
3420 * N/A
3421 *
3422 ****************************************************************************************************
3423 */
HwlSelectTileMode(ADDR_COMPUTE_SURFACE_INFO_INPUT * pInOut) const3424 VOID SiLib::HwlSelectTileMode(
3425 ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut ///< [in,out] input output structure
3426 ) const
3427 {
3428 AddrTileMode tileMode;
3429 AddrTileType tileType;
3430
3431 if (pInOut->flags.volume)
3432 {
3433 if (pInOut->numSlices >= 8)
3434 {
3435 tileMode = ADDR_TM_2D_TILED_XTHICK;
3436 }
3437 else if (pInOut->numSlices >= 4)
3438 {
3439 tileMode = ADDR_TM_2D_TILED_THICK;
3440 }
3441 else
3442 {
3443 tileMode = ADDR_TM_2D_TILED_THIN1;
3444 }
3445 tileType = ADDR_NON_DISPLAYABLE;
3446 }
3447 else
3448 {
3449 tileMode = ADDR_TM_2D_TILED_THIN1;
3450
3451 if (pInOut->flags.depth || pInOut->flags.stencil)
3452 {
3453 tileType = ADDR_DEPTH_SAMPLE_ORDER;
3454 }
3455 else if ((pInOut->bpp <= 32) ||
3456 (pInOut->flags.display == TRUE) ||
3457 (pInOut->flags.overlay == TRUE))
3458 {
3459 tileType = ADDR_DISPLAYABLE;
3460 }
3461 else
3462 {
3463 tileType = ADDR_NON_DISPLAYABLE;
3464 }
3465 }
3466
3467 if (pInOut->flags.prt)
3468 {
3469 tileMode = ADDR_TM_2D_TILED_THIN1;
3470 tileType = (tileType == ADDR_DISPLAYABLE) ? ADDR_NON_DISPLAYABLE : tileType;
3471 }
3472
3473 pInOut->tileMode = tileMode;
3474 pInOut->tileType = tileType;
3475
3476 // Optimize tile mode if possible
3477 pInOut->flags.opt4Space = TRUE;
3478
3479 // Optimize tile mode if possible
3480 OptimizeTileMode(pInOut);
3481
3482 HwlOverrideTileMode(pInOut);
3483 }
3484
3485 /**
3486 ****************************************************************************************************
3487 * SiLib::HwlComputeMaxBaseAlignments
3488 *
3489 * @brief
3490 * Gets maximum alignments
3491 * @return
3492 * maximum alignments
3493 ****************************************************************************************************
3494 */
HwlComputeMaxBaseAlignments() const3495 UINT_32 SiLib::HwlComputeMaxBaseAlignments() const
3496 {
3497 const UINT_32 pipes = HwlGetPipes(&m_tileTable[0].info);
3498
3499 // Initial size is 64 KiB for PRT.
3500 UINT_32 maxBaseAlign = 64 * 1024;
3501
3502 for (UINT_32 i = 0; i < m_noOfEntries; i++)
3503 {
3504 if ((IsMacroTiled(m_tileTable[i].mode) == TRUE) &&
3505 (IsPrtTileMode(m_tileTable[i].mode) == FALSE))
3506 {
3507 // The maximum tile size is 16 byte-per-pixel and either 8-sample or 8-slice.
3508 UINT_32 tileSize = Min(m_tileTable[i].info.tileSplitBytes,
3509 MicroTilePixels * 8 * 16);
3510
3511 UINT_32 baseAlign = tileSize * pipes * m_tileTable[i].info.banks *
3512 m_tileTable[i].info.bankWidth * m_tileTable[i].info.bankHeight;
3513
3514 if (baseAlign > maxBaseAlign)
3515 {
3516 maxBaseAlign = baseAlign;
3517 }
3518 }
3519 }
3520
3521 return maxBaseAlign;
3522 }
3523
3524 /**
3525 ****************************************************************************************************
3526 * SiLib::HwlComputeMaxMetaBaseAlignments
3527 *
3528 * @brief
3529 * Gets maximum alignments for metadata
3530 * @return
3531 * maximum alignments for metadata
3532 ****************************************************************************************************
3533 */
HwlComputeMaxMetaBaseAlignments() const3534 UINT_32 SiLib::HwlComputeMaxMetaBaseAlignments() const
3535 {
3536 UINT_32 maxPipe = 1;
3537
3538 for (UINT_32 i = 0; i < m_noOfEntries; i++)
3539 {
3540 maxPipe = Max(maxPipe, HwlGetPipes(&m_tileTable[i].info));
3541 }
3542
3543 return m_pipeInterleaveBytes * maxPipe;
3544 }
3545
3546 /**
3547 ****************************************************************************************************
3548 * SiLib::HwlComputeSurfaceAlignmentsMacroTiled
3549 *
3550 * @brief
3551 * Hardware layer function to compute alignment request for macro tile mode
3552 *
3553 * @return
3554 * N/A
3555 *
3556 ****************************************************************************************************
3557 */
HwlComputeSurfaceAlignmentsMacroTiled(AddrTileMode tileMode,UINT_32 bpp,ADDR_SURFACE_FLAGS flags,UINT_32 mipLevel,UINT_32 numSamples,ADDR_COMPUTE_SURFACE_INFO_OUTPUT * pOut) const3558 VOID SiLib::HwlComputeSurfaceAlignmentsMacroTiled(
3559 AddrTileMode tileMode, ///< [in] tile mode
3560 UINT_32 bpp, ///< [in] bits per pixel
3561 ADDR_SURFACE_FLAGS flags, ///< [in] surface flags
3562 UINT_32 mipLevel, ///< [in] mip level
3563 UINT_32 numSamples, ///< [in] number of samples
3564 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut ///< [in,out] Surface output
3565 ) const
3566 {
3567 if ((mipLevel == 0) && (flags.prt))
3568 {
3569 UINT_32 macroTileSize = pOut->blockWidth * pOut->blockHeight * numSamples * bpp / 8;
3570
3571 if (macroTileSize < PrtTileSize)
3572 {
3573 UINT_32 numMacroTiles = PrtTileSize / macroTileSize;
3574
3575 ADDR_ASSERT((PrtTileSize % macroTileSize) == 0);
3576
3577 pOut->pitchAlign *= numMacroTiles;
3578 pOut->baseAlign *= numMacroTiles;
3579 }
3580 }
3581 }
3582
3583 /**
3584 ****************************************************************************************************
3585 * SiLib::InitEquationTable
3586 *
3587 * @brief
3588 * Initialize Equation table.
3589 *
3590 * @return
3591 * N/A
3592 ****************************************************************************************************
3593 */
InitEquationTable()3594 VOID SiLib::InitEquationTable()
3595 {
3596 ADDR_EQUATION_KEY equationKeyTable[EquationTableSize];
3597 memset(equationKeyTable, 0, sizeof(equationKeyTable));
3598
3599 memset(m_equationTable, 0, sizeof(m_equationTable));
3600
3601 memset(m_blockWidth, 0, sizeof(m_blockWidth));
3602
3603 memset(m_blockHeight, 0, sizeof(m_blockHeight));
3604
3605 memset(m_blockSlices, 0, sizeof(m_blockSlices));
3606
3607 // Loop all possible bpp
3608 for (UINT_32 log2ElementBytes = 0; log2ElementBytes < MaxNumElementBytes; log2ElementBytes++)
3609 {
3610 // Get bits per pixel
3611 UINT_32 bpp = 1 << (log2ElementBytes + 3);
3612
3613 // Loop all possible tile index
3614 for (INT_32 tileIndex = 0; tileIndex < static_cast<INT_32>(m_noOfEntries); tileIndex++)
3615 {
3616 UINT_32 equationIndex = ADDR_INVALID_EQUATION_INDEX;
3617
3618 TileConfig tileConfig = m_tileTable[tileIndex];
3619
3620 ADDR_SURFACE_FLAGS flags = {{0}};
3621
3622 // Compute tile info, hardcode numSamples to 1 because MSAA is not supported
3623 // in swizzle pattern equation
3624 HwlComputeMacroModeIndex(tileIndex, flags, bpp, 1, &tileConfig.info, NULL, NULL);
3625
3626 // Check if the input is supported
3627 if (IsEquationSupported(bpp, tileConfig, tileIndex, log2ElementBytes) == TRUE)
3628 {
3629 ADDR_EQUATION_KEY key = {{0}};
3630
3631 // Generate swizzle equation key from bpp and tile config
3632 key.fields.log2ElementBytes = log2ElementBytes;
3633 key.fields.tileMode = tileConfig.mode;
3634 // Treat depth micro tile type and non-display micro tile type as the same key
3635 // because they have the same equation actually
3636 key.fields.microTileType = (tileConfig.type == ADDR_DEPTH_SAMPLE_ORDER) ?
3637 ADDR_NON_DISPLAYABLE : tileConfig.type;
3638 key.fields.pipeConfig = tileConfig.info.pipeConfig;
3639 key.fields.numBanksLog2 = Log2(tileConfig.info.banks);
3640 key.fields.bankWidth = tileConfig.info.bankWidth;
3641 key.fields.bankHeight = tileConfig.info.bankHeight;
3642 key.fields.macroAspectRatio = tileConfig.info.macroAspectRatio;
3643 key.fields.prt = ((m_chipFamily == ADDR_CHIP_FAMILY_SI) &&
3644 ((1 << tileIndex) & SiPrtTileIndexMask)) ? 1 : 0;
3645
3646 // Find in the table if the equation has been built based on the key
3647 for (UINT_32 i = 0; i < m_numEquations; i++)
3648 {
3649 if (key.value == equationKeyTable[i].value)
3650 {
3651 equationIndex = i;
3652 break;
3653 }
3654 }
3655
3656 // If found, just fill the index into the lookup table and no need
3657 // to generate the equation again. Otherwise, generate the equation.
3658 if (equationIndex == ADDR_INVALID_EQUATION_INDEX)
3659 {
3660 ADDR_EQUATION equation;
3661 ADDR_E_RETURNCODE retCode;
3662
3663 memset(&equation, 0, sizeof(ADDR_EQUATION));
3664
3665 // Generate the equation
3666 if (IsMicroTiled(tileConfig.mode))
3667 {
3668 retCode = ComputeMicroTileEquation(log2ElementBytes,
3669 tileConfig.mode,
3670 tileConfig.type,
3671 &equation);
3672 }
3673 else
3674 {
3675 retCode = ComputeMacroTileEquation(log2ElementBytes,
3676 tileConfig.mode,
3677 tileConfig.type,
3678 &tileConfig.info,
3679 &equation);
3680 }
3681 // Only fill the equation into the table if the return code is ADDR_OK,
3682 // otherwise if the return code is not ADDR_OK, it indicates this is not
3683 // a valid input, we do nothing but just fill invalid equation index
3684 // into the lookup table.
3685 if (retCode == ADDR_OK)
3686 {
3687 equationIndex = m_numEquations;
3688 ADDR_ASSERT(equationIndex < EquationTableSize);
3689
3690 m_blockSlices[equationIndex] = Thickness(tileConfig.mode);
3691
3692 if (IsMicroTiled(tileConfig.mode))
3693 {
3694 m_blockWidth[equationIndex] = MicroTileWidth;
3695 m_blockHeight[equationIndex] = MicroTileHeight;
3696 }
3697 else
3698 {
3699 const ADDR_TILEINFO* pTileInfo = &tileConfig.info;
3700
3701 m_blockWidth[equationIndex] =
3702 HwlGetPipes(pTileInfo) * MicroTileWidth * pTileInfo->bankWidth *
3703 pTileInfo->macroAspectRatio;
3704 m_blockHeight[equationIndex] =
3705 MicroTileHeight * pTileInfo->bankHeight * pTileInfo->banks /
3706 pTileInfo->macroAspectRatio;
3707
3708 if (key.fields.prt)
3709 {
3710 UINT_32 macroTileSize =
3711 m_blockWidth[equationIndex] * m_blockHeight[equationIndex] *
3712 bpp / 8;
3713
3714 if (macroTileSize < PrtTileSize)
3715 {
3716 UINT_32 numMacroTiles = PrtTileSize / macroTileSize;
3717
3718 ADDR_ASSERT(macroTileSize == (1u << equation.numBits));
3719 ADDR_ASSERT((PrtTileSize % macroTileSize) == 0);
3720
3721 UINT_32 numBits = Log2(numMacroTiles);
3722
3723 UINT_32 xStart = Log2(m_blockWidth[equationIndex]) +
3724 log2ElementBytes;
3725
3726 m_blockWidth[equationIndex] *= numMacroTiles;
3727
3728 for (UINT_32 i = 0; i < numBits; i++)
3729 {
3730 equation.addr[equation.numBits + i].valid = 1;
3731 equation.addr[equation.numBits + i].index = xStart + i;
3732 }
3733
3734 equation.numBits += numBits;
3735 }
3736 }
3737 }
3738
3739 equationKeyTable[equationIndex] = key;
3740 m_equationTable[equationIndex] = equation;
3741
3742 m_numEquations++;
3743 }
3744 }
3745 }
3746
3747 // Fill the index into the lookup table, if the combination is not supported
3748 // fill the invalid equation index
3749 m_equationLookupTable[log2ElementBytes][tileIndex] = equationIndex;
3750 }
3751
3752 if (m_chipFamily == ADDR_CHIP_FAMILY_SI)
3753 {
3754 // For tile index 3 which is shared between PRT depth and uncompressed depth
3755 m_uncompressDepthEqIndex = m_numEquations;
3756
3757 for (UINT_32 log2ElemBytes = 0; log2ElemBytes < MaxNumElementBytes; log2ElemBytes++)
3758 {
3759 TileConfig tileConfig = m_tileTable[3];
3760 ADDR_EQUATION equation;
3761 ADDR_E_RETURNCODE retCode;
3762
3763 memset(&equation, 0, sizeof(ADDR_EQUATION));
3764
3765 retCode = ComputeMacroTileEquation(log2ElemBytes,
3766 tileConfig.mode,
3767 tileConfig.type,
3768 &tileConfig.info,
3769 &equation);
3770
3771 if (retCode == ADDR_OK)
3772 {
3773 UINT_32 equationIndex = m_numEquations;
3774 ADDR_ASSERT(equationIndex < EquationTableSize);
3775
3776 m_blockSlices[equationIndex] = 1;
3777
3778 const ADDR_TILEINFO* pTileInfo = &tileConfig.info;
3779
3780 m_blockWidth[equationIndex] =
3781 HwlGetPipes(pTileInfo) * MicroTileWidth * pTileInfo->bankWidth *
3782 pTileInfo->macroAspectRatio;
3783 m_blockHeight[equationIndex] =
3784 MicroTileHeight * pTileInfo->bankHeight * pTileInfo->banks /
3785 pTileInfo->macroAspectRatio;
3786
3787 m_equationTable[equationIndex] = equation;
3788
3789 m_numEquations++;
3790 }
3791 }
3792 }
3793 }
3794 }
3795
3796 /**
3797 ****************************************************************************************************
3798 * SiLib::IsEquationSupported
3799 *
3800 * @brief
3801 * Check if it is supported for given bpp and tile config to generate a equation.
3802 *
3803 * @return
3804 * TRUE if supported
3805 ****************************************************************************************************
3806 */
IsEquationSupported(UINT_32 bpp,TileConfig tileConfig,INT_32 tileIndex,UINT_32 elementBytesLog2) const3807 BOOL_32 SiLib::IsEquationSupported(
3808 UINT_32 bpp, ///< Bits per pixel
3809 TileConfig tileConfig, ///< Tile config
3810 INT_32 tileIndex, ///< Tile index
3811 UINT_32 elementBytesLog2 ///< Log2 of element bytes
3812 ) const
3813 {
3814 BOOL_32 supported = TRUE;
3815
3816 // Linear tile mode is not supported in swizzle pattern equation
3817 if (IsLinear(tileConfig.mode))
3818 {
3819 supported = FALSE;
3820 }
3821 // These tile modes are for Tex2DArray and Tex3D which has depth (num_slice > 1) use,
3822 // which is not supported in swizzle pattern equation due to slice rotation
3823 else if ((tileConfig.mode == ADDR_TM_2D_TILED_THICK) ||
3824 (tileConfig.mode == ADDR_TM_2D_TILED_XTHICK) ||
3825 (tileConfig.mode == ADDR_TM_3D_TILED_THIN1) ||
3826 (tileConfig.mode == ADDR_TM_3D_TILED_THICK) ||
3827 (tileConfig.mode == ADDR_TM_3D_TILED_XTHICK))
3828 {
3829 supported = FALSE;
3830 }
3831 // Only 8bpp(stencil), 16bpp and 32bpp is supported for depth
3832 else if ((tileConfig.type == ADDR_DEPTH_SAMPLE_ORDER) && (bpp > 32))
3833 {
3834 supported = FALSE;
3835 }
3836 // Tile split is not supported in swizzle pattern equation
3837 else if (IsMacroTiled(tileConfig.mode))
3838 {
3839 UINT_32 thickness = Thickness(tileConfig.mode);
3840 if (((bpp >> 3) * MicroTilePixels * thickness) > tileConfig.info.tileSplitBytes)
3841 {
3842 supported = FALSE;
3843 }
3844
3845 if ((supported == TRUE) && (m_chipFamily == ADDR_CHIP_FAMILY_SI))
3846 {
3847 supported = m_EquationSupport[tileIndex][elementBytesLog2];
3848 }
3849 }
3850
3851 return supported;
3852 }
3853
3854 } // V1
3855 } // Addr
3856