1 /* 2 * Copyright © 2020 Valve Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 #include "helpers.h" 25 #include <stdarg.h> 26 27 using namespace aco; 28 29 BEGIN_TEST(validate.sdwa.allow) 30 for (unsigned i = GFX8; i <= GFX10; i++) { 31 //>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm 32 if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i)) 33 continue; 34 //>> Validation results: 35 //! Validation passed 36 37 SDWA_instruction* sdwa = 38 &bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1])->sdwa(); 39 sdwa->neg[0] = sdwa->neg[1] = sdwa->abs[0] = sdwa->abs[1] = true; 40 41 bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1b), inputs[0], inputs[1]); 42 43 sdwa = &bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1])->sdwa(); 44 sdwa->sel[0] = SubdwordSel::sbyte2; 45 sdwa->sel[1] = SubdwordSel::uword1; 46 47 finish_validator_test(); 48 } 49 END_TEST 50 51 BEGIN_TEST(validate.sdwa.support) 52 for (unsigned i = GFX7; i <= GFX11; i++) { 53 //>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm 54 if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i)) 55 continue; 56 //>> Validation results: 57 58 //~gfx(7|11)! SDWA is GFX8 to GFX10.3 only: v1: %t0 = v_mul_f32 %a, %b dst_sel:dword src0_sel:dword src1_sel:dword 59 //~gfx(7|11)! Validation failed 60 //~gfx([89]|10)! Validation passed 61 bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]); 62 63 finish_validator_test(); 64 } 65 END_TEST 66 67 BEGIN_TEST(validate.sdwa.operands) 68 for (unsigned i = GFX8; i <= GFX10; i++) { 69 //>> v1: %vgpr0, v1: %vgp1, s1: %sgpr0, s1: %sgpr1 = p_startpgm 70 if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i)) 71 continue; 72 //>> Validation results: 73 74 //~gfx8! Wrong source position for SGPR argument: v1: %_ = v_mul_f32 %sgpr0, %vgpr1 dst_sel:dword src0_sel:dword src1_sel:dword 75 //~gfx8! Wrong source position for SGPR argument: v1: %_ = v_mul_f32 %vgpr0, %sgpr1 dst_sel:dword src0_sel:dword src1_sel:dword 76 bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[2], inputs[1]); 77 bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[3]); 78 79 //~gfx8! Wrong source position for constant argument: v1: %_ = v_mul_f32 4, %vgpr1 dst_sel:dword src0_sel:dword src1_sel:dword 80 //~gfx8! Wrong source position for constant argument: v1: %_ = v_mul_f32 %vgpr0, 4 dst_sel:dword src0_sel:dword src1_sel:dword 81 bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), Operand::c32(4u), inputs[1]); 82 bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], Operand::c32(4u)); 83 84 //! Literal applied on wrong instruction format: v1: %_ = v_mul_f32 0x1234, %vgpr1 dst_sel:dword src0_sel:dword src1_sel:dword 85 //! Literal applied on wrong instruction format: v1: %_ = v_mul_f32 %vgpr0, 0x1234 dst_sel:dword src0_sel:dword src1_sel:dword 86 //! Wrong source position for Literal argument: v1: %_ = v_mul_f32 %vgpr0, 0x1234 dst_sel:dword src0_sel:dword src1_sel:dword 87 bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), Operand::c32(0x1234u), inputs[1]); 88 bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], Operand::c32(0x1234u)); 89 90 //! Validation failed 91 92 finish_validator_test(); 93 } 94 END_TEST 95 96 BEGIN_TEST(validate.sdwa.vopc) 97 for (unsigned i = GFX8; i <= GFX10; i++) { 98 //>> v1: %vgpr0, v1: %vgp1, s1: %sgpr0, s1: %sgpr1 = p_startpgm 99 if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i)) 100 continue; 101 //>> Validation results: 102 103 bld.vopc_sdwa(aco_opcode::v_cmp_gt_f32, bld.def(bld.lm, vcc), inputs[0], inputs[1]); 104 105 //~gfx8! SDWA+VOPC definition must be fixed to vcc on GFX8: s2: %_ = v_cmp_lt_f32 %vgpr0, %vgpr1 src0_sel:dword src1_sel:dword 106 bld.vopc_sdwa(aco_opcode::v_cmp_lt_f32, bld.def(bld.lm), inputs[0], inputs[1]); 107 108 //~gfx(9|10)! SDWA VOPC clamp only supported on GFX8: s2: %_:vcc = v_cmp_eq_f32 %vgpr0, %vgpr1 clamp src0_sel:dword src1_sel:dword 109 bld.vopc_sdwa(aco_opcode::v_cmp_eq_f32, bld.def(bld.lm, vcc), inputs[0], inputs[1]) 110 ->sdwa() 111 .clamp = true; 112 113 //! Validation failed 114 115 finish_validator_test(); 116 } 117 END_TEST 118 119 BEGIN_TEST(validate.sdwa.omod) 120 for (unsigned i = GFX8; i <= GFX10; i++) { 121 //>> v1: %vgpr0, v1: %vgp1, s1: %sgpr0, s1: %sgpr1 = p_startpgm 122 if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i)) 123 continue; 124 //>> Validation results: 125 126 //~gfx8! SDWA omod only supported on GFX9+: v1: %_ = v_mul_f32 %vgpr0, %vgpr1 *2 dst_sel:dword src0_sel:dword src1_sel:dword 127 //~gfx8! Validation failed 128 //~gfx(9|10)! Validation passed 129 bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1])->sdwa().omod = 1; 130 131 finish_validator_test(); 132 } 133 END_TEST 134 135 BEGIN_TEST(validate.sdwa.vcc) 136 for (unsigned i = GFX8; i <= GFX10; i++) { 137 //>> v1: %vgpr0, v1: %vgpr1, s2: %sgpr0 = p_startpgm 138 if (!setup_cs("v1 v1 s2", (amd_gfx_level)i)) 139 continue; 140 //>> Validation results: 141 142 //! 3rd operand must be fixed to vcc with SDWA: v1: %_ = v_cndmask_b32 %vgpr0, %vgpr1, %_ dst_sel:dword src0_sel:dword src1_sel:dword 143 bld.vop2_sdwa(aco_opcode::v_cndmask_b32, bld.def(v1), inputs[0], inputs[1], inputs[2]); 144 bld.vop2_sdwa(aco_opcode::v_cndmask_b32, bld.def(v1), inputs[0], inputs[1], 145 bld.vcc(inputs[2])); 146 147 //! 2nd definition must be fixed to vcc with SDWA: v1: %_, s2: %_ = v_add_co_u32 %vgpr0, %vgpr1 dst_sel:dword src0_sel:dword src1_sel:dword 148 bld.vop2_sdwa(aco_opcode::v_add_co_u32, bld.def(v1), bld.def(bld.lm), inputs[0], inputs[1]); 149 bld.vop2_sdwa(aco_opcode::v_add_co_u32, bld.def(v1), bld.def(bld.lm, vcc), inputs[0], 150 inputs[1]); 151 152 //! Validation failed 153 154 finish_validator_test(); 155 } 156 END_TEST 157 158 BEGIN_TEST(optimize.sdwa.extract) 159 for (unsigned i = GFX7; i <= GFX10; i++) { 160 for (unsigned is_signed = 0; is_signed <= 1; is_signed++) { 161 //>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm 162 if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i, CHIP_UNKNOWN, 163 is_signed ? "_signed" : "_unsigned")) 164 continue; 165 166 //; def standard_test(index, sel): 167 //; res = 'v1: %%res%s = v_mul_f32 %%a, %%b dst_sel:dword src0_sel:dword src1_sel:%c%s\n' % (index, 's' if variant.endswith('_signed') else 'u', sel) 168 //; res += 'p_unit_test %s, %%res%s' % (index, index) 169 //; return res 170 //; funcs['standard_test'] = lambda a: standard_test(*(v for v in a.split(','))) 171 172 aco_opcode ext = aco_opcode::p_extract; 173 aco_opcode ins = aco_opcode::p_insert; 174 175 { 176 //~gfx[^7].*! @standard_test(0,byte0) 177 Temp bfe_byte0_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::zero(), 178 Operand::c32(8u), Operand::c32(is_signed)); 179 writeout(0, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfe_byte0_b)); 180 181 //~gfx[^7].*! @standard_test(1,byte1) 182 Temp bfe_byte1_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(1u), 183 Operand::c32(8u), Operand::c32(is_signed)); 184 writeout(1, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfe_byte1_b)); 185 186 //~gfx[^7].*! @standard_test(2,byte2) 187 Temp bfe_byte2_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(2u), 188 Operand::c32(8u), Operand::c32(is_signed)); 189 writeout(2, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfe_byte2_b)); 190 191 //~gfx[^7].*! @standard_test(3,byte3) 192 Temp bfe_byte3_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(3u), 193 Operand::c32(8u), Operand::c32(is_signed)); 194 writeout(3, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfe_byte3_b)); 195 196 //~gfx[^7].*! @standard_test(4,word0) 197 Temp bfe_word0_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::zero(), 198 Operand::c32(16u), Operand::c32(is_signed)); 199 writeout(4, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfe_word0_b)); 200 201 //~gfx[^7].*! @standard_test(5,word1) 202 Temp bfe_word1_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(1u), 203 Operand::c32(16u), Operand::c32(is_signed)); 204 writeout(5, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfe_word1_b)); 205 206 //~gfx[^7]_unsigned! @standard_test(6,byte0) 207 Temp bfi_byte0_b = 208 bld.pseudo(ins, bld.def(v1), inputs[1], Operand::zero(), Operand::c32(8u)); 209 writeout(6, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfi_byte0_b)); 210 211 //~gfx[^7]_unsigned! @standard_test(7,word0) 212 Temp bfi_word0_b = 213 bld.pseudo(ins, bld.def(v1), inputs[1], Operand::zero(), Operand::c32(16u)); 214 writeout(7, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfi_word0_b)); 215 } 216 217 //>> p_unit_test 63 218 writeout(63); 219 220 { 221 //! v1: %tmp8 = p_insert %b, 1, 8 222 //! v1: %res8 = v_mul_f32 %a, %tmp8 223 //! p_unit_test 8, %res8 224 Temp bfi_byte1_b = 225 bld.pseudo(ins, bld.def(v1), inputs[1], Operand::c32(1u), Operand::c32(8u)); 226 writeout(8, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], bfi_byte1_b)); 227 228 /* v_cvt_f32_ubyte[0-3] can be used instead of v_cvt_f32_u32+sdwa */ 229 //~gfx7_signed! v1: %bfe_byte0_b = p_extract %b, 0, 8, 1 230 //~gfx7_signed! v1: %res9 = v_cvt_f32_u32 %bfe_byte0_b 231 //~gfx[^7]+_signed! v1: %res9 = v_cvt_f32_u32 %b dst_sel:dword src0_sel:sbyte0 232 //~gfx\d+_unsigned! v1: %res9 = v_cvt_f32_ubyte0 %b 233 //! p_unit_test 9, %res9 234 Temp bfe_byte0_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::zero(), 235 Operand::c32(8u), Operand::c32(is_signed)); 236 writeout(9, bld.vop1(aco_opcode::v_cvt_f32_u32, bld.def(v1), bfe_byte0_b)); 237 238 //~gfx7_signed! v1: %bfe_byte1_b = p_extract %b, 1, 8, 1 239 //~gfx7_signed! v1: %res10 = v_cvt_f32_u32 %bfe_byte1_b 240 //~gfx[^7]+_signed! v1: %res10 = v_cvt_f32_u32 %b dst_sel:dword src0_sel:sbyte1 241 //~gfx\d+_unsigned! v1: %res10 = v_cvt_f32_ubyte1 %b 242 //! p_unit_test 10, %res10 243 Temp bfe_byte1_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(1u), 244 Operand::c32(8u), Operand::c32(is_signed)); 245 writeout(10, bld.vop1(aco_opcode::v_cvt_f32_u32, bld.def(v1), bfe_byte1_b)); 246 247 //~gfx7_signed! v1: %bfe_byte2_b = p_extract %b, 2, 8, 1 248 //~gfx7_signed! v1: %res11 = v_cvt_f32_u32 %bfe_byte2_b 249 //~gfx[^7]+_signed! v1: %res11 = v_cvt_f32_u32 %b dst_sel:dword src0_sel:sbyte2 250 //~gfx\d+_unsigned! v1: %res11 = v_cvt_f32_ubyte2 %b 251 //! p_unit_test 11, %res11 252 Temp bfe_byte2_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(2u), 253 Operand::c32(8u), Operand::c32(is_signed)); 254 writeout(11, bld.vop1(aco_opcode::v_cvt_f32_u32, bld.def(v1), bfe_byte2_b)); 255 256 //~gfx7_signed! v1: %bfe_byte3_b = p_extract %b, 3, 8, 1 257 //~gfx7_signed! v1: %res12 = v_cvt_f32_u32 %bfe_byte3_b 258 //~gfx[^7]+_signed! v1: %res12 = v_cvt_f32_u32 %b dst_sel:dword src0_sel:sbyte3 259 //~gfx\d+_unsigned! v1: %res12 = v_cvt_f32_ubyte3 %b 260 //! p_unit_test 12, %res12 261 Temp bfe_byte3_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(3u), 262 Operand::c32(8u), Operand::c32(is_signed)); 263 writeout(12, bld.vop1(aco_opcode::v_cvt_f32_u32, bld.def(v1), bfe_byte3_b)); 264 265 /* VOP3-only instructions can't use SDWA but they can use opsel on GFX9+ instead */ 266 //~gfx(9|10).*! v1: %res13 = v_add_i16 %a, %b 267 //~gfx(9|10).*! p_unit_test 13, %res13 268 Temp bfe_word0_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::zero(), 269 Operand::c32(16u), Operand::c32(is_signed)); 270 writeout(13, bld.vop3(aco_opcode::v_add_i16, bld.def(v1), inputs[0], bfe_word0_b)); 271 272 //~gfx(9|10).*! v1: %res14 = v_add_i16 %a, hi(%b) 273 //~gfx(9|10).*! p_unit_test 14, %res14 274 Temp bfe_word1_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::c32(1u), 275 Operand::c32(16u), Operand::c32(is_signed)); 276 writeout(14, bld.vop3(aco_opcode::v_add_i16, bld.def(v1), inputs[0], bfe_word1_b)); 277 } 278 279 finish_opt_test(); 280 } 281 } 282 END_TEST 283 284 BEGIN_TEST(optimize.sdwa.extract_modifiers) 285 for (unsigned i = GFX8; i <= GFX10; i++) { 286 //>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm 287 if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i)) 288 continue; 289 290 aco_opcode ext = aco_opcode::p_extract; 291 292 //! v1: %res0 = v_mul_f32 %a, -%b dst_sel:dword src0_sel:dword src1_sel:ubyte0 293 //! p_unit_test 0, %res0 294 Temp byte0 = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::zero(), Operand::c32(8u), 295 Operand::zero()); 296 Temp neg_byte0 = fneg(byte0); 297 writeout(0, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], neg_byte0)); 298 299 //! v1: %neg = v_mul_f32 -1.0, %b 300 //! v1: %res1 = v_mul_f32 %a, %neg dst_sel:dword src0_sel:dword src1_sel:ubyte0 301 //! p_unit_test 1, %res1 302 Temp neg = fneg(inputs[1]); 303 Temp byte0_neg = 304 bld.pseudo(ext, bld.def(v1), neg, Operand::zero(), Operand::c32(8u), Operand::zero()); 305 writeout(1, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], byte0_neg)); 306 307 //! v1: %res2 = v_mul_f32 %a, |%b| dst_sel:dword src0_sel:dword src1_sel:ubyte0 308 //! p_unit_test 2, %res2 309 Temp abs_byte0 = fabs(byte0); 310 writeout(2, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], abs_byte0)); 311 312 //! v1: %abs = v_mul_f32 1.0, |%b| 313 //! v1: %res3 = v_mul_f32 %a, %abs dst_sel:dword src0_sel:dword src1_sel:ubyte0 314 //! p_unit_test 3, %res3 315 Temp abs = fabs(inputs[1]); 316 Temp byte0_abs = 317 bld.pseudo(ext, bld.def(v1), abs, Operand::zero(), Operand::c32(8u), Operand::zero()); 318 writeout(3, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], byte0_abs)); 319 320 //! v1: %res4 = v_mul_f32 %1, -|%2| dst_sel:dword src0_sel:dword src1_sel:ubyte0 321 //! p_unit_test 4, %res4 322 Temp neg_abs_byte0 = fneg(abs_byte0); 323 writeout(4, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], neg_abs_byte0)); 324 325 //! v1: %neg_abs = v_mul_f32 -1.0, |%b| 326 //! v1: %res5 = v_mul_f32 %a, %neg_abs dst_sel:dword src0_sel:dword src1_sel:ubyte0 327 //! p_unit_test 5, %res5 328 Temp neg_abs = fneg(abs); 329 Temp byte0_neg_abs = 330 bld.pseudo(ext, bld.def(v1), neg_abs, Operand::zero(), Operand::c32(8u), Operand::zero()); 331 writeout(5, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], byte0_neg_abs)); 332 333 finish_opt_test(); 334 } 335 END_TEST 336 337 BEGIN_TEST(optimize.sdwa.extract.sgpr) 338 for (unsigned i = GFX8; i <= GFX10; i++) { 339 //>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm 340 if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i)) 341 continue; 342 343 aco_opcode ext = aco_opcode::p_extract; 344 345 //~gfx8! v1: %byte0_b = p_extract %b, 0, 8, 0 346 //~gfx8! v1: %res1 = v_mul_f32 %c, %byte0_b 347 //~gfx(9|10)! v1: %res1 = v_mul_f32 %c, %b dst_sel:dword src0_sel:dword src1_sel:ubyte0 348 //! p_unit_test 1, %res1 349 Temp byte0_b = bld.pseudo(ext, bld.def(v1), inputs[1], Operand::zero(), Operand::c32(8u), 350 Operand::zero()); 351 writeout(1, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[2], byte0_b)); 352 353 //~gfx8! v1: %byte0_c = p_extract %c, 0, 8, 0 354 //~gfx8! v1: %res2 = v_mul_f32 %a, %byte0_c 355 //~gfx(9|10)! v1: %res2 = v_mul_f32 %a, %c dst_sel:dword src0_sel:dword src1_sel:ubyte0 356 //! p_unit_test 2, %res2 357 Temp byte0_c = bld.pseudo(ext, bld.def(v1), inputs[2], Operand::zero(), Operand::c32(8u), 358 Operand::zero()); 359 writeout(2, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], byte0_c)); 360 361 //~gfx8! v1: %byte0_c_2 = p_extract %c, 0, 8, 0 362 //~gfx8! v1: %res3 = v_mul_f32 %c, %byte0_c_2 363 //~gfx(9|10)! v1: %res3 = v_mul_f32 %c, %c dst_sel:dword src0_sel:dword src1_sel:ubyte0 364 //! p_unit_test 3, %res3 365 byte0_c = bld.pseudo(ext, bld.def(v1), inputs[2], Operand::zero(), Operand::c32(8u), 366 Operand::zero()); 367 writeout(3, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[2], byte0_c)); 368 369 //~gfx(8|9)! v1: %byte0_c_3 = p_extract %c, 0, 8, 0 370 //~gfx(8|9)! v1: %res4 = v_mul_f32 %d, %byte0_c_3 371 //~gfx10! v1: %res4 = v_mul_f32 %d, %c dst_sel:dword src0_sel:dword src1_sel:ubyte0 372 //! p_unit_test 4, %res4 373 byte0_c = bld.pseudo(ext, bld.def(v1), inputs[2], Operand::zero(), Operand::c32(8u), 374 Operand::zero()); 375 writeout(4, bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[3], byte0_c)); 376 377 finish_opt_test(); 378 } 379 END_TEST 380 381 BEGIN_TEST(optimize.sdwa.from_vop3) 382 for (unsigned i = GFX8; i <= GFX10; i++) { 383 //>> v1: %a, v1: %b, s1: %c, s1: %d = p_startpgm 384 if (!setup_cs("v1 v1 s1 s1", (amd_gfx_level)i)) 385 continue; 386 387 //! v1: %res0 = v_mul_f32 -|%a|, %b dst_sel:dword src0_sel:dword src1_sel:ubyte0 388 //! p_unit_test 0, %res0 389 Temp byte0_b = bld.pseudo(aco_opcode::p_extract, bld.def(v1), inputs[1], Operand::zero(), 390 Operand::c32(8u), Operand::zero()); 391 VALU_instruction* mul = 392 &bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], byte0_b)->valu(); 393 mul->neg[0] = true; 394 mul->abs[0] = true; 395 writeout(0, mul->definitions[0].getTemp()); 396 397 //~gfx8! v1: %byte0_b_0 = p_extract %b, 0, 8, 0 398 //~gfx8! v1: %res1 = v_mul_f32 %a, %byte0_b_0 *4 399 //~gfx(9|10)! v1: %res1 = v_mul_f32 %a, %b *4 dst_sel:dword src0_sel:dword src1_sel:ubyte0 400 //! p_unit_test 1, %res1 401 byte0_b = bld.pseudo(aco_opcode::p_extract, bld.def(v1), inputs[1], Operand::zero(), 402 Operand::c32(8u), Operand::zero()); 403 mul = &bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], byte0_b)->valu(); 404 mul->omod = 2; 405 writeout(1, mul->definitions[0].getTemp()); 406 407 //~gfx8! v1: %byte0_b_1 = p_extract %b, 0, 8, 0 408 //~gfx8! v1: %res2 = v_mul_f32 %byte0_b_1, %c 409 //~gfx(9|10)! v1: %res2 = v_mul_f32 %b, %c dst_sel:dword src0_sel:ubyte0 src1_sel:dword 410 //! p_unit_test 2, %res2 411 byte0_b = bld.pseudo(aco_opcode::p_extract, bld.def(v1), inputs[1], Operand::zero(), 412 Operand::c32(8u), Operand::zero()); 413 writeout(2, bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), byte0_b, inputs[2])); 414 415 if (i >= GFX10) { 416 //~gfx10! v1: %byte0_b_2 = p_extract %b, 0, 8, 0 417 //~gfx10! v1: %res3 = v_mul_f32 %byte0_b_2, 0x1234 418 //~gfx10! p_unit_test 3, %res3 419 byte0_b = bld.pseudo(aco_opcode::p_extract, bld.def(v1), inputs[1], Operand::zero(), 420 Operand::c32(8u), Operand::zero()); 421 writeout(3, 422 bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), byte0_b, Operand::c32(0x1234u))); 423 } 424 425 finish_opt_test(); 426 } 427 END_TEST 428 429 BEGIN_TEST(optimize.sdwa.insert) 430 for (unsigned i = GFX7; i <= GFX10; i++) { 431 //>> v1: %a, v1: %b = p_startpgm 432 if (!setup_cs("v1 v1", (amd_gfx_level)i)) 433 continue; 434 435 aco_opcode ext = aco_opcode::p_extract; 436 aco_opcode ins = aco_opcode::p_insert; 437 438 //~gfx[^7]! v1: %res0 = v_mul_f32 %a, %b dst_sel:ubyte0 src0_sel:dword src1_sel:dword 439 //~gfx[^7]! p_unit_test 0, %res0 440 Temp val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]); 441 writeout(0, bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(8u))); 442 443 //~gfx[^7]! v1: %res1 = v_mul_f32 %a, %b dst_sel:ubyte1 src0_sel:dword src1_sel:dword 444 //~gfx[^7]! p_unit_test 1, %res1 445 val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]); 446 writeout(1, bld.pseudo(ins, bld.def(v1), val, Operand::c32(1u), Operand::c32(8u))); 447 448 //~gfx[^7]! v1: %res2 = v_mul_f32 %a, %b dst_sel:ubyte2 src0_sel:dword src1_sel:dword 449 //~gfx[^7]! p_unit_test 2, %res2 450 val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]); 451 writeout(2, bld.pseudo(ins, bld.def(v1), val, Operand::c32(2u), Operand::c32(8u))); 452 453 //~gfx[^7]! v1: %res3 = v_mul_f32 %a, %b dst_sel:ubyte3 src0_sel:dword src1_sel:dword 454 //~gfx[^7]! p_unit_test 3, %res3 455 val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]); 456 writeout(3, bld.pseudo(ins, bld.def(v1), val, Operand::c32(3u), Operand::c32(8u))); 457 458 //~gfx[^7]! v1: %res4 = v_mul_f32 %a, %b dst_sel:uword0 src0_sel:dword src1_sel:dword 459 //~gfx[^7]! p_unit_test 4, %res4 460 val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]); 461 writeout(4, bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(16u))); 462 463 //~gfx[^7]! v1: %res5 = v_mul_f32 %a, %b dst_sel:uword1 src0_sel:dword src1_sel:dword 464 //~gfx[^7]! p_unit_test 5, %res5 465 val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]); 466 writeout(5, bld.pseudo(ins, bld.def(v1), val, Operand::c32(1u), Operand::c32(16u))); 467 468 //~gfx[^7]! v1: %res6 = v_mul_f32 %a, %b dst_sel:ubyte0 src0_sel:dword src1_sel:dword 469 //~gfx[^7]! p_unit_test 6, %res6 470 val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]); 471 writeout( 472 6, bld.pseudo(ext, bld.def(v1), val, Operand::zero(), Operand::c32(8u), Operand::zero())); 473 474 //~gfx[^7]! v1: %res7 = v_mul_f32 %a, %b dst_sel:uword0 src0_sel:dword src1_sel:dword 475 //~gfx[^7]! p_unit_test 7, %res7 476 val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]); 477 writeout( 478 7, bld.pseudo(ext, bld.def(v1), val, Operand::zero(), Operand::c32(16u), Operand::zero())); 479 480 //~gfx[^7]! v1: %tmp8 = v_mul_f32 %a, %b 481 //~gfx[^7]! v1: %res8 = p_extract %tmp8, 2, 8, 0 482 //~gfx[^7]! p_unit_test 8, %res8 483 val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]); 484 writeout( 485 8, bld.pseudo(ext, bld.def(v1), val, Operand::c32(2u), Operand::c32(8u), Operand::zero())); 486 487 //~gfx[^7]! v1: %tmp9 = v_mul_f32 %a, %b 488 //~gfx[^7]! v1: %res9 = p_extract %tmp9, 0, 8, 1 489 //~gfx[^7]! p_unit_test 9, %res9 490 val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]); 491 writeout( 492 9, bld.pseudo(ext, bld.def(v1), val, Operand::zero(), Operand::c32(8u), Operand::c32(1u))); 493 494 //>> p_unit_test 63 495 writeout(63); 496 497 //! v1: %res10 = v_mul_f32 %a, %b 498 //! p_unit_test 10, %res10 499 val = bld.vop2(aco_opcode::v_mul_f32, bld.def(v1), inputs[0], inputs[1]); 500 bld.pseudo(ins, bld.def(v1), val, Operand::c32(1u), Operand::c32(16u)); 501 writeout(10, val); 502 503 //~gfx[^7]! v1: %tmp11 = v_sub_i16 %a, %b 504 //~gfx[^7]! v1: %res11 = p_insert %tmp11, 0, 16 505 //~gfx[^7]! p_unit_test 11, %res11 506 val = bld.vop3(aco_opcode::v_sub_i16, bld.def(v1), inputs[0], inputs[1]); 507 writeout(11, bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(16u))); 508 509 //~gfx[^7]! v1: %tmp12 = v_sub_i16 %a, %b 510 //~gfx[^7]! v1: %res12 = p_insert %tmp12, 1, 16 511 //~gfx[^7]! p_unit_test 12, %res12 512 val = bld.vop3(aco_opcode::v_sub_i16, bld.def(v1), inputs[0], inputs[1]); 513 writeout(12, bld.pseudo(ins, bld.def(v1), val, Operand::c32(1u), Operand::c32(16u))); 514 515 //~gfx[^7]! v1: %tmp13 = v_sub_i16 %a, %b 516 //~gfx[^7]! v1: %res13 = p_insert %tmp13, 0, 8 517 //~gfx[^7]! p_unit_test 13, %res13 518 val = bld.vop3(aco_opcode::v_sub_i16, bld.def(v1), inputs[0], inputs[1]); 519 writeout(13, bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(8u))); 520 521 finish_opt_test(); 522 } 523 END_TEST 524 525 BEGIN_TEST(optimize.sdwa.insert_modifiers) 526 for (unsigned i = GFX8; i <= GFX9; i++) { 527 //>> v1: %a = p_startpgm 528 if (!setup_cs("v1", (amd_gfx_level)i)) 529 continue; 530 531 aco_opcode ins = aco_opcode::p_insert; 532 533 //~gfx8! v1: %tmp0 = v_rcp_f32 %a *2 534 //~gfx8! v1: %res0 = p_insert %tmp0, 0, 8 535 //~gfx9! v1: %res0 = v_rcp_f32 %a *2 dst_sel:ubyte0 src0_sel:dword 536 //! p_unit_test 0, %res0 537 Temp val = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), inputs[0]); 538 val = bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), val, Operand::c32(0x40000000u)); 539 writeout(0, bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(8u))); 540 541 //! v1: %res1 = v_rcp_f32 %a clamp dst_sel:ubyte0 src0_sel:dword 542 //! p_unit_test 1, %res1 543 val = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), inputs[0]); 544 val = bld.vop3(aco_opcode::v_med3_f32, bld.def(v1), val, Operand::zero(), 545 Operand::c32(0x3f800000u)); 546 writeout(1, bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(8u))); 547 548 //! v1: %tmp2 = v_rcp_f32 %a dst_sel:ubyte0 src0_sel:dword 549 //! v1: %res2 = v_mul_f32 %tmp2, 2.0 550 //! p_unit_test 2, %res2 551 val = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), inputs[0]); 552 val = bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(8u)); 553 val = bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), val, Operand::c32(0x40000000u)); 554 writeout(2, val); 555 556 //! v1: %tmp3 = v_rcp_f32 %a dst_sel:ubyte0 src0_sel:dword 557 //! v1: %res3 = v_add_f32 %tmp3, 0 clamp 558 //! p_unit_test 3, %res3 559 val = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), inputs[0]); 560 val = bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(8u)); 561 val = bld.vop3(aco_opcode::v_med3_f32, bld.def(v1), val, Operand::zero(), 562 Operand::c32(0x3f800000u)); 563 writeout(3, val); 564 565 //~gfx8! v1: %tmp4 = v_rcp_f32 %a *2 clamp 566 //~gfx8! v1: %res4 = p_insert %tmp4, 0, 8 567 //~gfx9! v1: %res4 = v_rcp_f32 %a *2 clamp dst_sel:ubyte0 src0_sel:dword 568 //! p_unit_test 4, %res4 569 val = bld.vop1(aco_opcode::v_rcp_f32, bld.def(v1), inputs[0]); 570 val = bld.vop2_e64(aco_opcode::v_mul_f32, bld.def(v1), val, Operand::c32(0x40000000u)); 571 val = bld.vop3(aco_opcode::v_med3_f32, bld.def(v1), val, Operand::zero(), 572 Operand::c32(0x3f800000u)); 573 writeout(4, bld.pseudo(ins, bld.def(v1), val, Operand::zero(), Operand::c32(8u))); 574 575 finish_opt_test(); 576 } 577 END_TEST 578