1 /*!
2 * \file trc_mem_acc_cache.cpp
3 * \brief OpenCSD : Memory accessor cache.
4 *
5 * \copyright Copyright (c) 2018, ARM Limited. All Rights Reserved.
6 */
7
8 /*
9 * Redistribution and use in source and binary forms, with or without modification,
10 * are permitted provided that the following conditions are met:
11 *
12 * 1. Redistributions of source code must retain the above copyright notice,
13 * this list of conditions and the following disclaimer.
14 *
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 *
19 * 3. Neither the name of the copyright holder nor the names of its contributors
20 * may be used to endorse or promote products derived from this software without
21 * specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35 #include <cstring>
36 #include <sstream>
37 #include <iomanip>
38 #include "mem_acc/trc_mem_acc_cache.h"
39 #include "mem_acc/trc_mem_acc_base.h"
40 #include "interfaces/trc_error_log_i.h"
41
42 #ifdef LOG_CACHE_STATS
43 #define INC_HITS_RL(idx) m_hits++; m_hit_rl[m_mru_idx]++;
44 #define INC_MISS() m_misses++;
45 #define INC_PAGES() m_pages++;
46 #define SET_MAX_RL(idx) \
47 { \
48 if (m_hit_rl_max[idx] < m_hit_rl[idx]) \
49 m_hit_rl_max[idx] = m_hit_rl[idx]; \
50 m_hit_rl[idx] = 0; \
51 }
52 #define INC_RL(idx) m_hit_rl[m_mru_idx]++;
53 #else
54 #define INC_HITS_RL(idx)
55 #define INC_MISS()
56 #define INC_PAGES()
57 #define SET_MAX_RL(idx)
58 #define INC_RL(idx)
59 #endif
60
61 // uncomment to log cache ops
62 // #define LOG_CACHE_OPS
63
createCaches()64 ocsd_err_t TrcMemAccCache::createCaches()
65 {
66 if (m_mru)
67 destroyCaches();
68 m_mru = (cache_block_t*) new (std::nothrow) cache_block_t[m_mru_num_pages];
69 if (!m_mru)
70 return OCSD_ERR_MEM;
71 for (int i = 0; i < m_mru_num_pages; i++) {
72 m_mru[i].data = new (std::nothrow) uint8_t[m_mru_page_size];
73 if (!m_mru[i].data)
74 return OCSD_ERR_MEM;
75 clearPage(&m_mru[i]);
76 }
77 #ifdef LOG_CACHE_STATS
78 m_hit_rl = (uint32_t *) new (std::nothrow) uint32_t[m_mru_num_pages];
79 m_hit_rl_max = (uint32_t*) new (std::nothrow) uint32_t[m_mru_num_pages];
80 if (!m_hit_rl || !m_hit_rl_max)
81 return OCSD_ERR_MEM;
82 for (int j = 0; j < m_mru_num_pages; j++) {
83 m_hit_rl[j] = 0;
84 m_hit_rl_max[j] = 0;
85 }
86 #endif
87
88 return OCSD_OK;
89 }
90
destroyCaches()91 void TrcMemAccCache::destroyCaches()
92 {
93 if (m_mru) {
94 for (int i = 0; i < m_mru_num_pages; i++)
95 delete[] m_mru[i].data;
96 delete[] m_mru;
97 m_mru = 0;
98 }
99 #ifdef LOG_CACHE_STATS
100 if (m_hit_rl)
101 delete[] m_hit_rl;
102 if (m_hit_rl_max)
103 delete[] m_hit_rl_max;
104 m_hit_rl = 0;
105 m_hit_rl_max = 0;
106 #endif
107
108 }
109
getenvMemaccCacheSizes(bool & enable,int & page_size,int & num_pages)110 void TrcMemAccCache::getenvMemaccCacheSizes(bool& enable, int& page_size, int& num_pages)
111 {
112 char* env_var;
113 long env_val;
114
115 /* set defaults */
116 enable = true;
117 page_size = MEM_ACC_CACHE_DEFAULT_PAGE_SIZE;
118 num_pages = MEM_ACC_CACHE_DEFAULT_MRU_SIZE;
119
120 /* check environment for adjustments */
121
122 /* override the default on switch? if so no need to look further */
123 if ((env_var = getenv(OCSD_ENV_MEMACC_CACHE_OFF)) != NULL)
124 {
125 enable = false;
126 return;
127 }
128
129 /* check for tweak in page size */
130 if ((env_var = getenv(OCSD_ENV_MEMACC_CACHE_PG_SIZE)) != NULL)
131 {
132 env_val = strtol(env_var, NULL, 0);
133 /*
134 * if no valid conversion then env_val = 0,
135 * otherwise set val and allow TrcMemAccCache::setCacheSizes
136 * fn to ensure the value in bounds
137 */
138 if (env_val > 0)
139 page_size = (int)env_val;
140 }
141
142 /* check for tweak in number of pages */
143 if ((env_var = getenv(OCSD_ENV_MEMACC_CACHE_PG_NUM)) != NULL)
144 {
145 env_val = strtol(env_var, NULL, 0);
146 /*
147 * if no valid conversion then env_val = 0,
148 * otherwise set val and allow TrcMemAccCache::setCacheSizes
149 * fn to ensure the value in bounds
150 */
151 if (env_val > 0)
152 num_pages = (int)env_val;
153 }
154
155 }
156
enableCaching(bool bEnable)157 ocsd_err_t TrcMemAccCache::enableCaching(bool bEnable)
158 {
159 ocsd_err_t err = OCSD_OK;
160
161 if (bEnable)
162 err = createCaches();
163 else
164 destroyCaches();
165 m_bCacheEnabled = bEnable;
166
167 return err;
168 }
169
setCacheSizes(const uint16_t page_size,const int nr_pages)170 ocsd_err_t TrcMemAccCache::setCacheSizes(const uint16_t page_size, const int nr_pages)
171 {
172 /* remove any caches with the existing sizes */
173 destroyCaches();
174
175 /* set page size within Max/Min range */
176 if (page_size > MEM_ACC_CACHE_PAGE_SIZE_MAX)
177 m_mru_page_size = MEM_ACC_CACHE_PAGE_SIZE_MAX;
178 else if (page_size < MEM_ACC_CACHE_PAGE_SIZE_MIN)
179 m_mru_page_size = MEM_ACC_CACHE_PAGE_SIZE_MIN;
180 else
181 m_mru_page_size = page_size;
182
183 /* set num pages within max/min range */
184 if (nr_pages > MEM_ACC_CACHE_MRU_SIZE_MAX)
185 m_mru_num_pages = MEM_ACC_CACHE_MRU_SIZE_MAX;
186 else if (nr_pages < MEM_ACC_CACHE_MRU_SIZE_MIN)
187 m_mru_num_pages = MEM_ACC_CACHE_MRU_SIZE_MIN;
188 else
189 m_mru_num_pages = nr_pages;
190
191 /* re-create with new sizes */
192 return createCaches();
193 }
194
195 /* return index of unused page, or oldest used page by sequence number */
findNewPage()196 int TrcMemAccCache::findNewPage()
197 {
198 uint32_t oldest_seq;
199 int current_idx, oldest_idx;
200 #ifdef LOG_CACHE_OPS
201 std::ostringstream oss;
202 #endif
203
204 /* set up search indexes and check the current search index has not wrapped. */
205 current_idx = m_mru_idx + 1;
206 oldest_idx = m_mru_idx;
207 oldest_seq = 0;
208 if (current_idx >= m_mru_num_pages)
209 current_idx = 0;
210
211 /* search forwards from m_mru_idx + 1 until we wrap and hit the index again */
212 while (current_idx != m_mru_idx) {
213 if (m_mru[current_idx].use_sequence == 0) {
214 #ifdef LOG_CACHE_OPS
215 oss << "TrcMemAccCache:: ALI-allocate clean page: [page: " << std::dec << current_idx << "]\n";
216 logMsg(oss.str());
217 #endif
218 return current_idx;
219 }
220
221 // if we find a page with a lower use sequence, that is older.
222 if ((oldest_seq == 0) || (oldest_seq > m_mru[current_idx].use_sequence)) {
223 oldest_seq = m_mru[current_idx].use_sequence;
224 oldest_idx = current_idx;
225 }
226
227 current_idx++;
228
229 // wrap around?
230 if (current_idx >= m_mru_num_pages)
231 current_idx = 0;
232 }
233 #ifdef LOG_CACHE_OPS
234 oss << "TrcMemAccCache:: ALI-evict and allocate old page: [page: " << std::dec << oldest_idx << "]\n";
235 logMsg(oss.str());
236 #endif
237 return oldest_idx;
238 }
239
incSequence()240 void TrcMemAccCache::incSequence()
241 {
242 m_mru[m_mru_idx].use_sequence = m_mru_sequence++;
243 if (m_mru_sequence == 0) {
244 // wrapped which throws out the oldest algorithm - oldest will now appear newer - so not evicted.
245 // arbitrarily re-sequence all in use..
246 m_mru_sequence = 1;
247 for (int i = 0; i < m_mru_num_pages; i++)
248 if (m_mru[i].use_sequence != 0)
249 m_mru[i].use_sequence = m_mru_sequence++;
250
251 // ensure newest still newest...
252 m_mru[m_mru_idx].use_sequence = m_mru_sequence++;
253 }
254 }
255
readBytesFromCache(TrcMemAccessorBase * p_accessor,const ocsd_vaddr_t address,const ocsd_mem_space_acc_t mem_space,const uint8_t trcID,uint32_t * numBytes,uint8_t * byteBuffer)256 ocsd_err_t TrcMemAccCache::readBytesFromCache(TrcMemAccessorBase *p_accessor, const ocsd_vaddr_t address, const ocsd_mem_space_acc_t mem_space, const uint8_t trcID, uint32_t *numBytes, uint8_t *byteBuffer)
257 {
258 uint32_t bytesRead = 0, reqBytes = *numBytes;
259 ocsd_err_t err = OCSD_OK;
260
261
262 #ifdef LOG_CACHE_OPS
263 std::ostringstream oss;
264 std::string memSpaceStr;
265 #endif
266
267 if (m_bCacheEnabled)
268 {
269 if (blockInCache(address, reqBytes, trcID))
270 {
271 bytesRead = reqBytes;
272 memcpy(byteBuffer, &m_mru[m_mru_idx].data[address - m_mru[m_mru_idx].st_addr], reqBytes);
273 incSequence();
274 #ifdef LOG_CACHE_OPS
275 oss << "TrcMemAccCache:: hit {page: " << std::dec << m_mru_idx << "; seq: " << m_mru[m_mru_idx].use_sequence << " CSID: " << std::hex << (int)m_mru[m_mru_idx].trcID;
276 oss << "} [addr:0x" << std::hex << address << ", bytes: " << std::dec << reqBytes << "]\n";
277 logMsg(oss.str());
278 #endif
279 INC_HITS_RL(m_mru_idx);
280 }
281 else
282 {
283 #ifdef LOG_CACHE_OPS
284 oss << "TrcMemAccCache:: miss [addr:0x" << std::hex << address << ", bytes: " << std::dec << reqBytes << "]\n";
285 logMsg(oss.str());
286 #endif
287 /* need a new cache page - check the underlying accessor for the data */
288 m_mru_idx = findNewPage();
289 m_mru[m_mru_idx].valid_len = p_accessor->readBytes(address, mem_space, trcID, m_mru_page_size, &m_mru[m_mru_idx].data[0]);
290
291 /* check return length valid - v bad if return length more than request */
292 if (m_mru[m_mru_idx].valid_len > m_mru_page_size)
293 {
294 m_mru[m_mru_idx].valid_len = 0; // set to nothing returned.
295 err = OCSD_ERR_MEM_ACC_BAD_LEN;
296 }
297
298 if (m_mru[m_mru_idx].valid_len > 0)
299 {
300 // got some data - so save the details
301 m_mru[m_mru_idx].st_addr = address;
302 m_mru[m_mru_idx].trcID = trcID;
303 incSequence();
304
305 // log the run length hit counts
306 SET_MAX_RL(m_mru_idx);
307
308 #ifdef LOG_CACHE_OPS
309 TrcMemAccessorBase::getMemAccSpaceString(memSpaceStr, mem_space);
310 oss.str("");
311 oss << "TrcMemAccCache:: ALI-load {page: " << std::dec << m_mru_idx << "; seq: " << m_mru[m_mru_idx].use_sequence << " CSID: " << std::hex << (int)m_mru[m_mru_idx].trcID;
312 oss << "} [mem space: " << memSpaceStr << ", addr:0x" << std::hex << address << ", bytes: " << std::dec << m_mru[m_mru_idx].valid_len << "]\n";
313 logMsg(oss.str());
314 #endif
315 INC_PAGES();
316
317 if (blockInPage(address, reqBytes, trcID)) /* check we got the data we needed */
318 {
319 bytesRead = reqBytes;
320 memcpy(byteBuffer, &m_mru[m_mru_idx].data[address - m_mru[m_mru_idx].st_addr], reqBytes);
321 INC_RL(m_mru_idx);
322 }
323 else
324 {
325 #ifdef LOG_CACHE_OPS
326 oss.str("");
327 oss << "TrcMemAccCache:: miss-after-load {page: " << std::dec << m_mru_idx << " } [addr:0x" << std::hex << address << ", bytes: " << std::dec << m_mru[m_mru_idx].valid_len << "]\n";
328 logMsg(oss.str());
329 #endif
330 INC_MISS();
331 }
332 }
333 }
334 }
335 *numBytes = bytesRead;
336 return err;
337 }
338
invalidateAll()339 void TrcMemAccCache::invalidateAll()
340 {
341 #ifdef LOG_CACHE_OPS
342 std::ostringstream oss;
343 oss << "TrcMemAccCache:: ALI-invalidate All\n";
344 logMsg(oss.str());
345 #endif
346
347 for (int i = 0; i < m_mru_num_pages; i++)
348 clearPage(&m_mru[i]);
349 m_mru_idx = 0;
350 }
351
invalidateByTraceID(int8_t trcID)352 void TrcMemAccCache::invalidateByTraceID(int8_t trcID)
353 {
354 #ifdef LOG_CACHE_OPS
355 std::ostringstream oss;
356 oss << "TrcMemAccCache:: ALI-invalidate by ID request {CSID: " << std::hex << (int)trcID << "}\n";
357 logMsg(oss.str());
358 #endif
359
360 for (int i = 0; i < m_mru_num_pages; i++)
361 {
362 if (m_mru[i].trcID == trcID)
363 {
364 #ifdef LOG_CACHE_OPS
365 oss.str("");
366 oss << "TrcMemAccCache:: ALI-invalidate page {page: " << std::dec << i << "; seq: " << m_mru[i].use_sequence << " CSID: " << std::hex << (int)m_mru[i].trcID;
367 oss << "} [addr:0x" << std::hex << m_mru[i].st_addr << ", bytes: " << std::dec << m_mru[i].valid_len << "]\n";
368 logMsg(oss.str());
369 #endif
370 clearPage(&m_mru[i]);
371 }
372 }
373 }
374
logMsg(const std::string & szMsg)375 void TrcMemAccCache::logMsg(const std::string &szMsg)
376 {
377 if (m_err_log)
378 m_err_log->LogMessage(ITraceErrorLog::HANDLE_GEN_INFO, OCSD_ERR_SEV_INFO, szMsg);
379 }
380
setErrorLog(ITraceErrorLog * log)381 void TrcMemAccCache::setErrorLog(ITraceErrorLog *log)
382 {
383 m_err_log = log;
384 }
385
logAndClearCounts()386 void TrcMemAccCache::logAndClearCounts()
387 {
388 #ifdef LOG_CACHE_STATS
389 std::ostringstream oss;
390
391 oss << "TrcMemAccCache:: cache performance: Page Size: 0x" << std::hex << m_mru_page_size << "; Number of Pages: " << std::dec << m_mru_num_pages << "\n";
392 oss << "Cache hits(" << std::dec << m_hits << "), misses(" << m_misses << "), new pages(" << m_pages << ")\n";
393 logMsg(oss.str());
394 for (int i = 0; i < m_mru_num_pages; i++)
395 {
396 if (m_hit_rl_max[i] < m_hit_rl[i])
397 m_hit_rl_max[i] = m_hit_rl[i];
398 oss.str("");
399 oss << "Run length max page " << std::dec << i << ": " << m_hit_rl_max[i] << "\n";
400 logMsg(oss.str());
401 }
402 m_hits = m_misses = m_pages = 0;
403 #endif
404 }
405
406 /* End of File trc_mem_acc_cache.cpp */
407