1 /* Copyright 2022 Advanced Micro Devices, Inc. 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 * OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: AMD 22 * 23 */ 24 #pragma once 25 26 #ifdef __cplusplus 27 extern "C" { 28 #endif 29 30 /**************** 31 * VPE OP Codes 32 ****************/ 33 enum VPE_CMD_OPCODE { 34 VPE_CMD_OPCODE_NOP = 0x0, 35 VPE_CMD_OPCODE_VPE_DESC = 0x1, 36 VPE_CMD_OPCODE_PLANE_CFG = 0x2, 37 VPE_CMD_OPCODE_VPEP_CFG = 0x3, 38 VPE_CMD_OPCODE_FENCE = 0x5, 39 VPE_CMD_OPCODE_TRAP = 0x6, 40 VPE_CMD_OPCODE_REG_WRITE = 0x7, 41 VPE_CMD_OPCODE_POLL_REGMEM = 0x8, 42 VPE_CMD_OPCODE_ATOMIC = 0xA, 43 VPE_CMD_OPCODE_PLANE_FILL = 0xB, 44 VPE_CMD_OPCODE_TIMESTAMP = 0xD 45 }; 46 47 /** Generic Command Header 48 * Generic Commands include: 49 * Noop, Fence, Trap, 50 * RegisterWrite, PollRegisterWriteMemory, 51 * SetLocalTimestamp, GetLocalTimestamp 52 * GetGlobalGPUTimestamp */ 53 #define VPE_HEADER_SUB_OPCODE__SHIFT 8 54 #define VPE_HEADER_SUB_OPCODE_MASK 0x0000FF00 55 #define VPE_HEADER_OPCODE__SHIFT 0 56 #define VPE_HEADER_OPCODE_MASK 0x000000FF 57 58 #define VPE_CMD_HEADER(op, subop) \ 59 (((subop << VPE_HEADER_SUB_OPCODE__SHIFT) & VPE_HEADER_SUB_OPCODE_MASK) | \ 60 ((op << VPE_HEADER_OPCODE__SHIFT) & VPE_HEADER_OPCODE_MASK)) 61 62 /*************************** 63 * VPE Descriptor 64 ***************************/ 65 #define VPE_DESC_CD__SHIFT 16 66 #define VPE_DESC_CD_MASK 0x000F0000 67 68 #define VPE_DESC_ADDR__SHIFT 32 69 #define VPE_DESC_HIGH_ADDR_MASK 0xFFFFFFFF00000000 70 /* The lowest bits are reuse and tmz as bit 1 and bit 0. 71 Smibs will substract the address with emb gpuva to 72 get offset and then reuse bit will be preserved 73 So as long as the embedded buffer is allocated 74 at correct alignment (currently low addr is [31:2] 75 which means we need a 4 byte(2 bit) alignment), 76 the offset generated will still cover the 77 reuse bit as part of it. 78 Ex : Address : 0x200036 GPU Virtual Address : 0x200000 79 offset is 0x36 which keeps the reuse bit */ 80 #define VPE_DESC_LOW_ADDR_MASK 0x00000000FFFFFFFF 81 #define VPE_DESC_REUSE_TMZ_MASK 0x0000000000000003 82 83 #define VPE_DESC_NUM_CONFIG_DESCRIPTOR__SHIFT 0 84 #define VPE_DESC_NUM_CONFIG_DESCRIPTOR_MASK 0x000000FF 85 86 #define VPE_DESC_REUSE__MASK 0x00000002 87 88 #define VPE_DESC_CMD_HEADER(cd) \ 89 (VPE_CMD_HEADER(VPE_CMD_OPCODE_VPE_DESC, 0) | (((cd) << VPE_DESC_CD__SHIFT) & VPE_DESC_CD_MASK)) 90 91 /*************************** 92 * VPE Plane Config 93 ***************************/ 94 enum VPE_PLANE_CFG_SUBOP { 95 VPE_PLANE_CFG_SUBOP_1_TO_1 = 0x0, 96 VPE_PLANE_CFG_SUBOP_2_TO_1 = 0x1, 97 VPE_PLANE_CFG_SUBOP_2_TO_2 = 0x2 98 }; 99 100 #define VPE_PLANE_CFG_ONE_PLANE 0 101 #define VPE_PLANE_CFG_TWO_PLANES 1 102 103 #define VPE_PLANE_CFG_NPS0__SHIFT 16 104 #define VPE_PLANE_CFG_NPS0_MASK 0x00030000 105 106 #define VPE_PLANE_CFG_NPD0__SHIFT 18 107 #define VPE_PLANE_CFG_NPD0_MASK 0x000C0000 108 109 #define VPE_PLANE_CFG_NPS1__SHIFT 20 110 #define VPE_PLANE_CFG_NPS1_MASK 0x00300000 111 112 #define VPE_PLANE_CFG_NPD1__SHIFT 22 113 #define VPE_PLANE_CFG_NPD1_MASK 0x00C00000 114 115 #define VPE_PLANE_CFG_TMZ__SHIFT 16 116 #define VPE_PLANE_CFG_TMZ_MASK 0x00010000 117 118 #define VPE_PLANE_CFG_SWIZZLE_MODE__SHIFT 3 119 #define VPE_PLANE_CFG_SWIZZLE_MODE_MASK 0x000000F8 120 121 #define VPE_PLANE_CFG_ROTATION__SHIFT 0 122 #define VPE_PLANE_CFG_ROTATION_MASK 0x00000003 123 124 #define VPE_PLANE_CFG_MIRROR__SHIFT 0 125 #define VPE_PLANE_CFG_MIRROR_MASK 0x00000003 126 127 #define VPE_PLANE_ADDR_LO__SHIFT 0 128 #define VPE_PLANE_ADDR_LO_MASK 0xFFFFFF00 129 130 #define VPE_PLANE_CFG_PITCH__SHIFT 0 131 #define VPE_PLANE_CFG_PITCH_MASK 0x00003FFF 132 133 #define VPE_PLANE_CFG_VIEWPORT_Y__SHIFT 16 134 #define VPE_PLANE_CFG_VIEWPORT_Y_MASK 0x3FFF0000 135 #define VPE_PLANE_CFG_VIEWPORT_X__SHIFT 0 136 #define VPE_PLANE_CFG_VIEWPORT_X_MASK 0x00003FFF 137 138 #define VPE_PLANE_CFG_VIEWPORT_HEIGHT__SHIFT 16 139 #define VPE_PLANE_CFG_VIEWPORT_HEIGHT_MASK 0x1FFF0000 140 #define VPE_PLANE_CFG_VIEWPORT_ELEMENT_SIZE__SHIFT 13 141 #define VPE_PLANE_CFG_VIEWPORT_ELEMENT_SIZE_MASK 0x0000E000 142 #define VPE_PLANE_CFG_VIEWPORT_WIDTH__SHIFT 0 143 #define VPE_PLANE_CFG_VIEWPORT_WIDTH_MASK 0x00001FFF 144 145 enum VPE_PLANE_CFG_ELEMENT_SIZE { 146 VPE_PLANE_CFG_ELEMENT_SIZE_8BPE = 0, 147 VPE_PLANE_CFG_ELEMENT_SIZE_16BPE = 1, 148 VPE_PLANE_CFG_ELEMENT_SIZE_32BPE = 2, 149 VPE_PLANE_CFG_ELEMENT_SIZE_64BPE = 3 150 }; 151 152 #define VPE_PLANE_CFG_CMD_HEADER(subop, nps0, npd0, nps1, npd1) \ 153 (VPE_CMD_HEADER(VPE_CMD_OPCODE_PLANE_CFG, subop) | \ 154 (((nps0) << VPE_PLANE_CFG_NPS0__SHIFT) & VPE_PLANE_CFG_NPS0_MASK) | \ 155 (((npd0) << VPE_PLANE_CFG_NPD0__SHIFT) & VPE_PLANE_CFG_NPD0_MASK) | \ 156 (((nps1) << VPE_PLANE_CFG_NPS1__SHIFT) & VPE_PLANE_CFG_NPS1_MASK) | \ 157 (((npd0) << VPE_PLANE_CFG_NPD1__SHIFT) & VPE_PLANE_CFG_NPD1_MASK)) 158 159 /************************ 160 * VPEP Config 161 ************************/ 162 enum VPE_VPEP_CFG_SUBOP { 163 VPE_VPEP_CFG_SUBOP_DIR_CFG = 0x0, 164 VPE_VPEP_CFG_SUBOP_IND_CFG = 0x1 165 }; 166 167 // Direct Config Command Header 168 #define VPE_DIR_CFG_HEADER_ARRAY_SIZE__SHIFT 16 169 #define VPE_DIR_CFG_HEADER_ARRAY_SIZE_MASK 0xFFFF0000 170 171 #define VPE_DIR_CFG_CMD_HEADER(arr_sz) \ 172 (VPE_CMD_HEADER(VPE_CMD_OPCODE_VPEP_CFG, VPE_VPEP_CFG_SUBOP_DIR_CFG) | \ 173 (((arr_sz) << VPE_DIR_CFG_HEADER_ARRAY_SIZE__SHIFT) & VPE_DIR_CFG_HEADER_ARRAY_SIZE_MASK)) 174 175 #define VPE_DIR_CFG_PKT_REGISTER_OFFSET__SHIFT 2 176 #define VPE_DIR_CFG_PKT_REGISTER_OFFSET_MASK 0x000FFFFC 177 178 #define VPE_DIR_CFG_PKT_DATA_SIZE__SHIFT 20 179 #define VPE_DIR_CFG_PKT_DATA_SIZE_MASK 0xFFF00000 180 181 // InDirect Config Command Header 182 #define VPE_IND_CFG_HEADER_NUM_DST__SHIFT 28 183 #define VPE_IND_CFG_HEADER_NUM_DST_MASK 0xF0000000 184 185 #define VPE_IND_CFG_CMD_HEADER(num_dst) \ 186 (VPE_CMD_HEADER(VPE_CMD_OPCODE_VPEP_CFG, VPE_VPEP_CFG_SUBOP_IND_CFG) | \ 187 ((((uint32_t)num_dst) << VPE_IND_CFG_HEADER_NUM_DST__SHIFT) & \ 188 VPE_IND_CFG_HEADER_NUM_DST_MASK)) 189 190 #define VPE_IND_CFG_DATA_ARRAY_SIZE__SHIFT 0 191 #define VPE_IND_CFG_DATA_ARRAY_SIZE_MASK 0x0007FFFF 192 193 #define VPE_IND_CFG_PKT_REGISTER_OFFSET__SHIFT 2 194 #define VPE_IND_CFG_PKT_REGISTER_OFFSET_MASK 0x000FFFFC 195 196 /************************** 197 * Poll Reg/Mem Sub-OpCode 198 **************************/ 199 enum VPE_POLL_REGMEM_SUBOP { 200 VPE_POLL_REGMEM_SUBOP_REGMEM = 0x0, 201 VPE_POLL_REGMEM_SUBOP_REGMEM_WRITE = 0x1 202 }; 203 204 #ifdef __cplusplus 205 } 206 #endif 207