1 /* Copyright 2022 Advanced Micro Devices, Inc. 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 * OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: AMD 22 * 23 */ 24 25 #pragma once 26 27 #include <stdbool.h> 28 #include <stdint.h> 29 #include <stddef.h> 30 #include <limits.h> 31 #include "vpe_hw_types.h" 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 struct vpe; 38 39 #define MAX_NB_POLYPHASE_COEFFS \ 40 (8 * 33) /* currently vpe supports up to 8 taps and 64 phases, only (32+1) phases needed*/ 41 42 enum vpe_status { 43 VPE_STATUS_OK = 1, 44 VPE_STATUS_ERROR, 45 VPE_STATUS_NO_MEMORY, 46 47 // errors for not supported operations 48 VPE_STATUS_NOT_SUPPORTED, 49 VPE_STATUS_DCC_NOT_SUPPORTED, 50 VPE_STATUS_SWIZZLE_NOT_SUPPORTED, 51 VPE_STATUS_NUM_STREAM_NOT_SUPPORTED, 52 VPE_STATUS_PIXEL_FORMAT_NOT_SUPPORTED, 53 VPE_STATUS_COLOR_SPACE_VALUE_NOT_SUPPORTED, 54 VPE_STATUS_SCALING_RATIO_NOT_SUPPORTED, 55 VPE_STATUS_PITCH_ALIGNMENT_NOT_SUPPORTED, 56 VPE_STATUS_ROTATION_NOT_SUPPORTED, 57 VPE_STATUS_MIRROR_NOT_SUPPORTED, 58 VPE_STATUS_ALPHA_BLENDING_NOT_SUPPORTED, 59 VPE_STATUS_VIEWPORT_SIZE_NOT_SUPPORTED, 60 VPE_STATUS_LUMA_KEYING_NOT_SUPPORTED, 61 VPE_STATUS_PLANE_ADDR_NOT_SUPPORTED, 62 VPE_STATUS_ADJUSTMENT_NOT_SUPPORTED, 63 VPE_STATUS_CMD_OVERFLOW_ERROR, 64 VPE_STATUS_SEGMENT_WIDTH_ERROR, 65 VPE_STATUS_PARAM_CHECK_ERROR, 66 VPE_STATUS_TONE_MAP_NOT_SUPPORTED, 67 VPE_STATUS_BAD_TONE_MAP_PARAMS, 68 VPE_STATUS_BAD_HDR_METADATA, 69 VPE_STATUS_BUFFER_OVERFLOW, 70 VPE_STATUS_BUFFER_UNDERRUN, 71 VPE_STATUS_BG_COLOR_OUT_OF_RANGE, 72 VPE_STATUS_REPEAT_ITEM, 73 VPE_STATUS_PATCH_OVER_MAXSIZE, 74 VPE_STATUS_INVALID_BUFFER_SIZE, 75 VPE_STATUS_SCALER_NOT_SET, 76 VPE_STATUS_GEOMETRICSCALING_ERROR 77 }; 78 79 /** HW IP level */ 80 enum vpe_ip_level { 81 VPE_IP_LEVEL_UNKNOWN = (-1), 82 VPE_IP_LEVEL_1_0, 83 }; 84 85 /**************************************** 86 * Plane Caps 87 ****************************************/ 88 struct vpe_pixel_format_support { 89 uint32_t argb_packed_32b : 1; 90 uint32_t nv12 : 1; 91 uint32_t fp16 : 1; 92 uint32_t p010 : 1; /**< planar 4:2:0 10-bit */ 93 uint32_t p016 : 1; /**< planar 4:2:0 16-bit */ 94 uint32_t ayuv : 1; /**< packed 4:4:4 */ 95 uint32_t yuy2 : 1; /**< packed 4:2:2 */ 96 }; 97 98 struct vpe_plane_caps { 99 uint32_t per_pixel_alpha : 1; 100 101 struct vpe_pixel_format_support input_pixel_format_support; 102 struct vpe_pixel_format_support output_pixel_format_support; 103 104 /* max upscaling factor x 1000 105 * upscaling factors are always >= 1 106 * e.g. 1080p -> 8K is 4.0 => 4000 107 */ 108 uint32_t max_upscale_factor; 109 110 /* max downscale factor x1000 111 * downscale factors are always <= 1 112 * e.g 8K -> 1080p is 0.25 => 250 113 */ 114 uint32_t max_downscale_factor; 115 116 uint32_t pitch_alignment; /**< alignment in bytes */ 117 uint32_t addr_alignment; /**< alignment in bytes */ 118 uint32_t max_viewport_width; 119 }; 120 121 /************************* 122 * Color management caps 123 *************************/ 124 struct vpe_rom_curve_caps { 125 uint32_t srgb : 1; 126 uint32_t bt2020 : 1; 127 uint32_t gamma2_2 : 1; 128 uint32_t pq : 1; 129 uint32_t hlg : 1; 130 }; 131 132 struct dpp_color_caps { 133 uint32_t pre_csc : 1; 134 uint32_t luma_key : 1; 135 uint32_t dgam_ram : 1; 136 uint32_t post_csc : 1; /**< before gamut remap */ 137 uint32_t gamma_corr : 1; 138 uint32_t hw_3dlut : 1; 139 uint32_t ogam_ram : 1; 140 uint32_t ocsc : 1; 141 struct vpe_rom_curve_caps dgam_rom_caps; 142 }; 143 144 struct mpc_color_caps { 145 uint32_t gamut_remap : 1; 146 uint32_t ogam_ram : 1; 147 uint32_t ocsc : 1; 148 uint32_t shared_3d_lut : 1; /**< can be in either dpp or mpc, but single instance */ 149 uint32_t global_alpha : 1; /**< e.g. top plane 30 %. bottom 70 % */ 150 uint32_t top_bottom_blending : 1; /**< two-layer blending */ 151 }; 152 153 struct vpe_color_caps { 154 struct dpp_color_caps dpp; 155 struct mpc_color_caps mpc; 156 }; 157 158 /************************************************** 159 * VPE Capabilities. 160 * 161 * Those depend on the condition like input format 162 * shall be queried by vpe_cap_funcs 163 **************************************************/ 164 struct vpe_caps { 165 uint32_t max_downscale_ratio; /**< max downscaling ratio in hundred. 166 ratio as src/dest x 100. e.g 600 */ 167 uint64_t lut_size; /**< 3dlut size */ 168 169 uint32_t rotation_support : 1; 170 uint32_t h_mirror_support : 1; 171 uint32_t v_mirror_support : 1; 172 uint32_t is_apu : 1; 173 uint32_t bg_color_check_support : 1; 174 struct { 175 int num_dpp; 176 int num_opp; 177 int num_mpc_3dlut; 178 179 int num_queue; /**< num of hw queue */ 180 } resource_caps; 181 182 struct vpe_color_caps color_caps; 183 struct vpe_plane_caps plane_caps; 184 }; 185 186 /*********************************** 187 * Conditional Capabilities 188 ***********************************/ 189 /** DCC CAP */ 190 struct vpe_dcc_surface_param { 191 struct vpe_size surface_size; 192 enum vpe_surface_pixel_format format; 193 enum vpe_swizzle_mode_values swizzle_mode; 194 enum vpe_scan_direction scan; 195 }; 196 197 struct vpe_dcc_setting { 198 unsigned int max_compressed_blk_size; 199 unsigned int max_uncompressed_blk_size; 200 bool independent_64b_blks; 201 202 struct { 203 uint32_t dcc_256_64_64 : 1; 204 uint32_t dcc_128_128_uncontrained : 1; 205 uint32_t dcc_256_128_128 : 1; 206 uint32_t dcc_256_256_unconstrained : 1; 207 } dcc_controls; 208 }; 209 210 struct vpe_surface_dcc_cap { 211 union { 212 struct { 213 struct vpe_dcc_setting rgb; 214 } grph; 215 216 struct { 217 struct vpe_dcc_setting luma; 218 struct vpe_dcc_setting chroma; 219 } video; 220 }; 221 222 bool capable; 223 bool const_color_support; 224 }; 225 226 /** Conditional Capability functions */ 227 struct vpe_cap_funcs { 228 /** 229 * Get DCC support and setting according to the format, 230 * scan direction and swizzle mdoe. 231 * 232 * @param[in] vpe vpe instance 233 * @param[in] input surface and scan properties 234 * @param[in/out] output dcc capable result and related settings 235 * @return true if supported 236 */ 237 bool (*get_dcc_compression_cap)(const struct vpe *vpe, 238 const struct vpe_dcc_surface_param *input, struct vpe_surface_dcc_cap *output); 239 }; 240 241 /**************************************** 242 * VPE Init Param 243 ****************************************/ 244 /** Log function 245 * @param[in] log_ctx given in the struct vpe_init_params 246 * @param[in] fmt format string 247 */ 248 typedef void (*vpe_log_func_t)(void *log_ctx, const char *fmt, ...); 249 250 /** system memory zalloc, allocated memory initailized with 0 251 * 252 * @param[in] mem_ctx given in the struct vpe_init_params 253 * @param[in] size number of bytes 254 * @return allocated memory 255 */ 256 typedef void *(*vpe_zalloc_func_t)(void *mem_ctx, size_t size); 257 258 /** system memory free 259 * @param[in] mem_ctx given in the struct vpe_init_params 260 * @param[in] ptr number of bytes 261 */ 262 typedef void (*vpe_free_func_t)(void *mem_ctx, void *ptr); 263 264 struct vpe_callback_funcs { 265 void *log_ctx; /**< optional. provided by the caller and pass back to callback */ 266 vpe_log_func_t log; 267 268 void *mem_ctx; /**< optional. provided by the caller and pass back to callback */ 269 vpe_zalloc_func_t zalloc; 270 vpe_free_func_t free; 271 }; 272 273 struct vpe_mem_low_power_enable_options { 274 // override flags 275 struct { 276 uint32_t dscl : 1; 277 uint32_t cm : 1; 278 uint32_t mpc : 1; 279 } flags; 280 281 struct { 282 uint32_t dscl : 1; 283 uint32_t cm : 1; 284 uint32_t mpc : 1; 285 } bits; 286 }; 287 288 enum vpe_expansion_mode { 289 VPE_EXPANSION_MODE_DYNAMIC, 290 VPE_EXPANSION_MODE_ZERO 291 }; 292 293 enum vpe_clamping_range { 294 VPE_CLAMPING_FULL_RANGE = 0, /* No Clamping */ 295 VPE_CLAMPING_LIMITED_RANGE_8BPC, /* 8 bpc: Clamping 1 to FE */ 296 VPE_CLAMPING_LIMITED_RANGE_10BPC, /* 10 bpc: Clamping 4 to 3FB */ 297 VPE_CLAMPING_LIMITED_RANGE_12BPC, /* 12 bpc: Clamping 10 to FEF */ 298 /* Use programmable clampping value on FMT_CLAMP_COMPONENT_R/G/B. */ 299 VPE_CLAMPING_LIMITED_RANGE_PROGRAMMABLE 300 }; 301 302 struct vpe_clamping_params { 303 enum vpe_clamping_range clamping_range; 304 uint32_t r_clamp_component_upper; 305 uint32_t b_clamp_component_upper; 306 uint32_t g_clamp_component_upper; 307 uint32_t r_clamp_component_lower; 308 uint32_t b_clamp_component_lower; 309 uint32_t g_clamp_component_lower; 310 }; 311 312 struct vpe_visual_confirm { 313 union { 314 struct { 315 uint32_t input_format : 1; 316 uint32_t output_format : 1; 317 uint32_t reserved : 30; 318 }; 319 uint32_t value; 320 }; 321 }; 322 323 /** configurable params for debugging purpose */ 324 struct vpe_debug_options { 325 // override flags 326 struct { 327 uint32_t cm_in_bypass : 1; 328 uint32_t vpcnvc_bypass : 1; 329 uint32_t mpc_bypass : 1; 330 uint32_t identity_3dlut : 1; 331 uint32_t sce_3dlut : 1; 332 uint32_t disable_reuse_bit : 1; 333 uint32_t bg_color_fill_only : 1; 334 uint32_t assert_when_not_support : 1; 335 uint32_t bypass_gamcor : 1; 336 uint32_t bypass_ogam : 1; 337 uint32_t force_tf_calculation : 1; 338 uint32_t bypass_dpp_gamut_remap : 1; 339 uint32_t bypass_post_csc : 1; 340 uint32_t clamping_setting : 1; 341 uint32_t expansion_mode : 1; 342 uint32_t bypass_per_pixel_alpha : 1; 343 uint32_t dpp_crc_ctrl : 1; 344 uint32_t opp_pipe_crc_ctrl : 1; 345 uint32_t mpc_crc_ctrl : 1; 346 uint32_t bg_bit_depth : 1; 347 uint32_t visual_confirm : 1; 348 uint32_t skip_optimal_tap_check : 1; 349 } flags; 350 351 // valid only if the corresponding flag is set 352 uint32_t cm_in_bypass : 1; 353 uint32_t vpcnvc_bypass : 1; 354 uint32_t mpc_bypass : 1; 355 uint32_t identity_3dlut : 1; 356 uint32_t sce_3dlut : 1; 357 uint32_t disable_reuse_bit : 1; 358 uint32_t bg_color_fill_only : 1; 359 uint32_t assert_when_not_support : 1; 360 uint32_t bypass_gamcor : 1; 361 uint32_t bypass_ogam : 1; 362 uint32_t force_tf_calculation : 1; 363 uint32_t bypass_dpp_gamut_remap : 1; 364 uint32_t bypass_post_csc : 1; 365 uint32_t clamping_setting : 1; 366 uint32_t bypass_per_pixel_alpha : 1; 367 uint32_t dpp_crc_ctrl : 1; 368 uint32_t opp_pipe_crc_ctrl : 1; 369 uint32_t mpc_crc_ctrl : 1; 370 uint32_t skip_optimal_tap_check : 1; 371 uint32_t bg_bit_depth; 372 373 struct vpe_mem_low_power_enable_options enable_mem_low_power; 374 enum vpe_expansion_mode expansion_mode; 375 struct vpe_clamping_params clamping_params; 376 struct vpe_visual_confirm visual_confirm_params; 377 }; 378 379 struct vpe_init_data { 380 /** vpe ip info */ 381 uint8_t ver_major; 382 uint8_t ver_minor; 383 uint8_t ver_rev; 384 385 /** function callbacks */ 386 struct vpe_callback_funcs funcs; 387 388 /** debug options */ 389 struct vpe_debug_options debug; 390 }; 391 392 /** VPE instance created through vpelib entry function vpe_create() */ 393 struct vpe { 394 uint32_t version; /**< API version */ 395 enum vpe_ip_level level; /**< HW IP level */ 396 397 struct vpe_caps *caps; /**< general static chip caps */ 398 struct vpe_cap_funcs *cap_funcs; /**< conditional caps */ 399 }; 400 401 /***************************************************** 402 * Structures for build VPE command 403 *****************************************************/ 404 enum vpe_pixel_encoding { 405 VPE_PIXEL_ENCODING_YCbCr, 406 VPE_PIXEL_ENCODING_RGB, 407 VPE_PIXEL_ENCODING_COUNT 408 }; 409 410 enum vpe_color_range { 411 VPE_COLOR_RANGE_FULL, 412 VPE_COLOR_RANGE_STUDIO, 413 VPE_COLOR_RANGE_COUNT 414 }; 415 416 enum vpe_chroma_cositing { 417 VPE_CHROMA_COSITING_NONE, 418 VPE_CHROMA_COSITING_LEFT, 419 VPE_CHROMA_COSITING_TOPLEFT, 420 VPE_CHROMA_COSITING_COUNT 421 }; 422 423 enum vpe_color_primaries { 424 VPE_PRIMARIES_BT601, 425 VPE_PRIMARIES_BT709, 426 VPE_PRIMARIES_BT2020, 427 VPE_PRIMARIES_JFIF, 428 VPE_PRIMARIES_COUNT 429 }; 430 431 enum vpe_transfer_function { 432 VPE_TF_G22, 433 VPE_TF_G24, 434 VPE_TF_G10, 435 VPE_TF_PQ, 436 VPE_TF_PQ_NORMALIZED, 437 VPE_TF_HLG, 438 VPE_TF_SRGB, 439 VPE_TF_BT709, 440 VPE_TF_COUNT 441 }; 442 443 enum vpe_alpha_mode { 444 VPE_ALPHA_OPAQUE, 445 VPE_ALPHA_BGCOLOR 446 }; 447 448 struct vpe_color_space { 449 enum vpe_pixel_encoding encoding; 450 enum vpe_color_range range; 451 enum vpe_transfer_function tf; 452 enum vpe_chroma_cositing cositing; 453 enum vpe_color_primaries primaries; 454 }; 455 456 /* component values are in the range: 0 - 1.0f */ 457 struct vpe_color_rgba { 458 float r; 459 float g; 460 float b; 461 float a; 462 }; 463 464 struct vpe_color_ycbcra { 465 float y; 466 float cb; 467 float cr; 468 float a; 469 }; 470 471 struct vpe_color { 472 bool is_ycbcr; 473 union { 474 struct vpe_color_rgba rgba; 475 struct vpe_color_ycbcra ycbcra; 476 }; 477 }; 478 479 /** 480 * Adjustment Min Max default step 481 * Brightness -100.0f, 100.0f, 0.0f, 0.1f 482 * Contrast 0.0f, 2.0f, 1.0f, 0.01f 483 * Hue -180.0f, 180.0f, 0.0f, 1.0f 484 * Saturation 0.0f, 3.0f, 1.0f, 0.01f 485 * 486 */ 487 struct vpe_color_adjust { 488 float brightness; 489 float contrast; 490 float hue; 491 float saturation; 492 }; 493 494 struct vpe_surface_info { 495 496 /** surface addressing info */ 497 struct vpe_plane_address address; 498 enum vpe_swizzle_mode_values swizzle; 499 500 /** surface properties */ 501 struct vpe_plane_size plane_size; /**< pitch */ 502 struct vpe_plane_dcc_param dcc; 503 enum vpe_surface_pixel_format format; 504 505 struct vpe_color_space cs; 506 }; 507 508 struct vpe_blend_info { 509 bool blending; /**< enable blending */ 510 bool pre_multiplied_alpha; /**< is the pixel value pre-multiplied with alpha */ 511 bool global_alpha; /**< enable global alpha */ 512 float global_alpha_value; /**< global alpha value, should be 0.0~1.0 */ 513 }; 514 515 struct vpe_scaling_info { 516 517 struct vpe_rect src_rect; 518 struct vpe_rect dst_rect; 519 struct vpe_scaling_taps taps; 520 }; 521 522 struct vpe_scaling_filter_coeffs { 523 524 struct vpe_scaling_taps taps; 525 unsigned int nb_phases; 526 uint16_t horiz_polyphase_coeffs[MAX_NB_POLYPHASE_COEFFS]; /*max nb of taps is 4, max nb of 527 phases 33 = (32+1)*/ 528 uint16_t vert_polyphase_coeffs[MAX_NB_POLYPHASE_COEFFS]; /*max nb of taps is 4, max nb of phases 529 33 = (32+1)*/ 530 }; 531 532 struct vpe_hdr_metadata { 533 uint16_t redX; 534 uint16_t redY; 535 uint16_t greenX; 536 uint16_t greenY; 537 uint16_t blueX; 538 uint16_t blueY; 539 uint16_t whiteX; 540 uint16_t whiteY; 541 542 uint32_t min_mastering; // luminance in 1/10000 nits 543 uint32_t max_mastering; // luminance in nits 544 uint32_t max_content; 545 uint32_t avg_content; 546 }; 547 548 struct vpe_tonemap_params { 549 uint64_t UID; /* Unique ID for tonemap params */ 550 enum vpe_transfer_function shaper_tf; 551 enum vpe_transfer_function lut_out_tf; 552 enum vpe_color_primaries lut_in_gamut; 553 enum vpe_color_primaries lut_out_gamut; 554 uint16_t input_pq_norm_factor; 555 uint16_t lut_dim; 556 uint16_t *lut_data; 557 558 bool update_3dlut; 559 bool enable_3dlut; 560 }; 561 562 struct vpe_stream { 563 struct vpe_surface_info surface_info; 564 struct vpe_scaling_info scaling_info; 565 struct vpe_blend_info blend_info; 566 struct vpe_color_adjust color_adj; 567 struct vpe_tonemap_params tm_params; 568 struct vpe_hdr_metadata hdr_metadata; 569 struct vpe_scaling_filter_coeffs polyphase_scaling_coeffs; 570 enum vpe_rotation_angle rotation; 571 bool horizontal_mirror; 572 bool vertical_mirror; 573 bool use_external_scaling_coeffs; 574 bool enable_luma_key; 575 float lower_luma_bound; 576 float upper_luma_bound; 577 578 struct { 579 uint32_t hdr_metadata : 1; 580 uint32_t geometric_scaling : 1; /* support 1 input stream only, 581 * if set, gamut/gamma remapping will be disabled, 582 * blending will be disabled 583 * dst rect must equal to target rect */ 584 uint32_t reserved : 30; 585 } flags; 586 }; 587 588 struct vpe_build_param { 589 /** source */ 590 uint32_t num_streams; 591 struct vpe_stream *streams; 592 593 /** destination */ 594 struct vpe_surface_info dst_surface; 595 struct vpe_rect target_rect; /**< rectangle in target surface to be blt'd. Ranges out of rect 596 won't be touched */ 597 struct vpe_color bg_color; 598 enum vpe_alpha_mode alpha_mode; 599 struct vpe_hdr_metadata hdr_metadata; 600 601 // data flags 602 struct { 603 uint32_t hdr_metadata : 1; 604 uint32_t reserved : 31; 605 } flags; 606 607 }; 608 609 /** reported through vpe_check_support() 610 * Once the operation is supported, 611 * it returns the required memory for storing 612 * 1. command buffer 613 * 2. embedded buffer 614 * - Pointed by the command buffer content. 615 * - Shall be free'ed together with command buffer once 616 * command is finished. 617 */ 618 struct vpe_bufs_req { 619 uint64_t cmd_buf_size; /**< total command buffer size for all vpe commands */ 620 uint64_t emb_buf_size; /**< total size for storing all embedded data */ 621 }; 622 623 struct vpe_buf { 624 uint64_t gpu_va; /**< GPU start address of the buffer */ 625 uint64_t cpu_va; 626 uint64_t size; 627 bool tmz; /**< allocated from tmz */ 628 }; 629 630 struct vpe_build_bufs { 631 struct vpe_buf cmd_buf; /**< Command buffer. gpu_va is optional */ 632 struct vpe_buf emb_buf; /**< Embedded buffer */ 633 }; 634 635 #ifdef __cplusplus 636 } 637 #endif 638