Searched refs:Riscv64Core (Results 1 – 5 of 5) sorted by relevance
94 opcodes.DefCFA(Reg::Riscv64Core(2), 0); // X2(SP). in WriteCIE()98 opcodes.Undefined(Reg::Riscv64Core(reg)); in WriteCIE()100 opcodes.SameValue(Reg::Riscv64Core(reg)); in WriteCIE()111 auto return_reg = Reg::Riscv64Core(1); // X1(RA). in WriteCIE()
42 return Reg::Riscv64Core(machine_reg); in GetDwarfCoreReg()
43 static Reg Riscv64Core(int num) { return Reg(num); } // X0-X31 in Riscv64Core() function
78 __ cfi().RelOffset(dwarf::Reg::Riscv64Core(RA), offset); in BuildFrame()83 __ cfi().RelOffset(dwarf::Reg::Riscv64Core(enum_cast<XRegister>(reg)), offset); in BuildFrame()113 __ cfi().Restore(dwarf::Reg::Riscv64Core(enum_cast<XRegister>(reg))); in RemoveFrame()118 __ cfi().Restore(dwarf::Reg::Riscv64Core(RA)); in RemoveFrame()
6033 __ cfi().RelOffset(dwarf::Reg::Riscv64Core(reg), offset); in GenerateFrameEntry()6076 __ cfi().Restore(dwarf::Reg::Riscv64Core(reg)); in GenerateFrameExit()