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Searched refs:out_reg (Results 1 – 19 of 19) sorted by relevance

/art/tools/dexanalyze/
Ddexanalyze_bytecode.cc266 uint32_t out_reg = inst->VRegA_22c(); in ProcessCodeItem() local
274 ExtendPrefix(&out_reg, &field_idx); in ProcessCodeItem()
275 CHECK(InstNibbles(new_opcode, {out_reg, field_idx})); in ProcessCodeItem()
286 CHECK(InstNibbles(new_opcode, {out_reg, receiver, type_idx, field_idx})); in ProcessCodeItem()
296 uint32_t out_reg = is_jumbo ? inst->VRegA_31c() : inst->VRegA_21c(); in ProcessCodeItem() local
303 ExtendPrefix(&out_reg, &idx); in ProcessCodeItem()
304 CHECK(InstNibbles(opcode, {out_reg, idx})); in ProcessCodeItem()
324 uint32_t out_reg = inst->VRegA_21c(); in ProcessCodeItem() local
334 ExtendPrefix(&out_reg, &field_idx); in ProcessCodeItem()
335 if (InstNibbles(new_opcode, {out_reg, field_idx})) { in ProcessCodeItem()
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/art/compiler/utils/arm/
Djni_macro_assembler_arm_vixl.cc799 vixl::aarch32::Register out_reg = AsVIXLRegister(mout_reg.AsArm()); in CreateJObject() local
803 temps.Exclude(out_reg); in CreateJObject()
809 asm_.LoadFromOffset(kLoadWord, out_reg, sp, spilled_reference_offset.Int32Value()); in CreateJObject()
810 in_reg = out_reg; in CreateJObject()
813 if (out_reg.IsLow() && spilled_reference_offset.Uint32Value() < kAddSpImmCutoff) { in CreateJObject()
815 if (out_reg.Is(in_reg)) { in CreateJObject()
818 ___ Movs(out_reg, in_reg); in CreateJObject()
823 ___ add(ne, Narrow, out_reg, sp, spilled_reference_offset.Int32Value()); in CreateJObject()
825 vixl32::Register addr_reg = out_reg.Is(in_reg) ? temps.Acquire() : out_reg; in CreateJObject()
826 vixl32::Register cond_mov_src_reg = out_reg.Is(in_reg) ? addr_reg : in_reg; in CreateJObject()
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Djni_macro_assembler_arm_vixl.h162 void CreateJObject(ManagedRegister out_reg,
/art/compiler/utils/x86/
Djni_macro_assembler_x86.cc359 X86ManagedRegister out_reg = mout_reg.AsX86(); in CreateJObject() local
362 CHECK(out_reg.IsCpuRegister()); in CreateJObject()
366 if (!out_reg.Equals(in_reg)) { in CreateJObject()
367 __ xorl(out_reg.AsCpuRegister(), out_reg.AsCpuRegister()); in CreateJObject()
371 __ leal(out_reg.AsCpuRegister(), Address(ESP, spilled_reference_offset)); in CreateJObject()
374 __ leal(out_reg.AsCpuRegister(), Address(ESP, spilled_reference_offset)); in CreateJObject()
Djni_macro_assembler_x86.h150 void CreateJObject(ManagedRegister out_reg,
/art/compiler/utils/x86_64/
Djni_macro_assembler_x86_64.cc426 X86_64ManagedRegister out_reg = mout_reg.AsX86_64(); in CreateJObject() local
430 in_reg = out_reg; in CreateJObject()
435 CHECK(out_reg.IsCpuRegister()); in CreateJObject()
439 if (!out_reg.Equals(in_reg)) { in CreateJObject()
440 __ xorl(out_reg.AsCpuRegister(), out_reg.AsCpuRegister()); in CreateJObject()
444 __ leaq(out_reg.AsCpuRegister(), Address(CpuRegister(RSP), spilled_reference_offset)); in CreateJObject()
447 __ leaq(out_reg.AsCpuRegister(), Address(CpuRegister(RSP), spilled_reference_offset)); in CreateJObject()
Djni_macro_assembler_x86_64.h151 void CreateJObject(ManagedRegister out_reg,
/art/compiler/utils/arm64/
Djni_macro_assembler_arm64.cc653 Arm64ManagedRegister out_reg = m_out_reg.AsArm64(); in CreateJObject() local
656 CHECK(out_reg.IsXRegister()) << out_reg; in CreateJObject()
665 in_reg = Arm64ManagedRegister::FromWRegister(out_reg.AsOverlappingWRegister()); in CreateJObject()
670 ___ Csel(reg_x(out_reg.AsXRegister()), scratch, xzr, ne); in CreateJObject()
672 AddConstant(out_reg.AsXRegister(), SP, spilled_reference_offset.Int32Value(), al); in CreateJObject()
Djni_macro_assembler_arm64.h183 void CreateJObject(ManagedRegister out_reg,
/art/compiler/optimizing/
Dcode_generator_arm_vixl.cc4895 vixl32::Register out_reg = OutputRegister(rem); in VisitRem() local
4905 __ Mls(out_reg, temp, reg2, reg1); in VisitRem()
4910 DCHECK(out_reg.Is(r1)); in VisitRem()
5203 vixl32::Register out_reg = RegisterFrom(locations->Out()); in VisitAbs() local
5206 __ Add(out_reg, in_reg, mask); in VisitAbs()
5207 __ Eor(out_reg, out_reg, mask); in VisitAbs()
5474 vixl32::Register out_reg = OutputRegister(op); in HandleShift() local
5479 __ And(out_reg, second_reg, kMaxIntShiftDistance); in HandleShift()
5481 __ Lsl(out_reg, first_reg, out_reg); in HandleShift()
5483 __ Asr(out_reg, first_reg, out_reg); in HandleShift()
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Dinstruction_builder.h127 void BuildCheckedDivRem(uint16_t out_reg,
Dcode_generator_riscv64.cc1202 XRegister out_reg = out.AsRegister<XRegister>(); in GenerateReferenceLoadOneRegister() local
1210 out_reg, in GenerateReferenceLoadOneRegister()
1219 __ Mv(maybe_temp.AsRegister<XRegister>(), out_reg); in GenerateReferenceLoadOneRegister()
1221 __ Loadwu(out_reg, out_reg, offset); in GenerateReferenceLoadOneRegister()
1227 __ Loadwu(out_reg, out_reg, offset); in GenerateReferenceLoadOneRegister()
1228 codegen_->MaybeUnpoisonHeapReference(out_reg); in GenerateReferenceLoadOneRegister()
1239 XRegister out_reg = out.AsRegister<XRegister>(); in GenerateReferenceLoadTwoRegisters() local
1255 __ Loadwu(out_reg, obj_reg, offset); in GenerateReferenceLoadTwoRegisters()
1261 __ Loadwu(out_reg, obj_reg, offset); in GenerateReferenceLoadTwoRegisters()
1262 codegen_->MaybeUnpoisonHeapReference(out_reg); in GenerateReferenceLoadTwoRegisters()
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Dcode_generator_arm64.cc6296 Register out_reg = OutputRegister(abs); in VisitAbs() local
6298 __ Cneg(out_reg, in_reg, lt); in VisitAbs()
6304 VRegister out_reg = OutputFPRegister(abs); in VisitAbs() local
6305 __ Fabs(out_reg, in_reg); in VisitAbs()
6717 Register out_reg = RegisterFrom(out, type); in GenerateReferenceLoadOneRegister() local
6725 out_reg, in GenerateReferenceLoadOneRegister()
6736 __ Mov(temp_reg, out_reg); in GenerateReferenceLoadOneRegister()
6738 __ Ldr(out_reg, HeapOperand(out_reg, offset)); in GenerateReferenceLoadOneRegister()
6744 __ Ldr(out_reg, HeapOperand(out_reg, offset)); in GenerateReferenceLoadOneRegister()
6745 GetAssembler()->MaybeUnpoisonHeapReference(out_reg); in GenerateReferenceLoadOneRegister()
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Dintrinsics_x86.cc2570 Register out_reg = out.AsRegister<Register>(); in GenUnsafeGetAndUpdate() local
2573 __ LockXaddl(field_address, out_reg); in GenUnsafeGetAndUpdate()
2576 __ xchgl(out_reg, field_address); in GenUnsafeGetAndUpdate()
2611 Register out_reg = out.AsRegister<Register>(); in GenUnsafeGetAndUpdate() local
2632 codegen->MaybeMarkGCCard(temp1, temp2, base, /*value=*/out_reg, new_value_can_be_null); in GenUnsafeGetAndUpdate()
2637 __ movl(temp1, out_reg); in GenUnsafeGetAndUpdate()
2641 __ movl(out_reg, temp1); in GenUnsafeGetAndUpdate()
2643 __ xchgl(out_reg, field_address); in GenUnsafeGetAndUpdate()
Dcode_generator_x86_64.cc7847 CpuRegister out_reg = out.AsRegister<CpuRegister>(); in GenerateReferenceLoadOneRegister() local
7854 instruction, out, out_reg, offset, /* needs_null_check= */ false); in GenerateReferenceLoadOneRegister()
7861 __ movl(maybe_temp.AsRegister<CpuRegister>(), out_reg); in GenerateReferenceLoadOneRegister()
7863 __ movl(out_reg, Address(out_reg, offset)); in GenerateReferenceLoadOneRegister()
7869 __ movl(out_reg, Address(out_reg, offset)); in GenerateReferenceLoadOneRegister()
7870 __ MaybeUnpoisonHeapReference(out_reg); in GenerateReferenceLoadOneRegister()
7880 CpuRegister out_reg = out.AsRegister<CpuRegister>(); in GenerateReferenceLoadTwoRegisters() local
7892 __ movl(out_reg, Address(obj_reg, offset)); in GenerateReferenceLoadTwoRegisters()
7898 __ movl(out_reg, Address(obj_reg, offset)); in GenerateReferenceLoadTwoRegisters()
7899 __ MaybeUnpoisonHeapReference(out_reg); in GenerateReferenceLoadTwoRegisters()
Dcode_generator_x86.cc8527 Register out_reg = out.AsRegister<Register>(); in GenerateReferenceLoadOneRegister() local
8534 instruction, out, out_reg, offset, /* needs_null_check= */ false); in GenerateReferenceLoadOneRegister()
8541 __ movl(maybe_temp.AsRegister<Register>(), out_reg); in GenerateReferenceLoadOneRegister()
8543 __ movl(out_reg, Address(out_reg, offset)); in GenerateReferenceLoadOneRegister()
8549 __ movl(out_reg, Address(out_reg, offset)); in GenerateReferenceLoadOneRegister()
8550 __ MaybeUnpoisonHeapReference(out_reg); in GenerateReferenceLoadOneRegister()
8560 Register out_reg = out.AsRegister<Register>(); in GenerateReferenceLoadTwoRegisters() local
8572 __ movl(out_reg, Address(obj_reg, offset)); in GenerateReferenceLoadTwoRegisters()
8578 __ movl(out_reg, Address(obj_reg, offset)); in GenerateReferenceLoadTwoRegisters()
8579 __ MaybeUnpoisonHeapReference(out_reg); in GenerateReferenceLoadTwoRegisters()
Dintrinsics_arm64.cc567 Register out_reg = is_double ? XRegisterFrom(l->Out()) : WRegisterFrom(l->Out()); in GenMathRound() local
571 __ Fcvtas(out_reg, in_reg); in GenMathRound()
574 __ Tbz(out_reg, out_reg.GetSizeInBits() - 1, &done); in GenMathRound()
582 __ Cinc(out_reg, out_reg, eq); in GenMathRound()
Dintrinsics_arm_vixl.cc381 vixl32::Register out_reg = OutputRegister(invoke); in VisitMathRoundFloat() local
389 __ Vmov(out_reg, temp1); in VisitMathRoundFloat()
392 __ Cmp(out_reg, 0); in VisitMathRoundFloat()
409 __ add(eq, out_reg, out_reg, 1); in VisitMathRoundFloat()
/art/oatdump/
Doatdump.cc1459 for (size_t out_reg = 0; out_reg < num_outs; out_reg++) { in DumpVregLocations() local
1460 if (out_reg == 0) { in DumpVregLocations()
1464 uint32_t offset = GetOutVROffset(out_reg, GetInstructionSet()); in DumpVregLocations()
1465 os << " v" << out_reg << "[sp + #" << offset << "]"; in DumpVregLocations()