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1  /*
2   * This file is auto-generated. Modifications will be lost.
3   *
4   * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/
5   * for more information.
6   */
7  #ifndef OMAP3_ISP_USER_H
8  #define OMAP3_ISP_USER_H
9  #include <linux/types.h>
10  #include <linux/videodev2.h>
11  #define VIDIOC_OMAP3ISP_CCDC_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 1, struct omap3isp_ccdc_update_config)
12  #define VIDIOC_OMAP3ISP_PRV_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 2, struct omap3isp_prev_update_config)
13  #define VIDIOC_OMAP3ISP_AEWB_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 3, struct omap3isp_h3a_aewb_config)
14  #define VIDIOC_OMAP3ISP_HIST_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 4, struct omap3isp_hist_config)
15  #define VIDIOC_OMAP3ISP_AF_CFG _IOWR('V', BASE_VIDIOC_PRIVATE + 5, struct omap3isp_h3a_af_config)
16  #define VIDIOC_OMAP3ISP_STAT_REQ _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct omap3isp_stat_data)
17  #define VIDIOC_OMAP3ISP_STAT_REQ_TIME32 _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct omap3isp_stat_data_time32)
18  #define VIDIOC_OMAP3ISP_STAT_EN _IOWR('V', BASE_VIDIOC_PRIVATE + 7, unsigned long)
19  #define V4L2_EVENT_OMAP3ISP_CLASS (V4L2_EVENT_PRIVATE_START | 0x100)
20  #define V4L2_EVENT_OMAP3ISP_AEWB (V4L2_EVENT_OMAP3ISP_CLASS | 0x1)
21  #define V4L2_EVENT_OMAP3ISP_AF (V4L2_EVENT_OMAP3ISP_CLASS | 0x2)
22  #define V4L2_EVENT_OMAP3ISP_HIST (V4L2_EVENT_OMAP3ISP_CLASS | 0x3)
23  struct omap3isp_stat_event_status {
24    __u32 frame_number;
25    __u16 config_counter;
26    __u8 buf_err;
27  };
28  #define OMAP3ISP_AEWB_MAX_SATURATION_LIM 1023
29  #define OMAP3ISP_AEWB_MIN_WIN_H 2
30  #define OMAP3ISP_AEWB_MAX_WIN_H 256
31  #define OMAP3ISP_AEWB_MIN_WIN_W 6
32  #define OMAP3ISP_AEWB_MAX_WIN_W 256
33  #define OMAP3ISP_AEWB_MIN_WINVC 1
34  #define OMAP3ISP_AEWB_MIN_WINHC 1
35  #define OMAP3ISP_AEWB_MAX_WINVC 128
36  #define OMAP3ISP_AEWB_MAX_WINHC 36
37  #define OMAP3ISP_AEWB_MAX_WINSTART 4095
38  #define OMAP3ISP_AEWB_MIN_SUB_INC 2
39  #define OMAP3ISP_AEWB_MAX_SUB_INC 32
40  #define OMAP3ISP_AEWB_MAX_BUF_SIZE 83600
41  #define OMAP3ISP_AF_IIRSH_MIN 0
42  #define OMAP3ISP_AF_IIRSH_MAX 4095
43  #define OMAP3ISP_AF_PAXEL_HORIZONTAL_COUNT_MIN 1
44  #define OMAP3ISP_AF_PAXEL_HORIZONTAL_COUNT_MAX 36
45  #define OMAP3ISP_AF_PAXEL_VERTICAL_COUNT_MIN 1
46  #define OMAP3ISP_AF_PAXEL_VERTICAL_COUNT_MAX 128
47  #define OMAP3ISP_AF_PAXEL_INCREMENT_MIN 2
48  #define OMAP3ISP_AF_PAXEL_INCREMENT_MAX 32
49  #define OMAP3ISP_AF_PAXEL_HEIGHT_MIN 2
50  #define OMAP3ISP_AF_PAXEL_HEIGHT_MAX 256
51  #define OMAP3ISP_AF_PAXEL_WIDTH_MIN 16
52  #define OMAP3ISP_AF_PAXEL_WIDTH_MAX 256
53  #define OMAP3ISP_AF_PAXEL_HZSTART_MIN 1
54  #define OMAP3ISP_AF_PAXEL_HZSTART_MAX 4095
55  #define OMAP3ISP_AF_PAXEL_VTSTART_MIN 0
56  #define OMAP3ISP_AF_PAXEL_VTSTART_MAX 4095
57  #define OMAP3ISP_AF_THRESHOLD_MAX 255
58  #define OMAP3ISP_AF_COEF_MAX 4095
59  #define OMAP3ISP_AF_PAXEL_SIZE 48
60  #define OMAP3ISP_AF_MAX_BUF_SIZE 221184
61  struct omap3isp_h3a_aewb_config {
62    __u32 buf_size;
63    __u16 config_counter;
64    __u16 saturation_limit;
65    __u16 win_height;
66    __u16 win_width;
67    __u16 ver_win_count;
68    __u16 hor_win_count;
69    __u16 ver_win_start;
70    __u16 hor_win_start;
71    __u16 blk_ver_win_start;
72    __u16 blk_win_height;
73    __u16 subsample_ver_inc;
74    __u16 subsample_hor_inc;
75    __u8 alaw_enable;
76  };
77  struct omap3isp_stat_data {
78    struct timeval ts;
79    void  * buf;
80    __struct_group(, frame,, __u32 buf_size;
81    __u16 frame_number;
82    __u16 cur_frame;
83    __u16 config_counter;
84   );
85  };
86  #define OMAP3ISP_HIST_BINS_32 0
87  #define OMAP3ISP_HIST_BINS_64 1
88  #define OMAP3ISP_HIST_BINS_128 2
89  #define OMAP3ISP_HIST_BINS_256 3
90  #define OMAP3ISP_HIST_MEM_SIZE_BINS(n) ((1 << ((n) + 5)) * 4 * 4)
91  #define OMAP3ISP_HIST_MEM_SIZE 1024
92  #define OMAP3ISP_HIST_MIN_REGIONS 1
93  #define OMAP3ISP_HIST_MAX_REGIONS 4
94  #define OMAP3ISP_HIST_MAX_WB_GAIN 255
95  #define OMAP3ISP_HIST_MIN_WB_GAIN 0
96  #define OMAP3ISP_HIST_MAX_BIT_WIDTH 14
97  #define OMAP3ISP_HIST_MIN_BIT_WIDTH 8
98  #define OMAP3ISP_HIST_MAX_WG 4
99  #define OMAP3ISP_HIST_MAX_BUF_SIZE 4096
100  #define OMAP3ISP_HIST_SOURCE_CCDC 0
101  #define OMAP3ISP_HIST_SOURCE_MEM 1
102  #define OMAP3ISP_HIST_CFA_BAYER 0
103  #define OMAP3ISP_HIST_CFA_FOVEONX3 1
104  struct omap3isp_hist_region {
105    __u16 h_start;
106    __u16 h_end;
107    __u16 v_start;
108    __u16 v_end;
109  };
110  struct omap3isp_hist_config {
111    __u32 buf_size;
112    __u16 config_counter;
113    __u8 num_acc_frames;
114    __u16 hist_bins;
115    __u8 cfa;
116    __u8 wg[OMAP3ISP_HIST_MAX_WG];
117    __u8 num_regions;
118    struct omap3isp_hist_region region[OMAP3ISP_HIST_MAX_REGIONS];
119  };
120  #define OMAP3ISP_AF_NUM_COEF 11
121  enum omap3isp_h3a_af_fvmode {
122    OMAP3ISP_AF_MODE_SUMMED = 0,
123    OMAP3ISP_AF_MODE_PEAK = 1
124  };
125  enum omap3isp_h3a_af_rgbpos {
126    OMAP3ISP_AF_GR_GB_BAYER = 0,
127    OMAP3ISP_AF_RG_GB_BAYER = 1,
128    OMAP3ISP_AF_GR_BG_BAYER = 2,
129    OMAP3ISP_AF_RG_BG_BAYER = 3,
130    OMAP3ISP_AF_GG_RB_CUSTOM = 4,
131    OMAP3ISP_AF_RB_GG_CUSTOM = 5
132  };
133  struct omap3isp_h3a_af_hmf {
134    __u8 enable;
135    __u8 threshold;
136  };
137  struct omap3isp_h3a_af_iir {
138    __u16 h_start;
139    __u16 coeff_set0[OMAP3ISP_AF_NUM_COEF];
140    __u16 coeff_set1[OMAP3ISP_AF_NUM_COEF];
141  };
142  struct omap3isp_h3a_af_paxel {
143    __u16 h_start;
144    __u16 v_start;
145    __u8 width;
146    __u8 height;
147    __u8 h_cnt;
148    __u8 v_cnt;
149    __u8 line_inc;
150  };
151  struct omap3isp_h3a_af_config {
152    __u32 buf_size;
153    __u16 config_counter;
154    struct omap3isp_h3a_af_hmf hmf;
155    struct omap3isp_h3a_af_iir iir;
156    struct omap3isp_h3a_af_paxel paxel;
157    enum omap3isp_h3a_af_rgbpos rgb_pos;
158    enum omap3isp_h3a_af_fvmode fvmode;
159    __u8 alaw_enable;
160  };
161  #define OMAP3ISP_CCDC_ALAW (1 << 0)
162  #define OMAP3ISP_CCDC_LPF (1 << 1)
163  #define OMAP3ISP_CCDC_BLCLAMP (1 << 2)
164  #define OMAP3ISP_CCDC_BCOMP (1 << 3)
165  #define OMAP3ISP_CCDC_FPC (1 << 4)
166  #define OMAP3ISP_CCDC_CULL (1 << 5)
167  #define OMAP3ISP_CCDC_CONFIG_LSC (1 << 7)
168  #define OMAP3ISP_CCDC_TBL_LSC (1 << 8)
169  #define OMAP3ISP_RGB_MAX 3
170  enum omap3isp_alaw_ipwidth {
171    OMAP3ISP_ALAW_BIT12_3 = 0x3,
172    OMAP3ISP_ALAW_BIT11_2 = 0x4,
173    OMAP3ISP_ALAW_BIT10_1 = 0x5,
174    OMAP3ISP_ALAW_BIT9_0 = 0x6
175  };
176  struct omap3isp_ccdc_lsc_config {
177    __u16 offset;
178    __u8 gain_mode_n;
179    __u8 gain_mode_m;
180    __u8 gain_format;
181    __u16 fmtsph;
182    __u16 fmtlnh;
183    __u16 fmtslv;
184    __u16 fmtlnv;
185    __u8 initial_x;
186    __u8 initial_y;
187    __u32 size;
188  };
189  struct omap3isp_ccdc_bclamp {
190    __u8 obgain;
191    __u8 obstpixel;
192    __u8 oblines;
193    __u8 oblen;
194    __u16 dcsubval;
195  };
196  struct omap3isp_ccdc_fpc {
197    __u16 fpnum;
198    __u32 fpcaddr;
199  };
200  struct omap3isp_ccdc_blcomp {
201    __u8 b_mg;
202    __u8 gb_g;
203    __u8 gr_cy;
204    __u8 r_ye;
205  };
206  struct omap3isp_ccdc_culling {
207    __u8 v_pattern;
208    __u16 h_odd;
209    __u16 h_even;
210  };
211  struct omap3isp_ccdc_update_config {
212    __u16 update;
213    __u16 flag;
214    enum omap3isp_alaw_ipwidth alawip;
215    struct omap3isp_ccdc_bclamp  * bclamp;
216    struct omap3isp_ccdc_blcomp  * blcomp;
217    struct omap3isp_ccdc_fpc  * fpc;
218    struct omap3isp_ccdc_lsc_config  * lsc_cfg;
219    struct omap3isp_ccdc_culling  * cull;
220    __u8  * lsc;
221  };
222  #define OMAP3ISP_PREV_LUMAENH (1 << 0)
223  #define OMAP3ISP_PREV_INVALAW (1 << 1)
224  #define OMAP3ISP_PREV_HRZ_MED (1 << 2)
225  #define OMAP3ISP_PREV_CFA (1 << 3)
226  #define OMAP3ISP_PREV_CHROMA_SUPP (1 << 4)
227  #define OMAP3ISP_PREV_WB (1 << 5)
228  #define OMAP3ISP_PREV_BLKADJ (1 << 6)
229  #define OMAP3ISP_PREV_RGB2RGB (1 << 7)
230  #define OMAP3ISP_PREV_COLOR_CONV (1 << 8)
231  #define OMAP3ISP_PREV_YC_LIMIT (1 << 9)
232  #define OMAP3ISP_PREV_DEFECT_COR (1 << 10)
233  #define OMAP3ISP_PREV_DRK_FRM_CAPTURE (1 << 12)
234  #define OMAP3ISP_PREV_DRK_FRM_SUBTRACT (1 << 13)
235  #define OMAP3ISP_PREV_LENS_SHADING (1 << 14)
236  #define OMAP3ISP_PREV_NF (1 << 15)
237  #define OMAP3ISP_PREV_GAMMA (1 << 16)
238  #define OMAP3ISP_PREV_NF_TBL_SIZE 64
239  #define OMAP3ISP_PREV_CFA_TBL_SIZE 576
240  #define OMAP3ISP_PREV_CFA_BLK_SIZE (OMAP3ISP_PREV_CFA_TBL_SIZE / 4)
241  #define OMAP3ISP_PREV_GAMMA_TBL_SIZE 1024
242  #define OMAP3ISP_PREV_YENH_TBL_SIZE 128
243  #define OMAP3ISP_PREV_DETECT_CORRECT_CHANNELS 4
244  struct omap3isp_prev_hmed {
245    __u8 odddist;
246    __u8 evendist;
247    __u8 thres;
248  };
249  enum omap3isp_cfa_fmt {
250    OMAP3ISP_CFAFMT_BAYER,
251    OMAP3ISP_CFAFMT_SONYVGA,
252    OMAP3ISP_CFAFMT_RGBFOVEON,
253    OMAP3ISP_CFAFMT_DNSPL,
254    OMAP3ISP_CFAFMT_HONEYCOMB,
255    OMAP3ISP_CFAFMT_RRGGBBFOVEON
256  };
257  struct omap3isp_prev_cfa {
258    enum omap3isp_cfa_fmt format;
259    __u8 gradthrs_vert;
260    __u8 gradthrs_horz;
261    __u32 table[4][OMAP3ISP_PREV_CFA_BLK_SIZE];
262  };
263  struct omap3isp_prev_csup {
264    __u8 gain;
265    __u8 thres;
266    __u8 hypf_en;
267  };
268  struct omap3isp_prev_wbal {
269    __u16 dgain;
270    __u8 coef3;
271    __u8 coef2;
272    __u8 coef1;
273    __u8 coef0;
274  };
275  struct omap3isp_prev_blkadj {
276    __u8 red;
277    __u8 green;
278    __u8 blue;
279  };
280  struct omap3isp_prev_rgbtorgb {
281    __u16 matrix[OMAP3ISP_RGB_MAX][OMAP3ISP_RGB_MAX];
282    __u16 offset[OMAP3ISP_RGB_MAX];
283  };
284  struct omap3isp_prev_csc {
285    __u16 matrix[OMAP3ISP_RGB_MAX][OMAP3ISP_RGB_MAX];
286    __s16 offset[OMAP3ISP_RGB_MAX];
287  };
288  struct omap3isp_prev_yclimit {
289    __u8 minC;
290    __u8 maxC;
291    __u8 minY;
292    __u8 maxY;
293  };
294  struct omap3isp_prev_dcor {
295    __u8 couplet_mode_en;
296    __u32 detect_correct[OMAP3ISP_PREV_DETECT_CORRECT_CHANNELS];
297  };
298  struct omap3isp_prev_nf {
299    __u8 spread;
300    __u32 table[OMAP3ISP_PREV_NF_TBL_SIZE];
301  };
302  struct omap3isp_prev_gtables {
303    __u32 red[OMAP3ISP_PREV_GAMMA_TBL_SIZE];
304    __u32 green[OMAP3ISP_PREV_GAMMA_TBL_SIZE];
305    __u32 blue[OMAP3ISP_PREV_GAMMA_TBL_SIZE];
306  };
307  struct omap3isp_prev_luma {
308    __u32 table[OMAP3ISP_PREV_YENH_TBL_SIZE];
309  };
310  struct omap3isp_prev_update_config {
311    __u32 update;
312    __u32 flag;
313    __u32 shading_shift;
314    struct omap3isp_prev_luma  * luma;
315    struct omap3isp_prev_hmed  * hmed;
316    struct omap3isp_prev_cfa  * cfa;
317    struct omap3isp_prev_csup  * csup;
318    struct omap3isp_prev_wbal  * wbal;
319    struct omap3isp_prev_blkadj  * blkadj;
320    struct omap3isp_prev_rgbtorgb  * rgb2rgb;
321    struct omap3isp_prev_csc  * csc;
322    struct omap3isp_prev_yclimit  * yclimit;
323    struct omap3isp_prev_dcor  * dcor;
324    struct omap3isp_prev_nf  * nf;
325    struct omap3isp_prev_gtables  * gamma;
326  };
327  #endif
328