• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1  /*
2   * This file is auto-generated. Modifications will be lost.
3   *
4   * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/
5   * for more information.
6   */
7  #ifndef HNS_ABI_USER_H
8  #define HNS_ABI_USER_H
9  #include <linux/types.h>
10  struct hns_roce_ib_create_cq {
11    __aligned_u64 buf_addr;
12    __aligned_u64 db_addr;
13    __u32 cqe_size;
14    __u32 reserved;
15  };
16  enum hns_roce_cq_cap_flags {
17    HNS_ROCE_CQ_FLAG_RECORD_DB = 1 << 0,
18  };
19  struct hns_roce_ib_create_cq_resp {
20    __aligned_u64 cqn;
21    __aligned_u64 cap_flags;
22  };
23  enum hns_roce_srq_cap_flags {
24    HNS_ROCE_SRQ_CAP_RECORD_DB = 1 << 0,
25  };
26  enum hns_roce_srq_cap_flags_resp {
27    HNS_ROCE_RSP_SRQ_CAP_RECORD_DB = 1 << 0,
28  };
29  struct hns_roce_ib_create_srq {
30    __aligned_u64 buf_addr;
31    __aligned_u64 db_addr;
32    __aligned_u64 que_addr;
33    __u32 req_cap_flags;
34    __u32 reserved;
35  };
36  struct hns_roce_ib_create_srq_resp {
37    __u32 srqn;
38    __u32 cap_flags;
39  };
40  enum hns_roce_congest_type_flags {
41    HNS_ROCE_CREATE_QP_FLAGS_DCQCN,
42    HNS_ROCE_CREATE_QP_FLAGS_LDCP,
43    HNS_ROCE_CREATE_QP_FLAGS_HC3,
44    HNS_ROCE_CREATE_QP_FLAGS_DIP,
45  };
46  enum hns_roce_create_qp_comp_mask {
47    HNS_ROCE_CREATE_QP_MASK_CONGEST_TYPE = 1 << 0,
48  };
49  struct hns_roce_ib_create_qp {
50    __aligned_u64 buf_addr;
51    __aligned_u64 db_addr;
52    __u8 log_sq_bb_count;
53    __u8 log_sq_stride;
54    __u8 sq_no_prefetch;
55    __u8 reserved[5];
56    __aligned_u64 sdb_addr;
57    __aligned_u64 comp_mask;
58    __aligned_u64 create_flags;
59    __aligned_u64 cong_type_flags;
60  };
61  enum hns_roce_qp_cap_flags {
62    HNS_ROCE_QP_CAP_RQ_RECORD_DB = 1 << 0,
63    HNS_ROCE_QP_CAP_SQ_RECORD_DB = 1 << 1,
64    HNS_ROCE_QP_CAP_OWNER_DB = 1 << 2,
65    HNS_ROCE_QP_CAP_DIRECT_WQE = 1 << 5,
66  };
67  struct hns_roce_ib_create_qp_resp {
68    __aligned_u64 cap_flags;
69    __aligned_u64 dwqe_mmap_key;
70  };
71  enum {
72    HNS_ROCE_EXSGE_FLAGS = 1 << 0,
73    HNS_ROCE_RQ_INLINE_FLAGS = 1 << 1,
74    HNS_ROCE_CQE_INLINE_FLAGS = 1 << 2,
75  };
76  enum {
77    HNS_ROCE_RSP_EXSGE_FLAGS = 1 << 0,
78    HNS_ROCE_RSP_RQ_INLINE_FLAGS = 1 << 1,
79    HNS_ROCE_RSP_CQE_INLINE_FLAGS = 1 << 2,
80  };
81  struct hns_roce_ib_alloc_ucontext_resp {
82    __u32 qp_tab_size;
83    __u32 cqe_size;
84    __u32 srq_tab_size;
85    __u32 reserved;
86    __u32 config;
87    __u32 max_inline_data;
88    __u8 congest_type;
89    __u8 reserved0[7];
90  };
91  struct hns_roce_ib_alloc_ucontext {
92    __u32 config;
93    __u32 reserved;
94  };
95  struct hns_roce_ib_alloc_pd_resp {
96    __u32 pdn;
97  };
98  struct hns_roce_ib_create_ah_resp {
99    __u8 dmac[6];
100    __u8 reserved[2];
101  };
102  #endif
103