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Searched refs:reg (Results 1 – 25 of 80) sorted by relevance

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/frameworks/libs/binary_translation/backend/common/
Dmachine_ir_test.cc26 MachineReg reg; in TEST() local
27 EXPECT_EQ(reg, kInvalidMachineReg); in TEST()
39 MachineReg reg; in TEST() local
40 EXPECT_FALSE(reg.IsVReg()); in TEST()
41 EXPECT_FALSE(reg.IsSpilledReg()); in TEST()
42 EXPECT_FALSE(reg.IsHardReg()); in TEST()
46 MachineReg reg = MachineReg::CreateVRegFromIndex(43); in TEST() local
47 ASSERT_TRUE(reg.IsVReg()); in TEST()
48 EXPECT_EQ(reg.GetVRegIndex(), 43U); in TEST()
49 EXPECT_FALSE(reg.IsSpilledReg()); in TEST()
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/frameworks/libs/binary_translation/backend/x86_64/
Drename_vregs_local.cc31 [[nodiscard]] MachineReg Get(MachineReg reg) const { return vreg_set_[reg.GetVRegIndex()]; } in Get()
33 [[nodiscard]] bool WasRenamed(MachineReg reg) const { in WasRenamed()
34 return vreg_set_[reg.GetVRegIndex()] != kInvalidMachineReg && in WasRenamed()
35 vreg_set_[reg.GetVRegIndex()] != reg; in WasRenamed()
38 bool WasSeen(MachineReg reg) { return vreg_set_[reg.GetVRegIndex()] != kInvalidMachineReg; } in WasSeen() argument
56 MachineReg reg = insn->RegAt(operand_index); in TryRenameRegOperand() local
58 if (!reg.IsVReg()) { in TryRenameRegOperand()
63 if (!vreg_map.WasSeen(reg)) { in TryRenameRegOperand()
64 vreg_map.Set(reg, reg); in TryRenameRegOperand()
72 insn_list.insert(insn_it, machine_ir->NewInsn<MovqRegReg>(new_reg, vreg_map.Get(reg))); in TryRenameRegOperand()
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Drename_copy_uses.cc24 MachineReg RenameCopyUsesMap::Get(MachineReg reg) { in Get() argument
25 MachineReg renamed = RenameDataForReg(reg).renamed; in Get()
29 if (RenameDataForReg(renamed).last_def_time > RenameDataForReg(reg).renaming_time) { in Get()
42 MachineReg reg = insn->RegAt(i); in RenameUseIfMapped() local
43 if (!reg.IsVReg()) { in RenameUseIfMapped()
47 MachineReg mapped = Get(reg); in RenameUseIfMapped()
54 MachineReg reg = insn->RegAt(i); in ProcessDef() local
56 if (!reg.IsVReg()) { in ProcessDef()
60 RenameDataForReg(reg) = {kInvalidMachineReg, 0, time_}; in ProcessDef()
Drename_vregs.cc30 auto reg = insn->RegAt(i); in AssignNewVRegs() local
31 if (reg.IsVReg()) { in AssignNewVRegs()
32 insn->SetRegAt(i, Get(reg, bb)); in AssignNewVRegs()
33 auto& max_size = max_size_.at(reg.GetVRegIndex()); in AssignNewVRegs()
41 MachineReg VRegMap::Get(MachineReg reg, const MachineBasicBlock* bb) { in Get() argument
42 CHECK(reg.IsVReg()); in Get()
43 MachineReg& mapped_reg = map_.at(bb->id()).at(reg.GetVRegIndex()); in Get()
Dloop_guest_context_optimizer.cc55 auto reg = ir->AllocVReg(); in ReplaceGetAndUpdateMap() local
56 mem_reg_map[disp] = {reg, regtype, false}; in ReplaceGetAndUpdateMap()
61 auto* new_insn = ir->NewInsn<PseudoCopy>(dst, mem_reg_map[disp].value().reg, copy_size); in ReplaceGetAndUpdateMap()
90 auto reg = ir->AllocVReg(); in ReplacePutAndUpdateMap() local
91 mem_reg_map[disp] = {reg, regtype, true}; in ReplacePutAndUpdateMap()
99 ir->NewInsn<PseudoCopy>(mem_reg_map[disp].value().reg, src, copy_size)); in ReplacePutAndUpdateMap()
124 get_insn = ir->NewInsn<MovqRegMemBaseDisp>(reg_info.reg, kMachineRegRBP, disp); in GenerateGetInsns()
127 get_insn = ir->NewInsn<MovdqaXRegMemBaseDisp>(reg_info.reg, kMachineRegRBP, disp); in GenerateGetInsns()
130 get_insn = ir->NewInsn<MovwRegMemBaseDisp>(reg_info.reg, kMachineRegRBP, disp); in GenerateGetInsns()
133 get_insn = ir->NewInsn<MovsdXRegMemBaseDisp>(reg_info.reg, kMachineRegRBP, disp); in GenerateGetInsns()
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Dcontext_liveness_analyzer_test.cc39 for (auto reg : dead_guest_regs) { in CheckBBLiveIn() local
40 CHECK_LE(reg, kNumGuestRegs); in CheckBBLiveIn()
43 for (unsigned int reg = 0; reg < kNumGuestRegs; reg++) { in CheckBBLiveIn() local
44 if (Contains(dead_guest_regs, reg)) { in CheckBBLiveIn()
45 EXPECT_FALSE(analyzer->IsLiveIn(bb, offsetof(ProcessState, cpu.x[reg]))); in CheckBBLiveIn()
47 EXPECT_TRUE(analyzer->IsLiveIn(bb, offsetof(ProcessState, cpu.x[reg]))); in CheckBBLiveIn()
Dmachine_ir_opt.cc40 void Set(MachineReg reg) { in Set() argument
41 if (reg.IsVReg()) { in Set()
42 reg_set_.Set(reg); in Set()
46 void Reset(MachineReg reg) { in Reset() argument
47 if (reg.IsVReg()) { in Reset()
48 reg_set_.Reset(reg); in Reset()
52 bool operator[](MachineReg reg) const { in operator []()
53 if (reg.IsVReg()) { in operator []()
54 return reg_set_[reg]; in operator []()
/frameworks/native/opengl/tools/glgen2/
Dglgen.py30 import reg
115 class TrampolineGen(reg.OutputGenerator):
117 reg.OutputGenerator.__init__(self, sys.stderr, sys.stderr, None)
122 reg.OutputGenerator.genCmd(self, cmd, name)
140 class ApiGenerator(reg.OutputGenerator):
142 reg.OutputGenerator.__init__(self, sys.stderr, sys.stderr, None)
149 reg.OutputGenerator.genCmd(self, cmd, name)
155 reg.OutputGenerator.genEnum(self, enuminfo, name)
211 class SpecGenerator(reg.OutputGenerator):
213 reg.OutputGenerator.__init__(self, sys.stderr, sys.stderr, None)
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/frameworks/libs/binary_translation/lite_translator/riscv64_to_x86_64/
Dlite_translator.h177 Register GetReg(uint8_t reg) { in GetReg() argument
178 CHECK_GT(reg, 0); in GetReg()
179 CHECK_LT(reg, std::size(ThreadState{}.cpu.x)); in GetReg()
181 auto [mapped_reg, is_new_mapping] = GetMappedRegisterOrMap(reg); in GetReg()
183 int32_t offset = offsetof(ThreadState, cpu.x[0]) + reg * 8; in GetReg()
189 int32_t offset = offsetof(ThreadState, cpu.x[0]) + reg * 8; in GetReg()
194 void SetReg(uint8_t reg, Register value) { in SetReg() argument
195 CHECK_GT(reg, 0); in SetReg()
196 CHECK_LT(reg, std::size(ThreadState{}.cpu.x)); in SetReg()
197 CHECK_LE(reg, kNumGuestRegs); in SetReg()
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Dlite_translator_tests.cc87 LiteTranslator::FpRegister reg; in TEST() local
90 translator.StoreFpReg(reg, offset); in TEST()
94 translator.MoveFpReg(reg, reg); in TEST()
98 translator.NanBoxFpReg<LiteTranslator::Float32>(reg); in TEST()
104 translator.NanBoxAndSetFpReg<LiteTranslator::Float32>(1, reg); in TEST()
108 translator.NanBoxAndSetFpReg<LiteTranslator::Float32>(1, reg); in TEST()
115 LiteTranslator::Register reg; in TEST() local
118 translator.as()->Movq({.base = translator.as()->rbp, .disp = offset}, reg); in TEST()
122 translator.as()->Movq(reg, reg); in TEST()
128 translator.SetReg(1, reg); in TEST()
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Dcall_intrinsic.h55 for (auto reg : kCallerSavedRegs) { variable
56 regs_on_stack[reg.num] = stack_allocation_size;
90 for (auto reg : kCallerSavedXMMRegs) { variable
91 simd_regs_on_stack[reg.num] = stack_allocation_size;
109 for (auto reg : kCallerSavedRegs) { in PushCallerSaved() local
110 as.Movq({.base = as.rsp, .disp = kRegOffsetsOnStack[reg.num] * 8}, reg); in PushCallerSaved()
113 for (auto reg : kCallerSavedXMMRegs) { in PushCallerSaved() local
114 as.Movdqa({.base = as.rsp, .disp = kSimdRegOffsetsOnStack[reg.num] * 8}, reg); in PushCallerSaved()
122 for (auto reg : kCallerSavedRegs) { in PopCallerSaved() local
123 if (regs_info.regs_on_stack[reg.num] != kRegIsNotOnStack) { in PopCallerSaved()
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Dregister_maintainer.h32 void Map(RegType reg) { reg_ = std::optional<RegType>(reg); } in Map() argument
50 void Map(unsigned i, RegType reg) { in Map() argument
52 arr_[i].Map(reg); in Map()
/frameworks/libs/binary_translation/backend/include/berberis/backend/x86_64/
Dinsn_folding.h32 [[nodiscard]] std::pair<const MachineInsn*, int> Get(MachineReg reg) const { in Get() argument
33 if (!reg.IsVReg()) { in Get()
36 return def_map_.at(reg.GetVRegIndex()); in Get()
38 [[nodiscard]] std::pair<const MachineInsn*, int> Get(MachineReg reg, int use_index) const { in Get() argument
39 if (!reg.IsVReg()) { in Get()
42 auto [def_insn, def_insn_index] = def_map_.at(reg.GetVRegIndex()); in Get()
52 void Set(MachineReg reg, const MachineInsn* insn) { in Set() argument
53 if (reg.IsVReg()) { in Set()
54 def_map_.at(reg.GetVRegIndex()) = std::pair(insn, index_); in Set()
73 bool IsRegImm(MachineReg reg, uint64_t* imm) const;
Dvreg_bit_set.h33 void Set(MachineReg reg) { bit_set_[reg.GetVRegIndex()] = true; } in Set() argument
34 void Reset(MachineReg reg) { bit_set_[reg.GetVRegIndex()] = false; } in Reset() argument
38 bool operator[](MachineReg reg) const { return bit_set_[reg.GetVRegIndex()]; }
Drename_vregs.h41 MachineReg Get(MachineReg reg, const MachineBasicBlock* bb);
42 [[nodiscard]] int GetMaxSize(MachineReg reg) const { return max_size_.at(reg.GetVRegIndex()); } in GetMaxSize() argument
Dmachine_ir.h87 return r.reg() >= kMachineRegR8.reg() && r.reg() <= kMachineRegR15.reg(); in IsGReg()
91 return r.reg() >= kMachineRegXMM0.reg() && r.reg() <= kMachineRegXMM15.reg(); in IsXReg()
236 MachineReg reg; member
Drename_copy_uses.h47 MachineReg Get(MachineReg reg);
48 RenameData& RenameDataForReg(MachineReg reg) { return map_.at(reg.GetVRegIndex()); } in RenameDataForReg() argument
/frameworks/native/libs/ui/include_private/ui/
DRegionHelper.h178 static inline void advance(region& reg, TYPE& aTop, TYPE& aBottom) { in advance() argument
180 size_t count = reg.count; in advance()
181 RECT const* rects = reg.rects; in advance()
189 aTop = rects->top + reg.dy; in advance()
190 aBottom = rects->bottom + reg.dy; in advance()
195 reg.rects = rects; in advance()
196 reg.count = count; in advance()
252 static inline void advance(region& reg, TYPE& left, TYPE& right) { in advance() argument
253 if (reg.rects && reg.count) { in advance()
254 const int cur_span_top = reg.rects->top; in advance()
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/frameworks/base/services/core/java/com/android/server/am/
DUidObserverController.java124 var reg = (UidObserverRegistration) mUidObservers.getBroadcastCookie(i); in addUidToObserverImpl() local
125 if (reg.getToken().equals(observerToken)) { in addUidToObserverImpl()
126 reg.addUid(uid); in addUidToObserverImpl()
153 var reg = (UidObserverRegistration) mUidObservers.getBroadcastCookie(i); in removeUidFromObserverImpl() local
154 if (reg.getToken().equals(observerToken)) { in removeUidFromObserverImpl()
155 reg.removeUid(uid); in removeUidFromObserverImpl()
319 @NonNull UidObserverRegistration reg, int changesSize) { in dispatchUidsChangedForObserver() argument
329 if (!reg.isWatchingUid(item.uid)) { in dispatchUidsChangedForObserver()
333 if (UserHandle.getUserId(item.uid) != UserHandle.getUserId(reg.mUid) in dispatchUidsChangedForObserver()
334 && !reg.mCanInteractAcrossUsers) { in dispatchUidsChangedForObserver()
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/frameworks/libs/binary_translation/intrinsics/include/berberis/intrinsics/
Dsimd_register.h39 [[nodiscard]] constexpr T SIMD128RegisterGet(const SIMD128Register* reg, int index) = delete;
41 constexpr T SIMD128RegisterSet(SIMD128Register* reg, T elem, int index) = delete;
221 friend constexpr T SIMD128RegisterGet(const SIMD128Register* reg, int index);
223 friend constexpr T SIMD128RegisterSet(SIMD128Register* reg, T elem, int index);
250 inline TYPE SIMD128RegisterGet<TYPE>(const SIMD128Register* reg, int index) { \
251 CHECK_LT(unsigned(index), sizeof(*reg) / sizeof(TYPE)); \
252 return reg->MEMBER[index]; \
255 inline TYPE SIMD128RegisterSet<TYPE>(SIMD128Register * reg, TYPE elem, int index) { \
256 CHECK_LT(unsigned(index), sizeof(*reg) / sizeof(TYPE)); \
257 return reg->MEMBER[index] = elem; \
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/frameworks/base/core/java/android/os/
DBroadcaster.java65 Registration reg = new Registration(); in request() local
66 reg.senderWhat = senderWhat; in request()
67 reg.targets = new Handler[1]; in request()
68 reg.targetWhats = new int[1]; in request()
69 reg.next = r; in request()
70 reg.prev = r.prev; in request()
71 r.prev.next = reg; in request()
72 r.prev = reg; in request()
74 if (r == mReg && r.senderWhat > reg.senderWhat) { in request()
75 mReg = reg; in request()
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/frameworks/libs/binary_translation/backend/testing/include/x86_64/
Dloop_guest_context_optimizer_test_checks.h48 EXPECT_EQ(mem_reg_map[offset].value().reg, mapped_reg); in CheckMemRegMap()
53 inline void CheckGetInsn(MachineInsn* insn, MachineOpcode opcode, MachineReg reg, size_t disp) { in CheckGetInsn() argument
57 EXPECT_EQ(get_insn->RegAt(0), reg); in CheckGetInsn()
61 inline void CheckPutInsn(MachineInsn* insn, MachineOpcode opcode, MachineReg reg, size_t disp) { in CheckPutInsn() argument
65 EXPECT_EQ(put_insn->RegAt(1), reg); in CheckPutInsn()
/frameworks/libs/binary_translation/assembler/include/berberis/assembler/
Dx86_32.h202 static bool IsAccumulator(Register reg) { return reg == eax; } in IsAccumulator() argument
292 void EmitIndexDispOperand(int reg, const Operand& addr);
312 int reg = number << 3; in EmitOperandOp() local
322 EmitBaseIndexDispOperand<uint8_t, &Assembler::Emit8>(addr.base.num | reg, addr); in EmitOperandOp()
324 Emit8(0x05 | reg); in EmitOperandOp()
330 EmitBaseIndexDispOperand<int16_t, &Assembler::Emit16>(0x2004 | (addr.base.num << 8) | reg, in EmitOperandOp()
333 EmitIndexDispOperand(reg, addr); in EmitOperandOp()
336 0x04 | (addr.scale << 14) | (addr.index.num << 11) | (addr.base.num << 8) | reg, addr); in EmitOperandOp()
340 inline void Assembler::EmitIndexDispOperand(int reg, const Operand& addr) { in EmitIndexDispOperand() argument
342 Emit16(0x0504 | (addr.scale << 14) | (addr.index.num << 11) | reg); in EmitIndexDispOperand()
Dcommon_x86.h86 constexpr bool operator==(const Register& reg) const { return num == reg.num; }
88 constexpr bool operator!=(const Register& reg) const { return num != reg.num; }
99 constexpr bool operator==(const Register& reg) const { return num == reg.num; }
101 constexpr bool operator!=(const Register& reg) const { return num != reg.num; }
122 constexpr bool operator==(const XMMRegister& reg) const { return num == reg.num; }
124 constexpr bool operator!=(const XMMRegister& reg) const { return num != reg.num; }
261 explicit constexpr Register8Bit(Register reg) : num(reg.num) {} in Register8Bit()
266 explicit constexpr Register32Bit(Register reg) : num(reg.num) {} in Register32Bit()
267 explicit constexpr Register32Bit(XMMRegister reg) : num(reg.num) {} in Register32Bit()
/frameworks/libs/binary_translation/guest_state/arm64/
Dguest_state_arch.cc64 std::size_t GetThreadStateRegOffset(int reg) { in GetThreadStateRegOffset() argument
65 return offsetof(ThreadState, cpu.x[reg]); in GetThreadStateRegOffset()
73 std::size_t GetThreadStateSimdRegOffset(int reg) { in GetThreadStateSimdRegOffset() argument
74 return offsetof(ThreadState, cpu.v[reg]); in GetThreadStateSimdRegOffset()

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