Searched refs:F_NONE (Results 1 – 3 of 3) sorted by relevance
| /hardware/google/gchips/gralloc4/src/core/ |
| D | format_info.cpp | 130 … .dpu_rd = F_LIN|F_AFBC, .dpu_wr = F_NONE, .dpu_aeu_wr = F_AFBC, .vpu_rd = F_NONE, .vpu_wr = F_NON…
131 …F_LIN|F_AFBC, .dpu_wr = F_LIN, .dpu_aeu_wr = F_AFBC, .vpu_rd = F_NONE, .vpu_wr = F_NONE, .cam_wr …
132 …FBC, .dpu_wr = F_LIN, .dpu_aeu_wr = F_AFBC, .vpu_rd = F_LIN, .vpu_wr = F_NONE, .cam_wr = F_LIN, …
133 …F_LIN, .dpu_wr = F_LIN, .dpu_aeu_wr = F_NONE, .vpu_rd = F_LIN, .vpu_wr = F_NONE, .cam_wr …
134 …F_LIN|F_AFBC, .dpu_wr = F_LIN, .dpu_aeu_wr = F_NONE, .vpu_rd = F_NONE, .vpu_wr = F_NONE, .cam_wr …
135 …, .dpu_wr = F_LIN, .dpu_aeu_wr = F_AFBC, .vpu_rd = F_LIN, .vpu_wr = F_NONE, .cam_wr = F_NONE, },
136 …_LIN|F_AFBC, .dpu_rd = F_NONE, .dpu_wr = F_NONE, .dpu_aeu_wr = F_NONE, .vpu_rd = F_NONE, .vp…
137 …pu_rd = F_NONE, .gpu_wr = F_NONE, .dpu_rd = F_NONE, .dpu_wr = F_NONE, .dpu_aeu_w…
138 …F_NONE, .gpu_wr = F_NONE, .dpu_rd = F_NONE, .dpu_wr = F_NONE, .dpu_aeu_wr = F_NO…
140 …F_NONE, .cpu_wr = F_NONE, .gpu_rd = F_AFBC, .gpu_wr = F_NONE, .dpu_rd = F_AFBC, …
[all …]
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| D | format_info.h | 27 #define F_NONE 0 macro
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| D | mali_gralloc_formats.cpp | 637 if (f_flags != F_NONE) in is_format_supported()
643 f_flags = F_NONE; in is_format_supported()
1009 if (fmt_supported->f_flags == F_NONE && in get_supported_format()
1079 return (fmt_supported->f_flags == F_NONE) ? false : true; in get_supported_format()
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