Home
last modified time | relevance | path

Searched refs:UCI_RESPONSE_STATUS_OFFSET (Results 1 – 5 of 5) sorted by relevance

/hardware/nxp/uwb/halimpl/hal/sr1xx/
DNxpUwbChipSr1xx.cc175 uint8_t status = packet[UCI_RESPONSE_STATUS_OFFSET]; in sr1xx_do_bind()
232 if (packet_len >= UCI_RESPONSE_STATUS_OFFSET) { in sr1xx_check_binding_status()
233 binding_status_got = packet[UCI_RESPONSE_STATUS_OFFSET]; in sr1xx_check_binding_status()
301 if(packet_len > UCI_RESPONSE_STATUS_OFFSET) { in onDeviceStatusNtf()
302 uint8_t status = packet[UCI_RESPONSE_STATUS_OFFSET]; in onDeviceStatusNtf()
311 if(packet_len > UCI_RESPONSE_STATUS_OFFSET) { in onGenericErrorNtf()
312 uint8_t status = packet[UCI_RESPONSE_STATUS_OFFSET]; in onGenericErrorNtf()
322 if (packet_len > UCI_RESPONSE_STATUS_OFFSET) { in onBindingStatusNtf()
323 bindingStatus_ = packet[UCI_RESPONSE_STATUS_OFFSET]; in onBindingStatusNtf()
/hardware/nxp/uwb/halimpl/hal/sr200/
DNxpUwbChipSr200.cc49 if (packet_len >= UCI_RESPONSE_STATUS_OFFSET) { in on_binding_status_ntf()
50 bindingStatus_ = packet[UCI_RESPONSE_STATUS_OFFSET]; in on_binding_status_ntf()
/hardware/nxp/uwb/halimpl/hal/
DphNxpUciHal.cc541 uint8_t status_code = nxpucihal_ctrl.p_rx_data[UCI_RESPONSE_STATUS_OFFSET]; in phNxpUciHal_read_complete()
565 uint8_t status_code = (nxpucihal_ctrl.rx_data_len > UCI_RESPONSE_STATUS_OFFSET) ? in phNxpUciHal_read_complete()
566 nxpucihal_ctrl.p_rx_data[UCI_RESPONSE_STATUS_OFFSET] : UCI_STATUS_UNKNOWN; in phNxpUciHal_read_complete()
799 if (packet_len < 5 || packet[UCI_RESPONSE_STATUS_OFFSET] != UWBSTATUS_SUCCESS) { in cacheDevInfoRsp()
887 dev_status = packet[UCI_RESPONSE_STATUS_OFFSET]; in phNxpUciHal_init_hw()
DphNxpUciHal_ext.cc937 uint8_t status = p_data[UCI_RESPONSE_STATUS_OFFSET]; in phNxpUciHal_handle_get_caps_info()
1010 packet[UCI_RESPONSE_STATUS_OFFSET] = UWBSTATUS_SUCCESS; in phNxpUciHal_handle_get_caps_info()
/hardware/nxp/uwb/extns/inc/
Duci_defs.h30 #define UCI_RESPONSE_STATUS_OFFSET 4 macro