/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Target Register Enum Values *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_REGINFO_ENUM #undef GET_REGINFO_ENUM namespace llvm { class MCRegisterClass; extern const MCRegisterClass MipsMCRegisterClasses[]; namespace Mips { enum { NoRegister, AT = 1, DSPCCond = 2, DSPCarry = 3, DSPEFI = 4, DSPOutFlag = 5, DSPPos = 6, DSPSCount = 7, FP = 8, GP = 9, MSAAccess = 10, MSACSR = 11, MSAIR = 12, MSAMap = 13, MSAModify = 14, MSARequest = 15, MSASave = 16, MSAUnmap = 17, PC = 18, RA = 19, SP = 20, ZERO = 21, A0 = 22, A1 = 23, A2 = 24, A3 = 25, AC0 = 26, AC1 = 27, AC2 = 28, AC3 = 29, AT_64 = 30, COP00 = 31, COP01 = 32, COP02 = 33, COP03 = 34, COP04 = 35, COP05 = 36, COP06 = 37, COP07 = 38, COP08 = 39, COP09 = 40, COP20 = 41, COP21 = 42, COP22 = 43, COP23 = 44, COP24 = 45, COP25 = 46, COP26 = 47, COP27 = 48, COP28 = 49, COP29 = 50, COP30 = 51, COP31 = 52, COP32 = 53, COP33 = 54, COP34 = 55, COP35 = 56, COP36 = 57, COP37 = 58, COP38 = 59, COP39 = 60, COP010 = 61, COP011 = 62, COP012 = 63, COP013 = 64, COP014 = 65, COP015 = 66, COP016 = 67, COP017 = 68, COP018 = 69, COP019 = 70, COP020 = 71, COP021 = 72, COP022 = 73, COP023 = 74, COP024 = 75, COP025 = 76, COP026 = 77, COP027 = 78, COP028 = 79, COP029 = 80, COP030 = 81, COP031 = 82, COP210 = 83, COP211 = 84, COP212 = 85, COP213 = 86, COP214 = 87, COP215 = 88, COP216 = 89, COP217 = 90, COP218 = 91, COP219 = 92, COP220 = 93, COP221 = 94, COP222 = 95, COP223 = 96, COP224 = 97, COP225 = 98, COP226 = 99, COP227 = 100, COP228 = 101, COP229 = 102, COP230 = 103, COP231 = 104, COP310 = 105, COP311 = 106, COP312 = 107, COP313 = 108, COP314 = 109, COP315 = 110, COP316 = 111, COP317 = 112, COP318 = 113, COP319 = 114, COP320 = 115, COP321 = 116, COP322 = 117, COP323 = 118, COP324 = 119, COP325 = 120, COP326 = 121, COP327 = 122, COP328 = 123, COP329 = 124, COP330 = 125, COP331 = 126, D0 = 127, D1 = 128, D2 = 129, D3 = 130, D4 = 131, D5 = 132, D6 = 133, D7 = 134, D8 = 135, D9 = 136, D10 = 137, D11 = 138, D12 = 139, D13 = 140, D14 = 141, D15 = 142, DSPOutFlag20 = 143, DSPOutFlag21 = 144, DSPOutFlag22 = 145, DSPOutFlag23 = 146, F0 = 147, F1 = 148, F2 = 149, F3 = 150, F4 = 151, F5 = 152, F6 = 153, F7 = 154, F8 = 155, F9 = 156, F10 = 157, F11 = 158, F12 = 159, F13 = 160, F14 = 161, F15 = 162, F16 = 163, F17 = 164, F18 = 165, F19 = 166, F20 = 167, F21 = 168, F22 = 169, F23 = 170, F24 = 171, F25 = 172, F26 = 173, F27 = 174, F28 = 175, F29 = 176, F30 = 177, F31 = 178, FCC0 = 179, FCC1 = 180, FCC2 = 181, FCC3 = 182, FCC4 = 183, FCC5 = 184, FCC6 = 185, FCC7 = 186, FCR0 = 187, FCR1 = 188, FCR2 = 189, FCR3 = 190, FCR4 = 191, FCR5 = 192, FCR6 = 193, FCR7 = 194, FCR8 = 195, FCR9 = 196, FCR10 = 197, FCR11 = 198, FCR12 = 199, FCR13 = 200, FCR14 = 201, FCR15 = 202, FCR16 = 203, FCR17 = 204, FCR18 = 205, FCR19 = 206, FCR20 = 207, FCR21 = 208, FCR22 = 209, FCR23 = 210, FCR24 = 211, FCR25 = 212, FCR26 = 213, FCR27 = 214, FCR28 = 215, FCR29 = 216, FCR30 = 217, FCR31 = 218, FP_64 = 219, F_HI0 = 220, F_HI1 = 221, F_HI2 = 222, F_HI3 = 223, F_HI4 = 224, F_HI5 = 225, F_HI6 = 226, F_HI7 = 227, F_HI8 = 228, F_HI9 = 229, F_HI10 = 230, F_HI11 = 231, F_HI12 = 232, F_HI13 = 233, F_HI14 = 234, F_HI15 = 235, F_HI16 = 236, F_HI17 = 237, F_HI18 = 238, F_HI19 = 239, F_HI20 = 240, F_HI21 = 241, F_HI22 = 242, F_HI23 = 243, F_HI24 = 244, F_HI25 = 245, F_HI26 = 246, F_HI27 = 247, F_HI28 = 248, F_HI29 = 249, F_HI30 = 250, F_HI31 = 251, GP_64 = 252, HI0 = 253, HI1 = 254, HI2 = 255, HI3 = 256, HWR0 = 257, HWR1 = 258, HWR2 = 259, HWR3 = 260, HWR4 = 261, HWR5 = 262, HWR6 = 263, HWR7 = 264, HWR8 = 265, HWR9 = 266, HWR10 = 267, HWR11 = 268, HWR12 = 269, HWR13 = 270, HWR14 = 271, HWR15 = 272, HWR16 = 273, HWR17 = 274, HWR18 = 275, HWR19 = 276, HWR20 = 277, HWR21 = 278, HWR22 = 279, HWR23 = 280, HWR24 = 281, HWR25 = 282, HWR26 = 283, HWR27 = 284, HWR28 = 285, HWR29 = 286, HWR30 = 287, HWR31 = 288, K0 = 289, K1 = 290, LO0 = 291, LO1 = 292, LO2 = 293, LO3 = 294, MPL0 = 295, MPL1 = 296, MPL2 = 297, MSA8 = 298, MSA9 = 299, MSA10 = 300, MSA11 = 301, MSA12 = 302, MSA13 = 303, MSA14 = 304, MSA15 = 305, MSA16 = 306, MSA17 = 307, MSA18 = 308, MSA19 = 309, MSA20 = 310, MSA21 = 311, MSA22 = 312, MSA23 = 313, MSA24 = 314, MSA25 = 315, MSA26 = 316, MSA27 = 317, MSA28 = 318, MSA29 = 319, MSA30 = 320, MSA31 = 321, P0 = 322, P1 = 323, P2 = 324, RA_64 = 325, S0 = 326, S1 = 327, S2 = 328, S3 = 329, S4 = 330, S5 = 331, S6 = 332, S7 = 333, SP_64 = 334, T0 = 335, T1 = 336, T2 = 337, T3 = 338, T4 = 339, T5 = 340, T6 = 341, T7 = 342, T8 = 343, T9 = 344, V0 = 345, V1 = 346, W0 = 347, W1 = 348, W2 = 349, W3 = 350, W4 = 351, W5 = 352, W6 = 353, W7 = 354, W8 = 355, W9 = 356, W10 = 357, W11 = 358, W12 = 359, W13 = 360, W14 = 361, W15 = 362, W16 = 363, W17 = 364, W18 = 365, W19 = 366, W20 = 367, W21 = 368, W22 = 369, W23 = 370, W24 = 371, W25 = 372, W26 = 373, W27 = 374, W28 = 375, W29 = 376, W30 = 377, W31 = 378, ZERO_64 = 379, A0_64 = 380, A1_64 = 381, A2_64 = 382, A3_64 = 383, AC0_64 = 384, D0_64 = 385, D1_64 = 386, D2_64 = 387, D3_64 = 388, D4_64 = 389, D5_64 = 390, D6_64 = 391, D7_64 = 392, D8_64 = 393, D9_64 = 394, D10_64 = 395, D11_64 = 396, D12_64 = 397, D13_64 = 398, D14_64 = 399, D15_64 = 400, D16_64 = 401, D17_64 = 402, D18_64 = 403, D19_64 = 404, D20_64 = 405, D21_64 = 406, D22_64 = 407, D23_64 = 408, D24_64 = 409, D25_64 = 410, D26_64 = 411, D27_64 = 412, D28_64 = 413, D29_64 = 414, D30_64 = 415, D31_64 = 416, DSPOutFlag16_19 = 417, HI0_64 = 418, K0_64 = 419, K1_64 = 420, LO0_64 = 421, S0_64 = 422, S1_64 = 423, S2_64 = 424, S3_64 = 425, S4_64 = 426, S5_64 = 427, S6_64 = 428, S7_64 = 429, T0_64 = 430, T1_64 = 431, T2_64 = 432, T3_64 = 433, T4_64 = 434, T5_64 = 435, T6_64 = 436, T7_64 = 437, T8_64 = 438, T9_64 = 439, V0_64 = 440, V1_64 = 441, NUM_TARGET_REGS // 442 }; } // end namespace Mips // Register classes namespace Mips { enum { MSA128F16RegClassID = 0, CCRRegClassID = 1, COP0RegClassID = 2, COP2RegClassID = 3, COP3RegClassID = 4, DSPRRegClassID = 5, FGR32RegClassID = 6, FGRCCRegClassID = 7, GPR32RegClassID = 8, HWRegsRegClassID = 9, MSACtrlRegClassID = 10, GPR32NONZERORegClassID = 11, CPU16RegsPlusSPRegClassID = 12, CPU16RegsRegClassID = 13, FCCRegClassID = 14, GPRMM16RegClassID = 15, GPRMM16MovePRegClassID = 16, GPRMM16ZeroRegClassID = 17, CPU16Regs_and_GPRMM16ZeroRegClassID = 18, GPR32NONZERO_and_GPRMM16MovePRegClassID = 19, GPRMM16MovePPairSecondRegClassID = 20, CPU16Regs_and_GPRMM16MovePRegClassID = 21, GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 22, HI32DSPRegClassID = 23, LO32DSPRegClassID = 24, CPU16Regs_and_GPRMM16MovePPairSecondRegClassID = 25, GPRMM16MovePPairFirstRegClassID = 26, GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 27, GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID = 28, CPURARegRegClassID = 29, CPUSPRegRegClassID = 30, DSPCCRegClassID = 31, GP32RegClassID = 32, GPR32ZERORegClassID = 33, HI32RegClassID = 34, LO32RegClassID = 35, SP32RegClassID = 36, FGR64RegClassID = 37, GPR64RegClassID = 38, GPR64_with_sub_32_in_GPR32NONZERORegClassID = 39, AFGR64RegClassID = 40, GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID = 41, GPR64_with_sub_32_in_CPU16RegsRegClassID = 42, GPR64_with_sub_32_in_GPRMM16MovePRegClassID = 43, GPR64_with_sub_32_in_GPRMM16ZeroRegClassID = 44, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID = 45, GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID = 46, GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID = 47, ACC64DSPRegClassID = 48, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID = 49, GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 50, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID = 51, GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID = 52, GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 53, OCTEON_MPLRegClassID = 54, OCTEON_PRegClassID = 55, GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID = 56, ACC64RegClassID = 57, GP64RegClassID = 58, GPR64_with_sub_32_in_CPURARegRegClassID = 59, GPR64_with_sub_32_in_GPR32ZERORegClassID = 60, HI64RegClassID = 61, LO64RegClassID = 62, SP64RegClassID = 63, MSA128BRegClassID = 64, MSA128DRegClassID = 65, MSA128HRegClassID = 66, MSA128WRegClassID = 67, MSA128WEvensRegClassID = 68, ACC128RegClassID = 69, }; } // end namespace Mips // Subregister indices namespace Mips { enum { NoSubRegister, sub_32, // 1 sub_64, // 2 sub_dsp16_19, // 3 sub_dsp20, // 4 sub_dsp21, // 5 sub_dsp22, // 6 sub_dsp23, // 7 sub_hi, // 8 sub_lo, // 9 sub_hi_then_sub_32, // 10 sub_32_sub_hi_then_sub_32, // 11 NUM_TARGET_SUBREGS }; } // end namespace Mips } // end namespace llvm #endif // GET_REGINFO_ENUM /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* MC Register Information *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_REGINFO_MC_DESC #undef GET_REGINFO_MC_DESC namespace llvm { extern const MCPhysReg MipsRegDiffLists[] = { /* 0 */ 0, 0, /* 2 */ 4, 1, 1, 1, 1, 0, /* 8 */ 412, 65262, 1, 1, 1, 0, /* 14 */ 20, 1, 0, /* 17 */ 21, 1, 0, /* 20 */ 22, 1, 0, /* 23 */ 23, 1, 0, /* 26 */ 24, 1, 0, /* 29 */ 25, 1, 0, /* 32 */ 26, 1, 0, /* 35 */ 27, 1, 0, /* 38 */ 28, 1, 0, /* 41 */ 29, 1, 0, /* 44 */ 30, 1, 0, /* 47 */ 31, 1, 0, /* 50 */ 32, 1, 0, /* 53 */ 33, 1, 0, /* 56 */ 34, 1, 0, /* 59 */ 35, 1, 0, /* 62 */ 65415, 1, 0, /* 65 */ 65513, 1, 0, /* 68 */ 3, 0, /* 70 */ 4, 0, /* 72 */ 6, 0, /* 74 */ 11, 0, /* 76 */ 12, 0, /* 78 */ 22, 0, /* 80 */ 23, 0, /* 82 */ 29, 0, /* 84 */ 30, 0, /* 86 */ 65284, 72, 0, /* 89 */ 65322, 72, 0, /* 92 */ 38, 65298, 73, 0, /* 96 */ 95, 0, /* 98 */ 96, 0, /* 100 */ 130, 0, /* 102 */ 211, 0, /* 104 */ 243, 0, /* 106 */ 306, 0, /* 108 */ 314, 0, /* 110 */ 358, 0, /* 112 */ 64983, 0, /* 114 */ 65060, 0, /* 116 */ 65124, 0, /* 118 */ 65178, 0, /* 120 */ 65181, 0, /* 122 */ 65222, 0, /* 124 */ 65230, 0, /* 126 */ 65271, 0, /* 128 */ 65293, 0, /* 130 */ 37, 65406, 127, 65371, 65309, 0, /* 136 */ 65325, 0, /* 138 */ 65371, 0, /* 140 */ 65386, 0, /* 142 */ 65395, 0, /* 144 */ 65396, 0, /* 146 */ 65397, 0, /* 148 */ 65398, 0, /* 150 */ 65406, 0, /* 152 */ 65415, 0, /* 154 */ 65440, 0, /* 156 */ 65441, 0, /* 158 */ 165, 65498, 0, /* 161 */ 65516, 258, 65498, 0, /* 165 */ 65515, 259, 65498, 0, /* 169 */ 65514, 260, 65498, 0, /* 173 */ 65513, 261, 65498, 0, /* 177 */ 65512, 262, 65498, 0, /* 181 */ 65511, 263, 65498, 0, /* 185 */ 65510, 264, 65498, 0, /* 189 */ 65509, 265, 65498, 0, /* 193 */ 65508, 266, 65498, 0, /* 197 */ 65507, 267, 65498, 0, /* 201 */ 65506, 268, 65498, 0, /* 205 */ 65505, 269, 65498, 0, /* 209 */ 65504, 270, 65498, 0, /* 213 */ 65503, 271, 65498, 0, /* 217 */ 65502, 272, 65498, 0, /* 221 */ 65501, 273, 65498, 0, /* 225 */ 65500, 274, 65498, 0, /* 229 */ 65271, 395, 65499, 0, /* 233 */ 65309, 392, 65502, 0, /* 237 */ 65507, 0, /* 239 */ 65510, 0, /* 241 */ 65511, 0, /* 243 */ 65512, 0, /* 245 */ 65516, 0, /* 247 */ 65521, 0, /* 249 */ 65522, 0, /* 251 */ 65535, 0, }; extern const LaneBitmask MipsLaneMaskLists[] = { /* 0 */ LaneBitmask(0x00000000), LaneBitmask::getAll(), /* 2 */ LaneBitmask(0x00000001), LaneBitmask::getAll(), /* 4 */ LaneBitmask(0x00000002), LaneBitmask(0x00000004), LaneBitmask(0x00000008), LaneBitmask(0x00000010), LaneBitmask(0x00000020), LaneBitmask::getAll(), /* 10 */ LaneBitmask(0x00000001), LaneBitmask(0x00000040), LaneBitmask::getAll(), }; extern const uint16_t MipsSubRegIdxLists[] = { /* 0 */ 1, 0, /* 2 */ 3, 4, 5, 6, 7, 0, /* 8 */ 2, 9, 8, 0, /* 12 */ 9, 1, 8, 10, 11, 0, }; extern const MCRegisterInfo::SubRegCoveredBits MipsSubRegIdxRanges[] = { { 65535, 65535 }, { 0, 32 }, // sub_32 { 0, 64 }, // sub_64 { 16, 4 }, // sub_dsp16_19 { 20, 1 }, // sub_dsp20 { 21, 1 }, // sub_dsp21 { 22, 1 }, // sub_dsp22 { 23, 1 }, // sub_dsp23 { 32, 32 }, // sub_hi { 0, 32 }, // sub_lo { 32, 32 }, // sub_hi_then_sub_32 { 0, 64 }, // sub_32_sub_hi_then_sub_32 }; extern const char MipsRegStrings[] = { /* 0 */ 'C', 'O', 'P', '0', '0', 0, /* 6 */ 'C', 'O', 'P', '0', '1', '0', 0, /* 13 */ 'C', 'O', 'P', '2', '1', '0', 0, /* 20 */ 'C', 'O', 'P', '3', '1', '0', 0, /* 27 */ 'M', 'S', 'A', '1', '0', 0, /* 33 */ 'D', '1', '0', 0, /* 37 */ 'F', '1', '0', 0, /* 41 */ 'F', '_', 'H', 'I', '1', '0', 0, /* 48 */ 'F', 'C', 'R', '1', '0', 0, /* 54 */ 'H', 'W', 'R', '1', '0', 0, /* 60 */ 'W', '1', '0', 0, /* 64 */ 'C', 'O', 'P', '0', '2', '0', 0, /* 71 */ 'C', 'O', 'P', '2', '2', '0', 0, /* 78 */ 'C', 'O', 'P', '3', '2', '0', 0, /* 85 */ 'M', 'S', 'A', '2', '0', 0, /* 91 */ 'F', '2', '0', 0, /* 95 */ 'F', '_', 'H', 'I', '2', '0', 0, /* 102 */ 'C', 'O', 'P', '2', '0', 0, /* 108 */ 'F', 'C', 'R', '2', '0', 0, /* 114 */ 'H', 'W', 'R', '2', '0', 0, /* 120 */ 'W', '2', '0', 0, /* 124 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '0', 0, /* 137 */ 'C', 'O', 'P', '0', '3', '0', 0, /* 144 */ 'C', 'O', 'P', '2', '3', '0', 0, /* 151 */ 'C', 'O', 'P', '3', '3', '0', 0, /* 158 */ 'M', 'S', 'A', '3', '0', 0, /* 164 */ 'F', '3', '0', 0, /* 168 */ 'F', '_', 'H', 'I', '3', '0', 0, /* 175 */ 'C', 'O', 'P', '3', '0', 0, /* 181 */ 'F', 'C', 'R', '3', '0', 0, /* 187 */ 'H', 'W', 'R', '3', '0', 0, /* 193 */ 'W', '3', '0', 0, /* 197 */ 'A', '0', 0, /* 200 */ 'A', 'C', '0', 0, /* 204 */ 'F', 'C', 'C', '0', 0, /* 209 */ 'D', '0', 0, /* 212 */ 'F', '0', 0, /* 215 */ 'F', '_', 'H', 'I', '0', 0, /* 221 */ 'K', '0', 0, /* 224 */ 'M', 'P', 'L', '0', 0, /* 229 */ 'L', 'O', '0', 0, /* 233 */ 'P', '0', 0, /* 236 */ 'F', 'C', 'R', '0', 0, /* 241 */ 'H', 'W', 'R', '0', 0, /* 246 */ 'S', '0', 0, /* 249 */ 'T', '0', 0, /* 252 */ 'V', '0', 0, /* 255 */ 'W', '0', 0, /* 258 */ 'C', 'O', 'P', '0', '1', 0, /* 264 */ 'C', 'O', 'P', '0', '1', '1', 0, /* 271 */ 'C', 'O', 'P', '2', '1', '1', 0, /* 278 */ 'C', 'O', 'P', '3', '1', '1', 0, /* 285 */ 'M', 'S', 'A', '1', '1', 0, /* 291 */ 'D', '1', '1', 0, /* 295 */ 'F', '1', '1', 0, /* 299 */ 'F', '_', 'H', 'I', '1', '1', 0, /* 306 */ 'F', 'C', 'R', '1', '1', 0, /* 312 */ 'H', 'W', 'R', '1', '1', 0, /* 318 */ 'W', '1', '1', 0, /* 322 */ 'C', 'O', 'P', '0', '2', '1', 0, /* 329 */ 'C', 'O', 'P', '2', '2', '1', 0, /* 336 */ 'C', 'O', 'P', '3', '2', '1', 0, /* 343 */ 'M', 'S', 'A', '2', '1', 0, /* 349 */ 'F', '2', '1', 0, /* 353 */ 'F', '_', 'H', 'I', '2', '1', 0, /* 360 */ 'C', 'O', 'P', '2', '1', 0, /* 366 */ 'F', 'C', 'R', '2', '1', 0, /* 372 */ 'H', 'W', 'R', '2', '1', 0, /* 378 */ 'W', '2', '1', 0, /* 382 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '1', 0, /* 395 */ 'C', 'O', 'P', '0', '3', '1', 0, /* 402 */ 'C', 'O', 'P', '2', '3', '1', 0, /* 409 */ 'C', 'O', 'P', '3', '3', '1', 0, /* 416 */ 'M', 'S', 'A', '3', '1', 0, /* 422 */ 'F', '3', '1', 0, /* 426 */ 'F', '_', 'H', 'I', '3', '1', 0, /* 433 */ 'C', 'O', 'P', '3', '1', 0, /* 439 */ 'F', 'C', 'R', '3', '1', 0, /* 445 */ 'H', 'W', 'R', '3', '1', 0, /* 451 */ 'W', '3', '1', 0, /* 455 */ 'A', '1', 0, /* 458 */ 'A', 'C', '1', 0, /* 462 */ 'F', 'C', 'C', '1', 0, /* 467 */ 'D', '1', 0, /* 470 */ 'F', '1', 0, /* 473 */ 'F', '_', 'H', 'I', '1', 0, /* 479 */ 'K', '1', 0, /* 482 */ 'M', 'P', 'L', '1', 0, /* 487 */ 'L', 'O', '1', 0, /* 491 */ 'P', '1', 0, /* 494 */ 'F', 'C', 'R', '1', 0, /* 499 */ 'H', 'W', 'R', '1', 0, /* 504 */ 'S', '1', 0, /* 507 */ 'T', '1', 0, /* 510 */ 'V', '1', 0, /* 513 */ 'W', '1', 0, /* 516 */ 'C', 'O', 'P', '0', '2', 0, /* 522 */ 'C', 'O', 'P', '0', '1', '2', 0, /* 529 */ 'C', 'O', 'P', '2', '1', '2', 0, /* 536 */ 'C', 'O', 'P', '3', '1', '2', 0, /* 543 */ 'M', 'S', 'A', '1', '2', 0, /* 549 */ 'D', '1', '2', 0, /* 553 */ 'F', '1', '2', 0, /* 557 */ 'F', '_', 'H', 'I', '1', '2', 0, /* 564 */ 'F', 'C', 'R', '1', '2', 0, /* 570 */ 'H', 'W', 'R', '1', '2', 0, /* 576 */ 'W', '1', '2', 0, /* 580 */ 'C', 'O', 'P', '0', '2', '2', 0, /* 587 */ 'C', 'O', 'P', '2', '2', '2', 0, /* 594 */ 'C', 'O', 'P', '3', '2', '2', 0, /* 601 */ 'M', 'S', 'A', '2', '2', 0, /* 607 */ 'F', '2', '2', 0, /* 611 */ 'F', '_', 'H', 'I', '2', '2', 0, /* 618 */ 'C', 'O', 'P', '2', '2', 0, /* 624 */ 'F', 'C', 'R', '2', '2', 0, /* 630 */ 'H', 'W', 'R', '2', '2', 0, /* 636 */ 'W', '2', '2', 0, /* 640 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '2', 0, /* 653 */ 'C', 'O', 'P', '3', '2', 0, /* 659 */ 'A', '2', 0, /* 662 */ 'A', 'C', '2', 0, /* 666 */ 'F', 'C', 'C', '2', 0, /* 671 */ 'D', '2', 0, /* 674 */ 'F', '2', 0, /* 677 */ 'F', '_', 'H', 'I', '2', 0, /* 683 */ 'M', 'P', 'L', '2', 0, /* 688 */ 'L', 'O', '2', 0, /* 692 */ 'P', '2', 0, /* 695 */ 'F', 'C', 'R', '2', 0, /* 700 */ 'H', 'W', 'R', '2', 0, /* 705 */ 'S', '2', 0, /* 708 */ 'T', '2', 0, /* 711 */ 'W', '2', 0, /* 714 */ 'C', 'O', 'P', '0', '3', 0, /* 720 */ 'C', 'O', 'P', '0', '1', '3', 0, /* 727 */ 'C', 'O', 'P', '2', '1', '3', 0, /* 734 */ 'C', 'O', 'P', '3', '1', '3', 0, /* 741 */ 'M', 'S', 'A', '1', '3', 0, /* 747 */ 'D', '1', '3', 0, /* 751 */ 'F', '1', '3', 0, /* 755 */ 'F', '_', 'H', 'I', '1', '3', 0, /* 762 */ 'F', 'C', 'R', '1', '3', 0, /* 768 */ 'H', 'W', 'R', '1', '3', 0, /* 774 */ 'W', '1', '3', 0, /* 778 */ 'C', 'O', 'P', '0', '2', '3', 0, /* 785 */ 'C', 'O', 'P', '2', '2', '3', 0, /* 792 */ 'C', 'O', 'P', '3', '2', '3', 0, /* 799 */ 'M', 'S', 'A', '2', '3', 0, /* 805 */ 'F', '2', '3', 0, /* 809 */ 'F', '_', 'H', 'I', '2', '3', 0, /* 816 */ 'C', 'O', 'P', '2', '3', 0, /* 822 */ 'F', 'C', 'R', '2', '3', 0, /* 828 */ 'H', 'W', 'R', '2', '3', 0, /* 834 */ 'W', '2', '3', 0, /* 838 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '2', '3', 0, /* 851 */ 'C', 'O', 'P', '3', '3', 0, /* 857 */ 'A', '3', 0, /* 860 */ 'A', 'C', '3', 0, /* 864 */ 'F', 'C', 'C', '3', 0, /* 869 */ 'D', '3', 0, /* 872 */ 'F', '3', 0, /* 875 */ 'F', '_', 'H', 'I', '3', 0, /* 881 */ 'L', 'O', '3', 0, /* 885 */ 'F', 'C', 'R', '3', 0, /* 890 */ 'H', 'W', 'R', '3', 0, /* 895 */ 'S', '3', 0, /* 898 */ 'T', '3', 0, /* 901 */ 'W', '3', 0, /* 904 */ 'C', 'O', 'P', '0', '4', 0, /* 910 */ 'C', 'O', 'P', '0', '1', '4', 0, /* 917 */ 'C', 'O', 'P', '2', '1', '4', 0, /* 924 */ 'C', 'O', 'P', '3', '1', '4', 0, /* 931 */ 'M', 'S', 'A', '1', '4', 0, /* 937 */ 'D', '1', '4', 0, /* 941 */ 'F', '1', '4', 0, /* 945 */ 'F', '_', 'H', 'I', '1', '4', 0, /* 952 */ 'F', 'C', 'R', '1', '4', 0, /* 958 */ 'H', 'W', 'R', '1', '4', 0, /* 964 */ 'W', '1', '4', 0, /* 968 */ 'C', 'O', 'P', '0', '2', '4', 0, /* 975 */ 'C', 'O', 'P', '2', '2', '4', 0, /* 982 */ 'C', 'O', 'P', '3', '2', '4', 0, /* 989 */ 'M', 'S', 'A', '2', '4', 0, /* 995 */ 'F', '2', '4', 0, /* 999 */ 'F', '_', 'H', 'I', '2', '4', 0, /* 1006 */ 'C', 'O', 'P', '2', '4', 0, /* 1012 */ 'F', 'C', 'R', '2', '4', 0, /* 1018 */ 'H', 'W', 'R', '2', '4', 0, /* 1024 */ 'W', '2', '4', 0, /* 1028 */ 'C', 'O', 'P', '3', '4', 0, /* 1034 */ 'D', '1', '0', '_', '6', '4', 0, /* 1041 */ 'D', '2', '0', '_', '6', '4', 0, /* 1048 */ 'D', '3', '0', '_', '6', '4', 0, /* 1055 */ 'A', '0', '_', '6', '4', 0, /* 1061 */ 'A', 'C', '0', '_', '6', '4', 0, /* 1068 */ 'D', '0', '_', '6', '4', 0, /* 1074 */ 'H', 'I', '0', '_', '6', '4', 0, /* 1081 */ 'K', '0', '_', '6', '4', 0, /* 1087 */ 'L', 'O', '0', '_', '6', '4', 0, /* 1094 */ 'S', '0', '_', '6', '4', 0, /* 1100 */ 'T', '0', '_', '6', '4', 0, /* 1106 */ 'V', '0', '_', '6', '4', 0, /* 1112 */ 'D', '1', '1', '_', '6', '4', 0, /* 1119 */ 'D', '2', '1', '_', '6', '4', 0, /* 1126 */ 'D', '3', '1', '_', '6', '4', 0, /* 1133 */ 'A', '1', '_', '6', '4', 0, /* 1139 */ 'D', '1', '_', '6', '4', 0, /* 1145 */ 'K', '1', '_', '6', '4', 0, /* 1151 */ 'S', '1', '_', '6', '4', 0, /* 1157 */ 'T', '1', '_', '6', '4', 0, /* 1163 */ 'V', '1', '_', '6', '4', 0, /* 1169 */ 'D', '1', '2', '_', '6', '4', 0, /* 1176 */ 'D', '2', '2', '_', '6', '4', 0, /* 1183 */ 'A', '2', '_', '6', '4', 0, /* 1189 */ 'D', '2', '_', '6', '4', 0, /* 1195 */ 'S', '2', '_', '6', '4', 0, /* 1201 */ 'T', '2', '_', '6', '4', 0, /* 1207 */ 'D', '1', '3', '_', '6', '4', 0, /* 1214 */ 'D', '2', '3', '_', '6', '4', 0, /* 1221 */ 'A', '3', '_', '6', '4', 0, /* 1227 */ 'D', '3', '_', '6', '4', 0, /* 1233 */ 'S', '3', '_', '6', '4', 0, /* 1239 */ 'T', '3', '_', '6', '4', 0, /* 1245 */ 'D', '1', '4', '_', '6', '4', 0, /* 1252 */ 'D', '2', '4', '_', '6', '4', 0, /* 1259 */ 'D', '4', '_', '6', '4', 0, /* 1265 */ 'S', '4', '_', '6', '4', 0, /* 1271 */ 'T', '4', '_', '6', '4', 0, /* 1277 */ 'D', '1', '5', '_', '6', '4', 0, /* 1284 */ 'D', '2', '5', '_', '6', '4', 0, /* 1291 */ 'D', '5', '_', '6', '4', 0, /* 1297 */ 'S', '5', '_', '6', '4', 0, /* 1303 */ 'T', '5', '_', '6', '4', 0, /* 1309 */ 'D', '1', '6', '_', '6', '4', 0, /* 1316 */ 'D', '2', '6', '_', '6', '4', 0, /* 1323 */ 'D', '6', '_', '6', '4', 0, /* 1329 */ 'S', '6', '_', '6', '4', 0, /* 1335 */ 'T', '6', '_', '6', '4', 0, /* 1341 */ 'D', '1', '7', '_', '6', '4', 0, /* 1348 */ 'D', '2', '7', '_', '6', '4', 0, /* 1355 */ 'D', '7', '_', '6', '4', 0, /* 1361 */ 'S', '7', '_', '6', '4', 0, /* 1367 */ 'T', '7', '_', '6', '4', 0, /* 1373 */ 'D', '1', '8', '_', '6', '4', 0, /* 1380 */ 'D', '2', '8', '_', '6', '4', 0, /* 1387 */ 'D', '8', '_', '6', '4', 0, /* 1393 */ 'T', '8', '_', '6', '4', 0, /* 1399 */ 'D', '1', '9', '_', '6', '4', 0, /* 1406 */ 'D', '2', '9', '_', '6', '4', 0, /* 1413 */ 'D', '9', '_', '6', '4', 0, /* 1419 */ 'T', '9', '_', '6', '4', 0, /* 1425 */ 'R', 'A', '_', '6', '4', 0, /* 1431 */ 'Z', 'E', 'R', 'O', '_', '6', '4', 0, /* 1439 */ 'F', 'P', '_', '6', '4', 0, /* 1445 */ 'G', 'P', '_', '6', '4', 0, /* 1451 */ 'S', 'P', '_', '6', '4', 0, /* 1457 */ 'A', 'T', '_', '6', '4', 0, /* 1463 */ 'F', 'C', 'C', '4', 0, /* 1468 */ 'D', '4', 0, /* 1471 */ 'F', '4', 0, /* 1474 */ 'F', '_', 'H', 'I', '4', 0, /* 1480 */ 'F', 'C', 'R', '4', 0, /* 1485 */ 'H', 'W', 'R', '4', 0, /* 1490 */ 'S', '4', 0, /* 1493 */ 'T', '4', 0, /* 1496 */ 'W', '4', 0, /* 1499 */ 'C', 'O', 'P', '0', '5', 0, /* 1505 */ 'C', 'O', 'P', '0', '1', '5', 0, /* 1512 */ 'C', 'O', 'P', '2', '1', '5', 0, /* 1519 */ 'C', 'O', 'P', '3', '1', '5', 0, /* 1526 */ 'M', 'S', 'A', '1', '5', 0, /* 1532 */ 'D', '1', '5', 0, /* 1536 */ 'F', '1', '5', 0, /* 1540 */ 'F', '_', 'H', 'I', '1', '5', 0, /* 1547 */ 'F', 'C', 'R', '1', '5', 0, /* 1553 */ 'H', 'W', 'R', '1', '5', 0, /* 1559 */ 'W', '1', '5', 0, /* 1563 */ 'C', 'O', 'P', '0', '2', '5', 0, /* 1570 */ 'C', 'O', 'P', '2', '2', '5', 0, /* 1577 */ 'C', 'O', 'P', '3', '2', '5', 0, /* 1584 */ 'M', 'S', 'A', '2', '5', 0, /* 1590 */ 'F', '2', '5', 0, /* 1594 */ 'F', '_', 'H', 'I', '2', '5', 0, /* 1601 */ 'C', 'O', 'P', '2', '5', 0, /* 1607 */ 'F', 'C', 'R', '2', '5', 0, /* 1613 */ 'H', 'W', 'R', '2', '5', 0, /* 1619 */ 'W', '2', '5', 0, /* 1623 */ 'C', 'O', 'P', '3', '5', 0, /* 1629 */ 'F', 'C', 'C', '5', 0, /* 1634 */ 'D', '5', 0, /* 1637 */ 'F', '5', 0, /* 1640 */ 'F', '_', 'H', 'I', '5', 0, /* 1646 */ 'F', 'C', 'R', '5', 0, /* 1651 */ 'H', 'W', 'R', '5', 0, /* 1656 */ 'S', '5', 0, /* 1659 */ 'T', '5', 0, /* 1662 */ 'W', '5', 0, /* 1665 */ 'C', 'O', 'P', '0', '6', 0, /* 1671 */ 'C', 'O', 'P', '0', '1', '6', 0, /* 1678 */ 'C', 'O', 'P', '2', '1', '6', 0, /* 1685 */ 'C', 'O', 'P', '3', '1', '6', 0, /* 1692 */ 'M', 'S', 'A', '1', '6', 0, /* 1698 */ 'F', '1', '6', 0, /* 1702 */ 'F', '_', 'H', 'I', '1', '6', 0, /* 1709 */ 'F', 'C', 'R', '1', '6', 0, /* 1715 */ 'H', 'W', 'R', '1', '6', 0, /* 1721 */ 'W', '1', '6', 0, /* 1725 */ 'C', 'O', 'P', '0', '2', '6', 0, /* 1732 */ 'C', 'O', 'P', '2', '2', '6', 0, /* 1739 */ 'C', 'O', 'P', '3', '2', '6', 0, /* 1746 */ 'M', 'S', 'A', '2', '6', 0, /* 1752 */ 'F', '2', '6', 0, /* 1756 */ 'F', '_', 'H', 'I', '2', '6', 0, /* 1763 */ 'C', 'O', 'P', '2', '6', 0, /* 1769 */ 'F', 'C', 'R', '2', '6', 0, /* 1775 */ 'H', 'W', 'R', '2', '6', 0, /* 1781 */ 'W', '2', '6', 0, /* 1785 */ 'C', 'O', 'P', '3', '6', 0, /* 1791 */ 'F', 'C', 'C', '6', 0, /* 1796 */ 'D', '6', 0, /* 1799 */ 'F', '6', 0, /* 1802 */ 'F', '_', 'H', 'I', '6', 0, /* 1808 */ 'F', 'C', 'R', '6', 0, /* 1813 */ 'H', 'W', 'R', '6', 0, /* 1818 */ 'S', '6', 0, /* 1821 */ 'T', '6', 0, /* 1824 */ 'W', '6', 0, /* 1827 */ 'C', 'O', 'P', '0', '7', 0, /* 1833 */ 'C', 'O', 'P', '0', '1', '7', 0, /* 1840 */ 'C', 'O', 'P', '2', '1', '7', 0, /* 1847 */ 'C', 'O', 'P', '3', '1', '7', 0, /* 1854 */ 'M', 'S', 'A', '1', '7', 0, /* 1860 */ 'F', '1', '7', 0, /* 1864 */ 'F', '_', 'H', 'I', '1', '7', 0, /* 1871 */ 'F', 'C', 'R', '1', '7', 0, /* 1877 */ 'H', 'W', 'R', '1', '7', 0, /* 1883 */ 'W', '1', '7', 0, /* 1887 */ 'C', 'O', 'P', '0', '2', '7', 0, /* 1894 */ 'C', 'O', 'P', '2', '2', '7', 0, /* 1901 */ 'C', 'O', 'P', '3', '2', '7', 0, /* 1908 */ 'M', 'S', 'A', '2', '7', 0, /* 1914 */ 'F', '2', '7', 0, /* 1918 */ 'F', '_', 'H', 'I', '2', '7', 0, /* 1925 */ 'C', 'O', 'P', '2', '7', 0, /* 1931 */ 'F', 'C', 'R', '2', '7', 0, /* 1937 */ 'H', 'W', 'R', '2', '7', 0, /* 1943 */ 'W', '2', '7', 0, /* 1947 */ 'C', 'O', 'P', '3', '7', 0, /* 1953 */ 'F', 'C', 'C', '7', 0, /* 1958 */ 'D', '7', 0, /* 1961 */ 'F', '7', 0, /* 1964 */ 'F', '_', 'H', 'I', '7', 0, /* 1970 */ 'F', 'C', 'R', '7', 0, /* 1975 */ 'H', 'W', 'R', '7', 0, /* 1980 */ 'S', '7', 0, /* 1983 */ 'T', '7', 0, /* 1986 */ 'W', '7', 0, /* 1989 */ 'C', 'O', 'P', '0', '8', 0, /* 1995 */ 'C', 'O', 'P', '0', '1', '8', 0, /* 2002 */ 'C', 'O', 'P', '2', '1', '8', 0, /* 2009 */ 'C', 'O', 'P', '3', '1', '8', 0, /* 2016 */ 'M', 'S', 'A', '1', '8', 0, /* 2022 */ 'F', '1', '8', 0, /* 2026 */ 'F', '_', 'H', 'I', '1', '8', 0, /* 2033 */ 'F', 'C', 'R', '1', '8', 0, /* 2039 */ 'H', 'W', 'R', '1', '8', 0, /* 2045 */ 'W', '1', '8', 0, /* 2049 */ 'C', 'O', 'P', '0', '2', '8', 0, /* 2056 */ 'C', 'O', 'P', '2', '2', '8', 0, /* 2063 */ 'C', 'O', 'P', '3', '2', '8', 0, /* 2070 */ 'M', 'S', 'A', '2', '8', 0, /* 2076 */ 'F', '2', '8', 0, /* 2080 */ 'F', '_', 'H', 'I', '2', '8', 0, /* 2087 */ 'C', 'O', 'P', '2', '8', 0, /* 2093 */ 'F', 'C', 'R', '2', '8', 0, /* 2099 */ 'H', 'W', 'R', '2', '8', 0, /* 2105 */ 'W', '2', '8', 0, /* 2109 */ 'C', 'O', 'P', '3', '8', 0, /* 2115 */ 'M', 'S', 'A', '8', 0, /* 2120 */ 'D', '8', 0, /* 2123 */ 'F', '8', 0, /* 2126 */ 'F', '_', 'H', 'I', '8', 0, /* 2132 */ 'F', 'C', 'R', '8', 0, /* 2137 */ 'H', 'W', 'R', '8', 0, /* 2142 */ 'T', '8', 0, /* 2145 */ 'W', '8', 0, /* 2148 */ 'C', 'O', 'P', '0', '9', 0, /* 2154 */ 'C', 'O', 'P', '0', '1', '9', 0, /* 2161 */ 'C', 'O', 'P', '2', '1', '9', 0, /* 2168 */ 'C', 'O', 'P', '3', '1', '9', 0, /* 2175 */ 'M', 'S', 'A', '1', '9', 0, /* 2181 */ 'F', '1', '9', 0, /* 2185 */ 'F', '_', 'H', 'I', '1', '9', 0, /* 2192 */ 'F', 'C', 'R', '1', '9', 0, /* 2198 */ 'H', 'W', 'R', '1', '9', 0, /* 2204 */ 'W', '1', '9', 0, /* 2208 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', '1', '6', '_', '1', '9', 0, /* 2224 */ 'C', 'O', 'P', '0', '2', '9', 0, /* 2231 */ 'C', 'O', 'P', '2', '2', '9', 0, /* 2238 */ 'C', 'O', 'P', '3', '2', '9', 0, /* 2245 */ 'M', 'S', 'A', '2', '9', 0, /* 2251 */ 'F', '2', '9', 0, /* 2255 */ 'F', '_', 'H', 'I', '2', '9', 0, /* 2262 */ 'C', 'O', 'P', '2', '9', 0, /* 2268 */ 'F', 'C', 'R', '2', '9', 0, /* 2274 */ 'H', 'W', 'R', '2', '9', 0, /* 2280 */ 'W', '2', '9', 0, /* 2284 */ 'C', 'O', 'P', '3', '9', 0, /* 2290 */ 'M', 'S', 'A', '9', 0, /* 2295 */ 'D', '9', 0, /* 2298 */ 'F', '9', 0, /* 2301 */ 'F', '_', 'H', 'I', '9', 0, /* 2307 */ 'F', 'C', 'R', '9', 0, /* 2312 */ 'H', 'W', 'R', '9', 0, /* 2317 */ 'T', '9', 0, /* 2320 */ 'W', '9', 0, /* 2323 */ 'R', 'A', 0, /* 2326 */ 'P', 'C', 0, /* 2329 */ 'D', 'S', 'P', 'E', 'F', 'I', 0, /* 2336 */ 'Z', 'E', 'R', 'O', 0, /* 2341 */ 'F', 'P', 0, /* 2344 */ 'G', 'P', 0, /* 2347 */ 'S', 'P', 0, /* 2350 */ 'M', 'S', 'A', 'I', 'R', 0, /* 2356 */ 'M', 'S', 'A', 'C', 'S', 'R', 0, /* 2363 */ 'A', 'T', 0, /* 2366 */ 'D', 'S', 'P', 'C', 'C', 'o', 'n', 'd', 0, /* 2375 */ 'M', 'S', 'A', 'S', 'a', 'v', 'e', 0, /* 2383 */ 'D', 'S', 'P', 'O', 'u', 't', 'F', 'l', 'a', 'g', 0, /* 2394 */ 'M', 'S', 'A', 'M', 'a', 'p', 0, /* 2401 */ 'M', 'S', 'A', 'U', 'n', 'm', 'a', 'p', 0, /* 2410 */ 'D', 'S', 'P', 'P', 'o', 's', 0, /* 2417 */ 'M', 'S', 'A', 'A', 'c', 'c', 'e', 's', 's', 0, /* 2427 */ 'D', 'S', 'P', 'S', 'C', 'o', 'u', 'n', 't', 0, /* 2437 */ 'M', 'S', 'A', 'R', 'e', 'q', 'u', 'e', 's', 't', 0, /* 2448 */ 'M', 'S', 'A', 'M', 'o', 'd', 'i', 'f', 'y', 0, /* 2458 */ 'D', 'S', 'P', 'C', 'a', 'r', 'r', 'y', 0, }; extern const MCRegisterDesc MipsRegDesc[] = { // Descriptors { 5, 0, 0, 0, 0, 0 }, { 2363, 1, 82, 1, 4017, 0 }, { 2366, 1, 1, 1, 4017, 0 }, { 2458, 1, 1, 1, 4017, 0 }, { 2329, 1, 1, 1, 4017, 0 }, { 2383, 8, 1, 2, 32, 4 }, { 2410, 1, 1, 1, 1089, 0 }, { 2427, 1, 1, 1, 1089, 0 }, { 2341, 1, 102, 1, 1089, 0 }, { 2344, 1, 104, 1, 1089, 0 }, { 2417, 1, 1, 1, 1089, 0 }, { 2356, 1, 1, 1, 1089, 0 }, { 2350, 1, 1, 1, 1089, 0 }, { 2394, 1, 1, 1, 1089, 0 }, { 2448, 1, 1, 1, 1089, 0 }, { 2437, 1, 1, 1, 1089, 0 }, { 2375, 1, 1, 1, 1089, 0 }, { 2401, 1, 1, 1, 1089, 0 }, { 2326, 1, 1, 1, 1089, 0 }, { 2323, 1, 106, 1, 1089, 0 }, { 2347, 1, 108, 1, 1089, 0 }, { 2336, 1, 110, 1, 1089, 0 }, { 197, 1, 110, 1, 1089, 0 }, { 455, 1, 110, 1, 1089, 0 }, { 659, 1, 110, 1, 1089, 0 }, { 857, 1, 110, 1, 1089, 0 }, { 200, 190, 110, 9, 1042, 10 }, { 458, 190, 1, 9, 1042, 10 }, { 662, 190, 1, 9, 1042, 10 }, { 860, 190, 1, 9, 1042, 10 }, { 1457, 237, 1, 0, 0, 2 }, { 0, 1, 1, 1, 1153, 0 }, { 258, 1, 1, 1, 1153, 0 }, { 516, 1, 1, 1, 1153, 0 }, { 714, 1, 1, 1, 1153, 0 }, { 904, 1, 1, 1, 1153, 0 }, { 1499, 1, 1, 1, 1153, 0 }, { 1665, 1, 1, 1, 1153, 0 }, { 1827, 1, 1, 1, 1153, 0 }, { 1989, 1, 1, 1, 1153, 0 }, { 2148, 1, 1, 1, 1153, 0 }, { 102, 1, 1, 1, 1153, 0 }, { 360, 1, 1, 1, 1153, 0 }, { 618, 1, 1, 1, 1153, 0 }, { 816, 1, 1, 1, 1153, 0 }, { 1006, 1, 1, 1, 1153, 0 }, { 1601, 1, 1, 1, 1153, 0 }, { 1763, 1, 1, 1, 1153, 0 }, { 1925, 1, 1, 1, 1153, 0 }, { 2087, 1, 1, 1, 1153, 0 }, { 2262, 1, 1, 1, 1153, 0 }, { 175, 1, 1, 1, 1153, 0 }, { 433, 1, 1, 1, 1153, 0 }, { 653, 1, 1, 1, 1153, 0 }, { 851, 1, 1, 1, 1153, 0 }, { 1028, 1, 1, 1, 1153, 0 }, { 1623, 1, 1, 1, 1153, 0 }, { 1785, 1, 1, 1, 1153, 0 }, { 1947, 1, 1, 1, 1153, 0 }, { 2109, 1, 1, 1, 1153, 0 }, { 2284, 1, 1, 1, 1153, 0 }, { 6, 1, 1, 1, 1153, 0 }, { 264, 1, 1, 1, 1153, 0 }, { 522, 1, 1, 1, 1153, 0 }, { 720, 1, 1, 1, 1153, 0 }, { 910, 1, 1, 1, 1153, 0 }, { 1505, 1, 1, 1, 1153, 0 }, { 1671, 1, 1, 1, 1153, 0 }, { 1833, 1, 1, 1, 1153, 0 }, { 1995, 1, 1, 1, 1153, 0 }, { 2154, 1, 1, 1, 1153, 0 }, { 64, 1, 1, 1, 1153, 0 }, { 322, 1, 1, 1, 1153, 0 }, { 580, 1, 1, 1, 1153, 0 }, { 778, 1, 1, 1, 1153, 0 }, { 968, 1, 1, 1, 1153, 0 }, { 1563, 1, 1, 1, 1153, 0 }, { 1725, 1, 1, 1, 1153, 0 }, { 1887, 1, 1, 1, 1153, 0 }, { 2049, 1, 1, 1, 1153, 0 }, { 2224, 1, 1, 1, 1153, 0 }, { 137, 1, 1, 1, 1153, 0 }, { 395, 1, 1, 1, 1153, 0 }, { 13, 1, 1, 1, 1153, 0 }, { 271, 1, 1, 1, 1153, 0 }, { 529, 1, 1, 1, 1153, 0 }, { 727, 1, 1, 1, 1153, 0 }, { 917, 1, 1, 1, 1153, 0 }, { 1512, 1, 1, 1, 1153, 0 }, { 1678, 1, 1, 1, 1153, 0 }, { 1840, 1, 1, 1, 1153, 0 }, { 2002, 1, 1, 1, 1153, 0 }, { 2161, 1, 1, 1, 1153, 0 }, { 71, 1, 1, 1, 1153, 0 }, { 329, 1, 1, 1, 1153, 0 }, { 587, 1, 1, 1, 1153, 0 }, { 785, 1, 1, 1, 1153, 0 }, { 975, 1, 1, 1, 1153, 0 }, { 1570, 1, 1, 1, 1153, 0 }, { 1732, 1, 1, 1, 1153, 0 }, { 1894, 1, 1, 1, 1153, 0 }, { 2056, 1, 1, 1, 1153, 0 }, { 2231, 1, 1, 1, 1153, 0 }, { 144, 1, 1, 1, 1153, 0 }, { 402, 1, 1, 1, 1153, 0 }, { 20, 1, 1, 1, 1153, 0 }, { 278, 1, 1, 1, 1153, 0 }, { 536, 1, 1, 1, 1153, 0 }, { 734, 1, 1, 1, 1153, 0 }, { 924, 1, 1, 1, 1153, 0 }, { 1519, 1, 1, 1, 1153, 0 }, { 1685, 1, 1, 1, 1153, 0 }, { 1847, 1, 1, 1, 1153, 0 }, { 2009, 1, 1, 1, 1153, 0 }, { 2168, 1, 1, 1, 1153, 0 }, { 78, 1, 1, 1, 1153, 0 }, { 336, 1, 1, 1, 1153, 0 }, { 594, 1, 1, 1, 1153, 0 }, { 792, 1, 1, 1, 1153, 0 }, { 982, 1, 1, 1, 1153, 0 }, { 1577, 1, 1, 1, 1153, 0 }, { 1739, 1, 1, 1, 1153, 0 }, { 1901, 1, 1, 1, 1153, 0 }, { 2063, 1, 1, 1, 1153, 0 }, { 2238, 1, 1, 1, 1153, 0 }, { 151, 1, 1, 1, 1153, 0 }, { 409, 1, 1, 1, 1153, 0 }, { 209, 14, 1, 9, 994, 10 }, { 467, 17, 1, 9, 994, 10 }, { 671, 20, 1, 9, 994, 10 }, { 869, 23, 1, 9, 994, 10 }, { 1468, 26, 1, 9, 994, 10 }, { 1634, 29, 1, 9, 994, 10 }, { 1796, 32, 1, 9, 994, 10 }, { 1958, 35, 1, 9, 994, 10 }, { 2120, 38, 1, 9, 994, 10 }, { 2295, 41, 1, 9, 994, 10 }, { 33, 44, 1, 9, 994, 10 }, { 291, 47, 1, 9, 994, 10 }, { 549, 50, 1, 9, 994, 10 }, { 747, 53, 1, 9, 994, 10 }, { 937, 56, 1, 9, 994, 10 }, { 1532, 59, 1, 9, 994, 10 }, { 124, 1, 148, 1, 2369, 0 }, { 382, 1, 146, 1, 2369, 0 }, { 640, 1, 144, 1, 2369, 0 }, { 838, 1, 142, 1, 2369, 0 }, { 212, 1, 161, 1, 3985, 0 }, { 470, 1, 165, 1, 3985, 0 }, { 674, 1, 165, 1, 3985, 0 }, { 872, 1, 169, 1, 3985, 0 }, { 1471, 1, 169, 1, 3985, 0 }, { 1637, 1, 173, 1, 3985, 0 }, { 1799, 1, 173, 1, 3985, 0 }, { 1961, 1, 177, 1, 3985, 0 }, { 2123, 1, 177, 1, 3985, 0 }, { 2298, 1, 181, 1, 3985, 0 }, { 37, 1, 181, 1, 3985, 0 }, { 295, 1, 185, 1, 3985, 0 }, { 553, 1, 185, 1, 3985, 0 }, { 751, 1, 189, 1, 3985, 0 }, { 941, 1, 189, 1, 3985, 0 }, { 1536, 1, 193, 1, 3985, 0 }, { 1698, 1, 193, 1, 3985, 0 }, { 1860, 1, 197, 1, 3985, 0 }, { 2022, 1, 197, 1, 3985, 0 }, { 2181, 1, 201, 1, 3985, 0 }, { 91, 1, 201, 1, 3985, 0 }, { 349, 1, 205, 1, 3985, 0 }, { 607, 1, 205, 1, 3985, 0 }, { 805, 1, 209, 1, 3985, 0 }, { 995, 1, 209, 1, 3985, 0 }, { 1590, 1, 213, 1, 3985, 0 }, { 1752, 1, 213, 1, 3985, 0 }, { 1914, 1, 217, 1, 3985, 0 }, { 2076, 1, 217, 1, 3985, 0 }, { 2251, 1, 221, 1, 3985, 0 }, { 164, 1, 221, 1, 3985, 0 }, { 422, 1, 225, 1, 3985, 0 }, { 204, 1, 1, 1, 3985, 0 }, { 462, 1, 1, 1, 3985, 0 }, { 666, 1, 1, 1, 3985, 0 }, { 864, 1, 1, 1, 3985, 0 }, { 1463, 1, 1, 1, 3985, 0 }, { 1629, 1, 1, 1, 3985, 0 }, { 1791, 1, 1, 1, 3985, 0 }, { 1953, 1, 1, 1, 3985, 0 }, { 236, 1, 1, 1, 3985, 0 }, { 494, 1, 1, 1, 3985, 0 }, { 695, 1, 1, 1, 3985, 0 }, { 885, 1, 1, 1, 3985, 0 }, { 1480, 1, 1, 1, 3985, 0 }, { 1646, 1, 1, 1, 3985, 0 }, { 1808, 1, 1, 1, 3985, 0 }, { 1970, 1, 1, 1, 3985, 0 }, { 2132, 1, 1, 1, 3985, 0 }, { 2307, 1, 1, 1, 3985, 0 }, { 48, 1, 1, 1, 3985, 0 }, { 306, 1, 1, 1, 3985, 0 }, { 564, 1, 1, 1, 3985, 0 }, { 762, 1, 1, 1, 3985, 0 }, { 952, 1, 1, 1, 3985, 0 }, { 1547, 1, 1, 1, 3985, 0 }, { 1709, 1, 1, 1, 3985, 0 }, { 1871, 1, 1, 1, 3985, 0 }, { 2033, 1, 1, 1, 3985, 0 }, { 2192, 1, 1, 1, 3985, 0 }, { 108, 1, 1, 1, 3985, 0 }, { 366, 1, 1, 1, 3985, 0 }, { 624, 1, 1, 1, 3985, 0 }, { 822, 1, 1, 1, 3985, 0 }, { 1012, 1, 1, 1, 3985, 0 }, { 1607, 1, 1, 1, 3985, 0 }, { 1769, 1, 1, 1, 3985, 0 }, { 1931, 1, 1, 1, 3985, 0 }, { 2093, 1, 1, 1, 3985, 0 }, { 2268, 1, 1, 1, 3985, 0 }, { 181, 1, 1, 1, 3985, 0 }, { 439, 1, 1, 1, 3985, 0 }, { 1439, 136, 1, 0, 1184, 2 }, { 215, 1, 158, 1, 3953, 0 }, { 473, 1, 158, 1, 3953, 0 }, { 677, 1, 158, 1, 3953, 0 }, { 875, 1, 158, 1, 3953, 0 }, { 1474, 1, 158, 1, 3953, 0 }, { 1640, 1, 158, 1, 3953, 0 }, { 1802, 1, 158, 1, 3953, 0 }, { 1964, 1, 158, 1, 3953, 0 }, { 2126, 1, 158, 1, 3953, 0 }, { 2301, 1, 158, 1, 3953, 0 }, { 41, 1, 158, 1, 3953, 0 }, { 299, 1, 158, 1, 3953, 0 }, { 557, 1, 158, 1, 3953, 0 }, { 755, 1, 158, 1, 3953, 0 }, { 945, 1, 158, 1, 3953, 0 }, { 1540, 1, 158, 1, 3953, 0 }, { 1702, 1, 158, 1, 3953, 0 }, { 1864, 1, 158, 1, 3953, 0 }, { 2026, 1, 158, 1, 3953, 0 }, { 2185, 1, 158, 1, 3953, 0 }, { 95, 1, 158, 1, 3953, 0 }, { 353, 1, 158, 1, 3953, 0 }, { 611, 1, 158, 1, 3953, 0 }, { 809, 1, 158, 1, 3953, 0 }, { 999, 1, 158, 1, 3953, 0 }, { 1594, 1, 158, 1, 3953, 0 }, { 1756, 1, 158, 1, 3953, 0 }, { 1918, 1, 158, 1, 3953, 0 }, { 2080, 1, 158, 1, 3953, 0 }, { 2255, 1, 158, 1, 3953, 0 }, { 168, 1, 158, 1, 3953, 0 }, { 426, 1, 158, 1, 3953, 0 }, { 1445, 128, 1, 0, 1216, 2 }, { 217, 1, 233, 1, 1826, 0 }, { 475, 1, 134, 1, 1826, 0 }, { 679, 1, 134, 1, 1826, 0 }, { 877, 1, 134, 1, 1826, 0 }, { 241, 1, 1, 1, 3921, 0 }, { 499, 1, 1, 1, 3921, 0 }, { 700, 1, 1, 1, 3921, 0 }, { 890, 1, 1, 1, 3921, 0 }, { 1485, 1, 1, 1, 3921, 0 }, { 1651, 1, 1, 1, 3921, 0 }, { 1813, 1, 1, 1, 3921, 0 }, { 1975, 1, 1, 1, 3921, 0 }, { 2137, 1, 1, 1, 3921, 0 }, { 2312, 1, 1, 1, 3921, 0 }, { 54, 1, 1, 1, 3921, 0 }, { 312, 1, 1, 1, 3921, 0 }, { 570, 1, 1, 1, 3921, 0 }, { 768, 1, 1, 1, 3921, 0 }, { 958, 1, 1, 1, 3921, 0 }, { 1553, 1, 1, 1, 3921, 0 }, { 1715, 1, 1, 1, 3921, 0 }, { 1877, 1, 1, 1, 3921, 0 }, { 2039, 1, 1, 1, 3921, 0 }, { 2198, 1, 1, 1, 3921, 0 }, { 114, 1, 1, 1, 3921, 0 }, { 372, 1, 1, 1, 3921, 0 }, { 630, 1, 1, 1, 3921, 0 }, { 828, 1, 1, 1, 3921, 0 }, { 1018, 1, 1, 1, 3921, 0 }, { 1613, 1, 1, 1, 3921, 0 }, { 1775, 1, 1, 1, 3921, 0 }, { 1937, 1, 1, 1, 3921, 0 }, { 2099, 1, 1, 1, 3921, 0 }, { 2274, 1, 1, 1, 3921, 0 }, { 187, 1, 1, 1, 3921, 0 }, { 445, 1, 1, 1, 3921, 0 }, { 221, 1, 100, 1, 3921, 0 }, { 479, 1, 100, 1, 3921, 0 }, { 229, 1, 229, 1, 1794, 0 }, { 487, 1, 126, 1, 1794, 0 }, { 688, 1, 126, 1, 1794, 0 }, { 881, 1, 126, 1, 1794, 0 }, { 224, 1, 1, 1, 3889, 0 }, { 482, 1, 1, 1, 3889, 0 }, { 683, 1, 1, 1, 3889, 0 }, { 2115, 1, 1, 1, 3889, 0 }, { 2290, 1, 1, 1, 3889, 0 }, { 27, 1, 1, 1, 3889, 0 }, { 285, 1, 1, 1, 3889, 0 }, { 543, 1, 1, 1, 3889, 0 }, { 741, 1, 1, 1, 3889, 0 }, { 931, 1, 1, 1, 3889, 0 }, { 1526, 1, 1, 1, 3889, 0 }, { 1692, 1, 1, 1, 3889, 0 }, { 1854, 1, 1, 1, 3889, 0 }, { 2016, 1, 1, 1, 3889, 0 }, { 2175, 1, 1, 1, 3889, 0 }, { 85, 1, 1, 1, 3889, 0 }, { 343, 1, 1, 1, 3889, 0 }, { 601, 1, 1, 1, 3889, 0 }, { 799, 1, 1, 1, 3889, 0 }, { 989, 1, 1, 1, 3889, 0 }, { 1584, 1, 1, 1, 3889, 0 }, { 1746, 1, 1, 1, 3889, 0 }, { 1908, 1, 1, 1, 3889, 0 }, { 2070, 1, 1, 1, 3889, 0 }, { 2245, 1, 1, 1, 3889, 0 }, { 158, 1, 1, 1, 3889, 0 }, { 416, 1, 1, 1, 3889, 0 }, { 233, 1, 1, 1, 3889, 0 }, { 491, 1, 1, 1, 3889, 0 }, { 692, 1, 1, 1, 3889, 0 }, { 1425, 124, 1, 0, 1248, 2 }, { 246, 1, 98, 1, 3857, 0 }, { 504, 1, 98, 1, 3857, 0 }, { 705, 1, 98, 1, 3857, 0 }, { 895, 1, 98, 1, 3857, 0 }, { 1490, 1, 98, 1, 3857, 0 }, { 1656, 1, 98, 1, 3857, 0 }, { 1818, 1, 98, 1, 3857, 0 }, { 1980, 1, 98, 1, 3857, 0 }, { 1451, 122, 1, 0, 1280, 2 }, { 249, 1, 96, 1, 3825, 0 }, { 507, 1, 96, 1, 3825, 0 }, { 708, 1, 96, 1, 3825, 0 }, { 898, 1, 96, 1, 3825, 0 }, { 1493, 1, 96, 1, 3825, 0 }, { 1659, 1, 96, 1, 3825, 0 }, { 1821, 1, 96, 1, 3825, 0 }, { 1983, 1, 96, 1, 3825, 0 }, { 2142, 1, 96, 1, 3825, 0 }, { 2317, 1, 96, 1, 3825, 0 }, { 252, 1, 96, 1, 3825, 0 }, { 510, 1, 96, 1, 3825, 0 }, { 255, 92, 1, 8, 1425, 10 }, { 513, 92, 1, 8, 1425, 10 }, { 711, 92, 1, 8, 1425, 10 }, { 901, 92, 1, 8, 1425, 10 }, { 1496, 92, 1, 8, 1425, 10 }, { 1662, 92, 1, 8, 1425, 10 }, { 1824, 92, 1, 8, 1425, 10 }, { 1986, 92, 1, 8, 1425, 10 }, { 2145, 92, 1, 8, 1425, 10 }, { 2320, 92, 1, 8, 1425, 10 }, { 60, 92, 1, 8, 1425, 10 }, { 318, 92, 1, 8, 1425, 10 }, { 576, 92, 1, 8, 1425, 10 }, { 774, 92, 1, 8, 1425, 10 }, { 964, 92, 1, 8, 1425, 10 }, { 1559, 92, 1, 8, 1425, 10 }, { 1721, 92, 1, 8, 1425, 10 }, { 1883, 92, 1, 8, 1425, 10 }, { 2045, 92, 1, 8, 1425, 10 }, { 2204, 92, 1, 8, 1425, 10 }, { 120, 92, 1, 8, 1425, 10 }, { 378, 92, 1, 8, 1425, 10 }, { 636, 92, 1, 8, 1425, 10 }, { 834, 92, 1, 8, 1425, 10 }, { 1024, 92, 1, 8, 1425, 10 }, { 1619, 92, 1, 8, 1425, 10 }, { 1781, 92, 1, 8, 1425, 10 }, { 1943, 92, 1, 8, 1425, 10 }, { 2105, 92, 1, 8, 1425, 10 }, { 2280, 92, 1, 8, 1425, 10 }, { 193, 92, 1, 8, 1425, 10 }, { 451, 92, 1, 8, 1425, 10 }, { 1431, 118, 1, 0, 1921, 2 }, { 1055, 118, 1, 0, 1921, 2 }, { 1133, 118, 1, 0, 1921, 2 }, { 1183, 118, 1, 0, 1921, 2 }, { 1221, 118, 1, 0, 1921, 2 }, { 1061, 130, 1, 12, 656, 10 }, { 1068, 93, 159, 9, 1377, 10 }, { 1139, 93, 159, 9, 1377, 10 }, { 1189, 93, 159, 9, 1377, 10 }, { 1227, 93, 159, 9, 1377, 10 }, { 1259, 93, 159, 9, 1377, 10 }, { 1291, 93, 159, 9, 1377, 10 }, { 1323, 93, 159, 9, 1377, 10 }, { 1355, 93, 159, 9, 1377, 10 }, { 1387, 93, 159, 9, 1377, 10 }, { 1413, 93, 159, 9, 1377, 10 }, { 1034, 93, 159, 9, 1377, 10 }, { 1112, 93, 159, 9, 1377, 10 }, { 1169, 93, 159, 9, 1377, 10 }, { 1207, 93, 159, 9, 1377, 10 }, { 1245, 93, 159, 9, 1377, 10 }, { 1277, 93, 159, 9, 1377, 10 }, { 1309, 93, 159, 9, 1377, 10 }, { 1341, 93, 159, 9, 1377, 10 }, { 1373, 93, 159, 9, 1377, 10 }, { 1399, 93, 159, 9, 1377, 10 }, { 1041, 93, 159, 9, 1377, 10 }, { 1119, 93, 159, 9, 1377, 10 }, { 1176, 93, 159, 9, 1377, 10 }, { 1214, 93, 159, 9, 1377, 10 }, { 1252, 93, 159, 9, 1377, 10 }, { 1284, 93, 159, 9, 1377, 10 }, { 1316, 93, 159, 9, 1377, 10 }, { 1348, 93, 159, 9, 1377, 10 }, { 1380, 93, 159, 9, 1377, 10 }, { 1406, 93, 159, 9, 1377, 10 }, { 1048, 93, 159, 9, 1377, 10 }, { 1126, 93, 159, 9, 1377, 10 }, { 2208, 1, 116, 1, 1120, 0 }, { 1074, 138, 235, 0, 1344, 2 }, { 1081, 150, 1, 0, 2241, 2 }, { 1145, 150, 1, 0, 2241, 2 }, { 1087, 150, 231, 0, 1312, 2 }, { 1094, 154, 1, 0, 2433, 2 }, { 1151, 154, 1, 0, 2433, 2 }, { 1195, 154, 1, 0, 2433, 2 }, { 1233, 154, 1, 0, 2433, 2 }, { 1265, 154, 1, 0, 2433, 2 }, { 1297, 154, 1, 0, 2433, 2 }, { 1329, 154, 1, 0, 2433, 2 }, { 1361, 154, 1, 0, 2433, 2 }, { 1100, 156, 1, 0, 2433, 2 }, { 1157, 156, 1, 0, 2433, 2 }, { 1201, 156, 1, 0, 2433, 2 }, { 1239, 156, 1, 0, 2433, 2 }, { 1271, 156, 1, 0, 2433, 2 }, { 1303, 156, 1, 0, 2433, 2 }, { 1335, 156, 1, 0, 2433, 2 }, { 1367, 156, 1, 0, 2433, 2 }, { 1393, 156, 1, 0, 2433, 2 }, { 1419, 156, 1, 0, 2433, 2 }, { 1106, 156, 1, 0, 2433, 2 }, { 1163, 156, 1, 0, 2433, 2 }, }; extern const MCPhysReg MipsRegUnitRoots[][2] = { { Mips::AT }, { Mips::DSPCCond }, { Mips::DSPCarry }, { Mips::DSPEFI }, { Mips::DSPOutFlag16_19 }, { Mips::DSPOutFlag20 }, { Mips::DSPOutFlag21 }, { Mips::DSPOutFlag22 }, { Mips::DSPOutFlag23 }, { Mips::DSPPos }, { Mips::DSPSCount }, { Mips::FP }, { Mips::GP }, { Mips::MSAAccess }, { Mips::MSACSR }, { Mips::MSAIR }, { Mips::MSAMap }, { Mips::MSAModify }, { Mips::MSARequest }, { Mips::MSASave }, { Mips::MSAUnmap }, { Mips::PC }, { Mips::RA }, { Mips::SP }, { Mips::ZERO }, { Mips::A0 }, { Mips::A1 }, { Mips::A2 }, { Mips::A3 }, { Mips::LO0 }, { Mips::HI0 }, { Mips::LO1 }, { Mips::HI1 }, { Mips::LO2 }, { Mips::HI2 }, { Mips::LO3 }, { Mips::HI3 }, { Mips::COP00 }, { Mips::COP01 }, { Mips::COP02 }, { Mips::COP03 }, { Mips::COP04 }, { Mips::COP05 }, { Mips::COP06 }, { Mips::COP07 }, { Mips::COP08 }, { Mips::COP09 }, { Mips::COP20 }, { Mips::COP21 }, { Mips::COP22 }, { Mips::COP23 }, { Mips::COP24 }, { Mips::COP25 }, { Mips::COP26 }, { Mips::COP27 }, { Mips::COP28 }, { Mips::COP29 }, { Mips::COP30 }, { Mips::COP31 }, { Mips::COP32 }, { Mips::COP33 }, { Mips::COP34 }, { Mips::COP35 }, { Mips::COP36 }, { Mips::COP37 }, { Mips::COP38 }, { Mips::COP39 }, { Mips::COP010 }, { Mips::COP011 }, { Mips::COP012 }, { Mips::COP013 }, { Mips::COP014 }, { Mips::COP015 }, { Mips::COP016 }, { Mips::COP017 }, { Mips::COP018 }, { Mips::COP019 }, { Mips::COP020 }, { Mips::COP021 }, { Mips::COP022 }, { Mips::COP023 }, { Mips::COP024 }, { Mips::COP025 }, { Mips::COP026 }, { Mips::COP027 }, { Mips::COP028 }, { Mips::COP029 }, { Mips::COP030 }, { Mips::COP031 }, { Mips::COP210 }, { Mips::COP211 }, { Mips::COP212 }, { Mips::COP213 }, { Mips::COP214 }, { Mips::COP215 }, { Mips::COP216 }, { Mips::COP217 }, { Mips::COP218 }, { Mips::COP219 }, { Mips::COP220 }, { Mips::COP221 }, { Mips::COP222 }, { Mips::COP223 }, { Mips::COP224 }, { Mips::COP225 }, { Mips::COP226 }, { Mips::COP227 }, { Mips::COP228 }, { Mips::COP229 }, { Mips::COP230 }, { Mips::COP231 }, { Mips::COP310 }, { Mips::COP311 }, { Mips::COP312 }, { Mips::COP313 }, { Mips::COP314 }, { Mips::COP315 }, { Mips::COP316 }, { Mips::COP317 }, { Mips::COP318 }, { Mips::COP319 }, { Mips::COP320 }, { Mips::COP321 }, { Mips::COP322 }, { Mips::COP323 }, { Mips::COP324 }, { Mips::COP325 }, { Mips::COP326 }, { Mips::COP327 }, { Mips::COP328 }, { Mips::COP329 }, { Mips::COP330 }, { Mips::COP331 }, { Mips::F0 }, { Mips::F1 }, { Mips::F2 }, { Mips::F3 }, { Mips::F4 }, { Mips::F5 }, { Mips::F6 }, { Mips::F7 }, { Mips::F8 }, { Mips::F9 }, { Mips::F10 }, { Mips::F11 }, { Mips::F12 }, { Mips::F13 }, { Mips::F14 }, { Mips::F15 }, { Mips::F16 }, { Mips::F17 }, { Mips::F18 }, { Mips::F19 }, { Mips::F20 }, { Mips::F21 }, { Mips::F22 }, { Mips::F23 }, { Mips::F24 }, { Mips::F25 }, { Mips::F26 }, { Mips::F27 }, { Mips::F28 }, { Mips::F29 }, { Mips::F30 }, { Mips::F31 }, { Mips::FCC0 }, { Mips::FCC1 }, { Mips::FCC2 }, { Mips::FCC3 }, { Mips::FCC4 }, { Mips::FCC5 }, { Mips::FCC6 }, { Mips::FCC7 }, { Mips::FCR0 }, { Mips::FCR1 }, { Mips::FCR2 }, { Mips::FCR3 }, { Mips::FCR4 }, { Mips::FCR5 }, { Mips::FCR6 }, { Mips::FCR7 }, { Mips::FCR8 }, { Mips::FCR9 }, { Mips::FCR10 }, { Mips::FCR11 }, { Mips::FCR12 }, { Mips::FCR13 }, { Mips::FCR14 }, { Mips::FCR15 }, { Mips::FCR16 }, { Mips::FCR17 }, { Mips::FCR18 }, { Mips::FCR19 }, { Mips::FCR20 }, { Mips::FCR21 }, { Mips::FCR22 }, { Mips::FCR23 }, { Mips::FCR24 }, { Mips::FCR25 }, { Mips::FCR26 }, { Mips::FCR27 }, { Mips::FCR28 }, { Mips::FCR29 }, { Mips::FCR30 }, { Mips::FCR31 }, { Mips::F_HI0 }, { Mips::F_HI1 }, { Mips::F_HI2 }, { Mips::F_HI3 }, { Mips::F_HI4 }, { Mips::F_HI5 }, { Mips::F_HI6 }, { Mips::F_HI7 }, { Mips::F_HI8 }, { Mips::F_HI9 }, { Mips::F_HI10 }, { Mips::F_HI11 }, { Mips::F_HI12 }, { Mips::F_HI13 }, { Mips::F_HI14 }, { Mips::F_HI15 }, { Mips::F_HI16 }, { Mips::F_HI17 }, { Mips::F_HI18 }, { Mips::F_HI19 }, { Mips::F_HI20 }, { Mips::F_HI21 }, { Mips::F_HI22 }, { Mips::F_HI23 }, { Mips::F_HI24 }, { Mips::F_HI25 }, { Mips::F_HI26 }, { Mips::F_HI27 }, { Mips::F_HI28 }, { Mips::F_HI29 }, { Mips::F_HI30 }, { Mips::F_HI31 }, { Mips::HWR0 }, { Mips::HWR1 }, { Mips::HWR2 }, { Mips::HWR3 }, { Mips::HWR4 }, { Mips::HWR5 }, { Mips::HWR6 }, { Mips::HWR7 }, { Mips::HWR8 }, { Mips::HWR9 }, { Mips::HWR10 }, { Mips::HWR11 }, { Mips::HWR12 }, { Mips::HWR13 }, { Mips::HWR14 }, { Mips::HWR15 }, { Mips::HWR16 }, { Mips::HWR17 }, { Mips::HWR18 }, { Mips::HWR19 }, { Mips::HWR20 }, { Mips::HWR21 }, { Mips::HWR22 }, { Mips::HWR23 }, { Mips::HWR24 }, { Mips::HWR25 }, { Mips::HWR26 }, { Mips::HWR27 }, { Mips::HWR28 }, { Mips::HWR29 }, { Mips::HWR30 }, { Mips::HWR31 }, { Mips::K0 }, { Mips::K1 }, { Mips::MPL0 }, { Mips::MPL1 }, { Mips::MPL2 }, { Mips::MSA8 }, { Mips::MSA9 }, { Mips::MSA10 }, { Mips::MSA11 }, { Mips::MSA12 }, { Mips::MSA13 }, { Mips::MSA14 }, { Mips::MSA15 }, { Mips::MSA16 }, { Mips::MSA17 }, { Mips::MSA18 }, { Mips::MSA19 }, { Mips::MSA20 }, { Mips::MSA21 }, { Mips::MSA22 }, { Mips::MSA23 }, { Mips::MSA24 }, { Mips::MSA25 }, { Mips::MSA26 }, { Mips::MSA27 }, { Mips::MSA28 }, { Mips::MSA29 }, { Mips::MSA30 }, { Mips::MSA31 }, { Mips::P0 }, { Mips::P1 }, { Mips::P2 }, { Mips::S0 }, { Mips::S1 }, { Mips::S2 }, { Mips::S3 }, { Mips::S4 }, { Mips::S5 }, { Mips::S6 }, { Mips::S7 }, { Mips::T0 }, { Mips::T1 }, { Mips::T2 }, { Mips::T3 }, { Mips::T4 }, { Mips::T5 }, { Mips::T6 }, { Mips::T7 }, { Mips::T8 }, { Mips::T9 }, { Mips::V0 }, { Mips::V1 }, }; namespace { // Register classes... // MSA128F16 Register Class... const MCPhysReg MSA128F16[] = { Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31, }; // MSA128F16 Bit set. const uint8_t MSA128F16Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, }; // CCR Register Class... const MCPhysReg CCR[] = { Mips::FCR0, Mips::FCR1, Mips::FCR2, Mips::FCR3, Mips::FCR4, Mips::FCR5, Mips::FCR6, Mips::FCR7, Mips::FCR8, Mips::FCR9, Mips::FCR10, Mips::FCR11, Mips::FCR12, Mips::FCR13, Mips::FCR14, Mips::FCR15, Mips::FCR16, Mips::FCR17, Mips::FCR18, Mips::FCR19, Mips::FCR20, Mips::FCR21, Mips::FCR22, Mips::FCR23, Mips::FCR24, Mips::FCR25, Mips::FCR26, Mips::FCR27, Mips::FCR28, Mips::FCR29, Mips::FCR30, Mips::FCR31, }; // CCR Bit set. const uint8_t CCRBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, }; // COP0 Register Class... const MCPhysReg COP0[] = { Mips::COP00, Mips::COP01, Mips::COP02, Mips::COP03, Mips::COP04, Mips::COP05, Mips::COP06, Mips::COP07, Mips::COP08, Mips::COP09, Mips::COP010, Mips::COP011, Mips::COP012, Mips::COP013, Mips::COP014, Mips::COP015, Mips::COP016, Mips::COP017, Mips::COP018, Mips::COP019, Mips::COP020, Mips::COP021, Mips::COP022, Mips::COP023, Mips::COP024, Mips::COP025, Mips::COP026, Mips::COP027, Mips::COP028, Mips::COP029, Mips::COP030, Mips::COP031, }; // COP0 Bit set. const uint8_t COP0Bits[] = { 0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0x00, 0xe0, 0xff, 0xff, 0x07, }; // COP2 Register Class... const MCPhysReg COP2[] = { Mips::COP20, Mips::COP21, Mips::COP22, Mips::COP23, Mips::COP24, Mips::COP25, Mips::COP26, Mips::COP27, Mips::COP28, Mips::COP29, Mips::COP210, Mips::COP211, Mips::COP212, Mips::COP213, Mips::COP214, Mips::COP215, Mips::COP216, Mips::COP217, Mips::COP218, Mips::COP219, Mips::COP220, Mips::COP221, Mips::COP222, Mips::COP223, Mips::COP224, Mips::COP225, Mips::COP226, Mips::COP227, Mips::COP228, Mips::COP229, Mips::COP230, Mips::COP231, }; // COP2 Bit set. const uint8_t COP2Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x01, }; // COP3 Register Class... const MCPhysReg COP3[] = { Mips::COP30, Mips::COP31, Mips::COP32, Mips::COP33, Mips::COP34, Mips::COP35, Mips::COP36, Mips::COP37, Mips::COP38, Mips::COP39, Mips::COP310, Mips::COP311, Mips::COP312, Mips::COP313, Mips::COP314, Mips::COP315, Mips::COP316, Mips::COP317, Mips::COP318, Mips::COP319, Mips::COP320, Mips::COP321, Mips::COP322, Mips::COP323, Mips::COP324, Mips::COP325, Mips::COP326, Mips::COP327, Mips::COP328, Mips::COP329, Mips::COP330, Mips::COP331, }; // COP3 Bit set. const uint8_t COP3Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x7f, }; // DSPR Register Class... const MCPhysReg DSPR[] = { Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA, }; // DSPR Bit set. const uint8_t DSPRBits[] = { 0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07, }; // FGR32 Register Class... const MCPhysReg FGR32[] = { Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, Mips::F31, }; // FGR32 Bit set. const uint8_t FGR32Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, }; // FGRCC Register Class... const MCPhysReg FGRCC[] = { Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, Mips::F31, }; // FGRCC Bit set. const uint8_t FGRCCBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, }; // GPR32 Register Class... const MCPhysReg GPR32[] = { Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA, }; // GPR32 Bit set. const uint8_t GPR32Bits[] = { 0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07, }; // HWRegs Register Class... const MCPhysReg HWRegs[] = { Mips::HWR0, Mips::HWR1, Mips::HWR2, Mips::HWR3, Mips::HWR4, Mips::HWR5, Mips::HWR6, Mips::HWR7, Mips::HWR8, Mips::HWR9, Mips::HWR10, Mips::HWR11, Mips::HWR12, Mips::HWR13, Mips::HWR14, Mips::HWR15, Mips::HWR16, Mips::HWR17, Mips::HWR18, Mips::HWR19, Mips::HWR20, Mips::HWR21, Mips::HWR22, Mips::HWR23, Mips::HWR24, Mips::HWR25, Mips::HWR26, Mips::HWR27, Mips::HWR28, Mips::HWR29, Mips::HWR30, Mips::HWR31, }; // HWRegs Bit set. const uint8_t HWRegsBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, }; // MSACtrl Register Class... const MCPhysReg MSACtrl[] = { Mips::MSAIR, Mips::MSACSR, Mips::MSAAccess, Mips::MSASave, Mips::MSAModify, Mips::MSARequest, Mips::MSAMap, Mips::MSAUnmap, Mips::MSA8, Mips::MSA9, Mips::MSA10, Mips::MSA11, Mips::MSA12, Mips::MSA13, Mips::MSA14, Mips::MSA15, Mips::MSA16, Mips::MSA17, Mips::MSA18, Mips::MSA19, Mips::MSA20, Mips::MSA21, Mips::MSA22, Mips::MSA23, Mips::MSA24, Mips::MSA25, Mips::MSA26, Mips::MSA27, Mips::MSA28, Mips::MSA29, Mips::MSA30, Mips::MSA31, }; // MSACtrl Bit set. const uint8_t MSACtrlBits[] = { 0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0x03, }; // GPR32NONZERO Register Class... const MCPhysReg GPR32NONZERO[] = { Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA, }; // GPR32NONZERO Bit set. const uint8_t GPR32NONZEROBits[] = { 0x02, 0x03, 0xd8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07, }; // CPU16RegsPlusSP Register Class... const MCPhysReg CPU16RegsPlusSP[] = { Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::S0, Mips::S1, Mips::SP, }; // CPU16RegsPlusSP Bit set. const uint8_t CPU16RegsPlusSPBits[] = { 0x00, 0x00, 0xd0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, }; // CPU16Regs Register Class... const MCPhysReg CPU16Regs[] = { Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::S0, Mips::S1, }; // CPU16Regs Bit set. const uint8_t CPU16RegsBits[] = { 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, }; // FCC Register Class... const MCPhysReg FCC[] = { Mips::FCC0, Mips::FCC1, Mips::FCC2, Mips::FCC3, Mips::FCC4, Mips::FCC5, Mips::FCC6, Mips::FCC7, }; // FCC Bit set. const uint8_t FCCBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, }; // GPRMM16 Register Class... const MCPhysReg GPRMM16[] = { Mips::S0, Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, }; // GPRMM16 Bit set. const uint8_t GPRMM16Bits[] = { 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, }; // GPRMM16MoveP Register Class... const MCPhysReg GPRMM16MoveP[] = { Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, Mips::S0, Mips::S2, Mips::S3, Mips::S4, }; // GPRMM16MoveP Bit set. const uint8_t GPRMM16MovePBits[] = { 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06, }; // GPRMM16Zero Register Class... const MCPhysReg GPRMM16Zero[] = { Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, }; // GPRMM16Zero Bit set. const uint8_t GPRMM16ZeroBits[] = { 0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, }; // CPU16Regs_and_GPRMM16Zero Register Class... const MCPhysReg CPU16Regs_and_GPRMM16Zero[] = { Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, }; // CPU16Regs_and_GPRMM16Zero Bit set. const uint8_t CPU16Regs_and_GPRMM16ZeroBits[] = { 0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, }; // GPR32NONZERO_and_GPRMM16MoveP Register Class... const MCPhysReg GPR32NONZERO_and_GPRMM16MoveP[] = { Mips::S1, Mips::V0, Mips::V1, Mips::S0, Mips::S2, Mips::S3, Mips::S4, }; // GPR32NONZERO_and_GPRMM16MoveP Bit set. const uint8_t GPR32NONZERO_and_GPRMM16MovePBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06, }; // GPRMM16MovePPairSecond Register Class... const MCPhysReg GPRMM16MovePPairSecond[] = { Mips::A1, Mips::A2, Mips::A3, Mips::S5, Mips::S6, }; // GPRMM16MovePPairSecond Bit set. const uint8_t GPRMM16MovePPairSecondBits[] = { 0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, }; // CPU16Regs_and_GPRMM16MoveP Register Class... const MCPhysReg CPU16Regs_and_GPRMM16MoveP[] = { Mips::S1, Mips::V0, Mips::V1, Mips::S0, }; // CPU16Regs_and_GPRMM16MoveP Bit set. const uint8_t CPU16Regs_and_GPRMM16MovePBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, }; // GPRMM16MoveP_and_GPRMM16Zero Register Class... const MCPhysReg GPRMM16MoveP_and_GPRMM16Zero[] = { Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, }; // GPRMM16MoveP_and_GPRMM16Zero Bit set. const uint8_t GPRMM16MoveP_and_GPRMM16ZeroBits[] = { 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, }; // HI32DSP Register Class... const MCPhysReg HI32DSP[] = { Mips::HI0, Mips::HI1, Mips::HI2, Mips::HI3, }; // HI32DSP Bit set. const uint8_t HI32DSPBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, }; // LO32DSP Register Class... const MCPhysReg LO32DSP[] = { Mips::LO0, Mips::LO1, Mips::LO2, Mips::LO3, }; // LO32DSP Bit set. const uint8_t LO32DSPBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, }; // CPU16Regs_and_GPRMM16MovePPairSecond Register Class... const MCPhysReg CPU16Regs_and_GPRMM16MovePPairSecond[] = { Mips::A1, Mips::A2, Mips::A3, }; // CPU16Regs_and_GPRMM16MovePPairSecond Bit set. const uint8_t CPU16Regs_and_GPRMM16MovePPairSecondBits[] = { 0x00, 0x00, 0x80, 0x03, }; // GPRMM16MovePPairFirst Register Class... const MCPhysReg GPRMM16MovePPairFirst[] = { Mips::A0, Mips::A1, Mips::A2, }; // GPRMM16MovePPairFirst Bit set. const uint8_t GPRMM16MovePPairFirstBits[] = { 0x00, 0x00, 0xc0, 0x01, }; // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class... const MCPhysReg GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = { Mips::S1, Mips::V0, Mips::V1, }; // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set. const uint8_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, }; // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Register Class... const MCPhysReg GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond[] = { Mips::A1, Mips::A2, }; // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Bit set. const uint8_t GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits[] = { 0x00, 0x00, 0x80, 0x01, }; // CPURAReg Register Class... const MCPhysReg CPURAReg[] = { Mips::RA, }; // CPURAReg Bit set. const uint8_t CPURARegBits[] = { 0x00, 0x00, 0x08, }; // CPUSPReg Register Class... const MCPhysReg CPUSPReg[] = { Mips::SP, }; // CPUSPReg Bit set. const uint8_t CPUSPRegBits[] = { 0x00, 0x00, 0x10, }; // DSPCC Register Class... const MCPhysReg DSPCC[] = { Mips::DSPCCond, }; // DSPCC Bit set. const uint8_t DSPCCBits[] = { 0x04, }; // GP32 Register Class... const MCPhysReg GP32[] = { Mips::GP, }; // GP32 Bit set. const uint8_t GP32Bits[] = { 0x00, 0x02, }; // GPR32ZERO Register Class... const MCPhysReg GPR32ZERO[] = { Mips::ZERO, }; // GPR32ZERO Bit set. const uint8_t GPR32ZEROBits[] = { 0x00, 0x00, 0x20, }; // HI32 Register Class... const MCPhysReg HI32[] = { Mips::HI0, }; // HI32 Bit set. const uint8_t HI32Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, }; // LO32 Register Class... const MCPhysReg LO32[] = { Mips::LO0, }; // LO32 Bit set. const uint8_t LO32Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, }; // SP32 Register Class... const MCPhysReg SP32[] = { Mips::SP, }; // SP32 Bit set. const uint8_t SP32Bits[] = { 0x00, 0x00, 0x10, }; // FGR64 Register Class... const MCPhysReg FGR64[] = { Mips::D0_64, Mips::D1_64, Mips::D2_64, Mips::D3_64, Mips::D4_64, Mips::D5_64, Mips::D6_64, Mips::D7_64, Mips::D8_64, Mips::D9_64, Mips::D10_64, Mips::D11_64, Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64, Mips::D20_64, Mips::D21_64, Mips::D22_64, Mips::D23_64, Mips::D24_64, Mips::D25_64, Mips::D26_64, Mips::D27_64, Mips::D28_64, Mips::D29_64, Mips::D30_64, Mips::D31_64, }; // FGR64 Bit set. const uint8_t FGR64Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, }; // GPR64 Register Class... const MCPhysReg GPR64[] = { Mips::ZERO_64, Mips::AT_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64, Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, Mips::S5_64, Mips::S6_64, Mips::S7_64, Mips::T8_64, Mips::T9_64, Mips::K0_64, Mips::K1_64, Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64, }; // GPR64 Bit set. const uint8_t GPR64Bits[] = { 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03, }; // GPR64_with_sub_32_in_GPR32NONZERO Register Class... const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO[] = { Mips::AT_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64, Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, Mips::S5_64, Mips::S6_64, Mips::S7_64, Mips::T8_64, Mips::T9_64, Mips::K0_64, Mips::K1_64, Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64, }; // GPR64_with_sub_32_in_GPR32NONZERO Bit set. const uint8_t GPR64_with_sub_32_in_GPR32NONZEROBits[] = { 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03, }; // AFGR64 Register Class... const MCPhysReg AFGR64[] = { Mips::D0, Mips::D1, Mips::D2, Mips::D3, Mips::D4, Mips::D5, Mips::D6, Mips::D7, Mips::D8, Mips::D9, Mips::D10, Mips::D11, Mips::D12, Mips::D13, Mips::D14, Mips::D15, }; // AFGR64 Bit set. const uint8_t AFGR64Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, }; // GPR64_with_sub_32_in_CPU16RegsPlusSP Register Class... const MCPhysReg GPR64_with_sub_32_in_CPU16RegsPlusSP[] = { Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S0_64, Mips::S1_64, Mips::SP_64, }; // GPR64_with_sub_32_in_CPU16RegsPlusSP Bit set. const uint8_t GPR64_with_sub_32_in_CPU16RegsPlusSPBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, }; // GPR64_with_sub_32_in_CPU16Regs Register Class... const MCPhysReg GPR64_with_sub_32_in_CPU16Regs[] = { Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S0_64, Mips::S1_64, }; // GPR64_with_sub_32_in_CPU16Regs Bit set. const uint8_t GPR64_with_sub_32_in_CPU16RegsBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, }; // GPR64_with_sub_32_in_GPRMM16MoveP Register Class... const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP[] = { Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, }; // GPR64_with_sub_32_in_GPRMM16MoveP Bit set. const uint8_t GPR64_with_sub_32_in_GPRMM16MovePBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03, }; // GPR64_with_sub_32_in_GPRMM16Zero Register Class... const MCPhysReg GPR64_with_sub_32_in_GPRMM16Zero[] = { Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S1_64, }; // GPR64_with_sub_32_in_GPRMM16Zero Bit set. const uint8_t GPR64_with_sub_32_in_GPRMM16ZeroBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, }; // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Register Class... const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero[] = { Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S1_64, }; // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Bit set. const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, }; // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP Register Class... const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP[] = { Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, }; // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP Bit set. const uint8_t GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03, }; // GPR64_with_sub_32_in_GPRMM16MovePPairSecond Register Class... const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairSecond[] = { Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S5_64, Mips::S6_64, }; // GPR64_with_sub_32_in_GPRMM16MovePPairSecond Bit set. const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, }; // ACC64DSP Register Class... const MCPhysReg ACC64DSP[] = { Mips::AC0, Mips::AC1, Mips::AC2, Mips::AC3, }; // ACC64DSP Bit set. const uint8_t ACC64DSPBits[] = { 0x00, 0x00, 0x00, 0x3c, }; // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Register Class... const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP[] = { Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64, }; // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Bit set. const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, }; // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Register Class... const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero[] = { Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::S1_64, }; // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Bit set. const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, }; // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond Register Class... const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond[] = { Mips::A1_64, Mips::A2_64, Mips::A3_64, }; // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond Bit set. const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, }; // GPR64_with_sub_32_in_GPRMM16MovePPairFirst Register Class... const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairFirst[] = { Mips::A0_64, Mips::A1_64, Mips::A2_64, }; // GPR64_with_sub_32_in_GPRMM16MovePPairFirst Bit set. const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, }; // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class... const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = { Mips::V0_64, Mips::V1_64, Mips::S1_64, }; // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set. const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, }; // OCTEON_MPL Register Class... const MCPhysReg OCTEON_MPL[] = { Mips::MPL0, Mips::MPL1, Mips::MPL2, }; // OCTEON_MPL Bit set. const uint8_t OCTEON_MPLBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03, }; // OCTEON_P Register Class... const MCPhysReg OCTEON_P[] = { Mips::P0, Mips::P1, Mips::P2, }; // OCTEON_P Bit set. const uint8_t OCTEON_PBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, }; // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Register Class... const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond[] = { Mips::A1_64, Mips::A2_64, }; // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Bit set. const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, }; // ACC64 Register Class... const MCPhysReg ACC64[] = { Mips::AC0, }; // ACC64 Bit set. const uint8_t ACC64Bits[] = { 0x00, 0x00, 0x00, 0x04, }; // GP64 Register Class... const MCPhysReg GP64[] = { Mips::GP_64, }; // GP64 Bit set. const uint8_t GP64Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, }; // GPR64_with_sub_32_in_CPURAReg Register Class... const MCPhysReg GPR64_with_sub_32_in_CPURAReg[] = { Mips::RA_64, }; // GPR64_with_sub_32_in_CPURAReg Bit set. const uint8_t GPR64_with_sub_32_in_CPURARegBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, }; // GPR64_with_sub_32_in_GPR32ZERO Register Class... const MCPhysReg GPR64_with_sub_32_in_GPR32ZERO[] = { Mips::ZERO_64, }; // GPR64_with_sub_32_in_GPR32ZERO Bit set. const uint8_t GPR64_with_sub_32_in_GPR32ZEROBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, }; // HI64 Register Class... const MCPhysReg HI64[] = { Mips::HI0_64, }; // HI64 Bit set. const uint8_t HI64Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, }; // LO64 Register Class... const MCPhysReg LO64[] = { Mips::LO0_64, }; // LO64 Bit set. const uint8_t LO64Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, }; // SP64 Register Class... const MCPhysReg SP64[] = { Mips::SP_64, }; // SP64 Bit set. const uint8_t SP64Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, }; // MSA128B Register Class... const MCPhysReg MSA128B[] = { Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31, }; // MSA128B Bit set. const uint8_t MSA128BBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, }; // MSA128D Register Class... const MCPhysReg MSA128D[] = { Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31, }; // MSA128D Bit set. const uint8_t MSA128DBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, }; // MSA128H Register Class... const MCPhysReg MSA128H[] = { Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31, }; // MSA128H Bit set. const uint8_t MSA128HBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, }; // MSA128W Register Class... const MCPhysReg MSA128W[] = { Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31, }; // MSA128W Bit set. const uint8_t MSA128WBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, }; // MSA128WEvens Register Class... const MCPhysReg MSA128WEvens[] = { Mips::W0, Mips::W2, Mips::W4, Mips::W6, Mips::W8, Mips::W10, Mips::W12, Mips::W14, Mips::W16, Mips::W18, Mips::W20, Mips::W22, Mips::W24, Mips::W26, Mips::W28, Mips::W30, }; // MSA128WEvens Bit set. const uint8_t MSA128WEvensBits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0xaa, 0xaa, 0xaa, 0x02, }; // ACC128 Register Class... const MCPhysReg ACC128[] = { Mips::AC0_64, }; // ACC128 Bit set. const uint8_t ACC128Bits[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, }; } // end anonymous namespace extern const char MipsRegClassStrings[] = { /* 0 */ 'C', 'O', 'P', '0', 0, /* 5 */ 'H', 'I', '3', '2', 0, /* 10 */ 'L', 'O', '3', '2', 0, /* 15 */ 'G', 'P', '3', '2', 0, /* 20 */ 'S', 'P', '3', '2', 0, /* 25 */ 'F', 'G', 'R', '3', '2', 0, /* 31 */ 'G', 'P', 'R', '3', '2', 0, /* 37 */ 'C', 'O', 'P', '2', 0, /* 42 */ 'C', 'O', 'P', '3', 0, /* 47 */ 'A', 'C', 'C', '6', '4', 0, /* 53 */ 'H', 'I', '6', '4', 0, /* 58 */ 'L', 'O', '6', '4', 0, /* 63 */ 'G', 'P', '6', '4', 0, /* 68 */ 'S', 'P', '6', '4', 0, /* 73 */ 'A', 'F', 'G', 'R', '6', '4', 0, /* 80 */ 'G', 'P', 'R', '6', '4', 0, /* 86 */ 'M', 'S', 'A', '1', '2', '8', 'F', '1', '6', 0, /* 96 */ 'G', 'P', 'R', 'M', 'M', '1', '6', 0, /* 104 */ 'A', 'C', 'C', '1', '2', '8', 0, /* 111 */ 'M', 'S', 'A', '1', '2', '8', 'B', 0, /* 119 */ 'F', 'C', 'C', 0, /* 123 */ 'D', 'S', 'P', 'C', 'C', 0, /* 129 */ 'F', 'G', 'R', 'C', 'C', 0, /* 135 */ 'M', 'S', 'A', '1', '2', '8', 'D', 0, /* 143 */ 'M', 'S', 'A', '1', '2', '8', 'H', 0, /* 151 */ 'O', 'C', 'T', 'E', 'O', 'N', '_', 'M', 'P', 'L', 0, /* 162 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'Z', 'E', 'R', 'O', 0, /* 193 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'N', 'O', 'N', 'Z', 'E', 'R', 'O', 0, /* 227 */ 'H', 'I', '3', '2', 'D', 'S', 'P', 0, /* 235 */ 'L', 'O', '3', '2', 'D', 'S', 'P', 0, /* 243 */ 'A', 'C', 'C', '6', '4', 'D', 'S', 'P', 0, /* 252 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', 'P', 'l', 'u', 's', 'S', 'P', 0, /* 289 */ 'O', 'C', 'T', 'E', 'O', 'N', '_', 'P', 0, /* 298 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'N', 'O', 'N', 'Z', 'E', 'R', 'O', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 0, /* 349 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 0, /* 397 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 0, /* 431 */ 'C', 'C', 'R', 0, /* 435 */ 'D', 'S', 'P', 'R', 0, /* 440 */ 'M', 'S', 'A', '1', '2', '8', 'W', 0, /* 448 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 'P', 'a', 'i', 'r', 'S', 'e', 'c', 'o', 'n', 'd', 0, /* 506 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 'P', 'a', 'i', 'r', 'F', 'i', 'r', 's', 't', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 'P', 'a', 'i', 'r', 'S', 'e', 'c', 'o', 'n', 'd', 0, /* 576 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 'P', 'a', 'i', 'r', 'S', 'e', 'c', 'o', 'n', 'd', 0, /* 620 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', 'R', 'A', 'R', 'e', 'g', 0, /* 650 */ 'C', 'P', 'U', 'S', 'P', 'R', 'e', 'g', 0, /* 659 */ 'M', 'S', 'A', 'C', 't', 'r', 'l', 0, /* 667 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0, /* 717 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', '_', 'a', 'n', 'd', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0, /* 781 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', '_', 'a', 'n', 'd', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0, /* 828 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'Z', 'e', 'r', 'o', 0, /* 861 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'C', 'P', 'U', '1', '6', 'R', 'e', 'g', 's', 0, /* 892 */ 'H', 'W', 'R', 'e', 'g', 's', 0, /* 899 */ 'M', 'S', 'A', '1', '2', '8', 'W', 'E', 'v', 'e', 'n', 's', 0, /* 912 */ 'G', 'P', 'R', '6', '4', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', 'M', 'M', '1', '6', 'M', 'o', 'v', 'e', 'P', 'P', 'a', 'i', 'r', 'F', 'i', 'r', 's', 't', 0, }; extern const MCRegisterClass MipsMCRegisterClasses[] = { { MSA128F16, MSA128F16Bits, 86, 32, sizeof(MSA128F16Bits), Mips::MSA128F16RegClassID, 1, true }, { CCR, CCRBits, 431, 32, sizeof(CCRBits), Mips::CCRRegClassID, 1, false }, { COP0, COP0Bits, 0, 32, sizeof(COP0Bits), Mips::COP0RegClassID, 1, false }, { COP2, COP2Bits, 37, 32, sizeof(COP2Bits), Mips::COP2RegClassID, 1, false }, { COP3, COP3Bits, 42, 32, sizeof(COP3Bits), Mips::COP3RegClassID, 1, false }, { DSPR, DSPRBits, 435, 32, sizeof(DSPRBits), Mips::DSPRRegClassID, 1, true }, { FGR32, FGR32Bits, 25, 32, sizeof(FGR32Bits), Mips::FGR32RegClassID, 1, true }, { FGRCC, FGRCCBits, 129, 32, sizeof(FGRCCBits), Mips::FGRCCRegClassID, 1, true }, { GPR32, GPR32Bits, 31, 32, sizeof(GPR32Bits), Mips::GPR32RegClassID, 1, true }, { HWRegs, HWRegsBits, 892, 32, sizeof(HWRegsBits), Mips::HWRegsRegClassID, 1, false }, { MSACtrl, MSACtrlBits, 659, 32, sizeof(MSACtrlBits), Mips::MSACtrlRegClassID, 1, false }, { GPR32NONZERO, GPR32NONZEROBits, 214, 31, sizeof(GPR32NONZEROBits), Mips::GPR32NONZERORegClassID, 1, true }, { CPU16RegsPlusSP, CPU16RegsPlusSPBits, 273, 9, sizeof(CPU16RegsPlusSPBits), Mips::CPU16RegsPlusSPRegClassID, 1, true }, { CPU16Regs, CPU16RegsBits, 882, 8, sizeof(CPU16RegsBits), Mips::CPU16RegsRegClassID, 1, true }, { FCC, FCCBits, 119, 8, sizeof(FCCBits), Mips::FCCRegClassID, 1, false }, { GPRMM16, GPRMM16Bits, 96, 8, sizeof(GPRMM16Bits), Mips::GPRMM16RegClassID, 1, true }, { GPRMM16MoveP, GPRMM16MovePBits, 336, 8, sizeof(GPRMM16MovePBits), Mips::GPRMM16MovePRegClassID, 1, true }, { GPRMM16Zero, GPRMM16ZeroBits, 705, 8, sizeof(GPRMM16ZeroBits), Mips::GPRMM16ZeroRegClassID, 1, true }, { CPU16Regs_and_GPRMM16Zero, CPU16Regs_and_GPRMM16ZeroBits, 755, 7, sizeof(CPU16Regs_and_GPRMM16ZeroBits), Mips::CPU16Regs_and_GPRMM16ZeroRegClassID, 1, true }, { GPR32NONZERO_and_GPRMM16MoveP, GPR32NONZERO_and_GPRMM16MovePBits, 319, 7, sizeof(GPR32NONZERO_and_GPRMM16MovePBits), Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID, 1, true }, { GPRMM16MovePPairSecond, GPRMM16MovePPairSecondBits, 483, 5, sizeof(GPRMM16MovePPairSecondBits), Mips::GPRMM16MovePPairSecondRegClassID, 1, true }, { CPU16Regs_and_GPRMM16MoveP, CPU16Regs_and_GPRMM16MovePBits, 370, 4, sizeof(CPU16Regs_and_GPRMM16MovePBits), Mips::CPU16Regs_and_GPRMM16MovePRegClassID, 1, true }, { GPRMM16MoveP_and_GPRMM16Zero, GPRMM16MoveP_and_GPRMM16ZeroBits, 688, 4, sizeof(GPRMM16MoveP_and_GPRMM16ZeroBits), Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 1, true }, { HI32DSP, HI32DSPBits, 227, 4, sizeof(HI32DSPBits), Mips::HI32DSPRegClassID, 1, true }, { LO32DSP, LO32DSPBits, 235, 4, sizeof(LO32DSPBits), Mips::LO32DSPRegClassID, 1, true }, { CPU16Regs_and_GPRMM16MovePPairSecond, CPU16Regs_and_GPRMM16MovePPairSecondBits, 469, 3, sizeof(CPU16Regs_and_GPRMM16MovePPairSecondBits), Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID, 1, true }, { GPRMM16MovePPairFirst, GPRMM16MovePPairFirstBits, 933, 3, sizeof(GPRMM16MovePPairFirstBits), Mips::GPRMM16MovePPairFirstRegClassID, 1, true }, { GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 738, 3, sizeof(GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 1, true }, { GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond, GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits, 527, 2, sizeof(GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits), Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID, 1, true }, { CPURAReg, CPURARegBits, 641, 1, sizeof(CPURARegBits), Mips::CPURARegRegClassID, 1, false }, { CPUSPReg, CPUSPRegBits, 650, 1, sizeof(CPUSPRegBits), Mips::CPUSPRegRegClassID, 1, false }, { DSPCC, DSPCCBits, 123, 1, sizeof(DSPCCBits), Mips::DSPCCRegClassID, 1, true }, { GP32, GP32Bits, 15, 1, sizeof(GP32Bits), Mips::GP32RegClassID, 1, false }, { GPR32ZERO, GPR32ZEROBits, 183, 1, sizeof(GPR32ZEROBits), Mips::GPR32ZERORegClassID, 1, true }, { HI32, HI32Bits, 5, 1, sizeof(HI32Bits), Mips::HI32RegClassID, 1, true }, { LO32, LO32Bits, 10, 1, sizeof(LO32Bits), Mips::LO32RegClassID, 1, true }, { SP32, SP32Bits, 20, 1, sizeof(SP32Bits), Mips::SP32RegClassID, 1, false }, { FGR64, FGR64Bits, 74, 32, sizeof(FGR64Bits), Mips::FGR64RegClassID, 1, true }, { GPR64, GPR64Bits, 80, 32, sizeof(GPR64Bits), Mips::GPR64RegClassID, 1, true }, { GPR64_with_sub_32_in_GPR32NONZERO, GPR64_with_sub_32_in_GPR32NONZEROBits, 193, 31, sizeof(GPR64_with_sub_32_in_GPR32NONZEROBits), Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, 1, true }, { AFGR64, AFGR64Bits, 73, 16, sizeof(AFGR64Bits), Mips::AFGR64RegClassID, 1, true }, { GPR64_with_sub_32_in_CPU16RegsPlusSP, GPR64_with_sub_32_in_CPU16RegsPlusSPBits, 252, 9, sizeof(GPR64_with_sub_32_in_CPU16RegsPlusSPBits), Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID, 1, true }, { GPR64_with_sub_32_in_CPU16Regs, GPR64_with_sub_32_in_CPU16RegsBits, 861, 8, sizeof(GPR64_with_sub_32_in_CPU16RegsBits), Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID, 1, true }, { GPR64_with_sub_32_in_GPRMM16MoveP, GPR64_with_sub_32_in_GPRMM16MovePBits, 397, 8, sizeof(GPR64_with_sub_32_in_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID, 1, true }, { GPR64_with_sub_32_in_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16ZeroBits, 828, 8, sizeof(GPR64_with_sub_32_in_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID, 1, true }, { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits, 781, 7, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID, 1, true }, { GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP, GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits, 298, 7, sizeof(GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID, 1, true }, { GPR64_with_sub_32_in_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits, 576, 5, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID, 1, true }, { ACC64DSP, ACC64DSPBits, 243, 4, sizeof(ACC64DSPBits), Mips::ACC64DSPRegClassID, 1, true }, { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits, 349, 4, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID, 1, true }, { GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits, 667, 4, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 1, true }, { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits, 448, 3, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID, 1, true }, { GPR64_with_sub_32_in_GPRMM16MovePPairFirst, GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits, 912, 3, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID, 1, true }, { GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 717, 3, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 1, true }, { OCTEON_MPL, OCTEON_MPLBits, 151, 3, sizeof(OCTEON_MPLBits), Mips::OCTEON_MPLRegClassID, 1, false }, { OCTEON_P, OCTEON_PBits, 289, 3, sizeof(OCTEON_PBits), Mips::OCTEON_PRegClassID, 1, false }, { GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits, 506, 2, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID, 1, true }, { ACC64, ACC64Bits, 47, 1, sizeof(ACC64Bits), Mips::ACC64RegClassID, 1, true }, { GP64, GP64Bits, 63, 1, sizeof(GP64Bits), Mips::GP64RegClassID, 1, false }, { GPR64_with_sub_32_in_CPURAReg, GPR64_with_sub_32_in_CPURARegBits, 620, 1, sizeof(GPR64_with_sub_32_in_CPURARegBits), Mips::GPR64_with_sub_32_in_CPURARegRegClassID, 1, true }, { GPR64_with_sub_32_in_GPR32ZERO, GPR64_with_sub_32_in_GPR32ZEROBits, 162, 1, sizeof(GPR64_with_sub_32_in_GPR32ZEROBits), Mips::GPR64_with_sub_32_in_GPR32ZERORegClassID, 1, true }, { HI64, HI64Bits, 53, 1, sizeof(HI64Bits), Mips::HI64RegClassID, 1, true }, { LO64, LO64Bits, 58, 1, sizeof(LO64Bits), Mips::LO64RegClassID, 1, true }, { SP64, SP64Bits, 68, 1, sizeof(SP64Bits), Mips::SP64RegClassID, 1, false }, { MSA128B, MSA128BBits, 111, 32, sizeof(MSA128BBits), Mips::MSA128BRegClassID, 1, true }, { MSA128D, MSA128DBits, 135, 32, sizeof(MSA128DBits), Mips::MSA128DRegClassID, 1, true }, { MSA128H, MSA128HBits, 143, 32, sizeof(MSA128HBits), Mips::MSA128HRegClassID, 1, true }, { MSA128W, MSA128WBits, 440, 32, sizeof(MSA128WBits), Mips::MSA128WRegClassID, 1, true }, { MSA128WEvens, MSA128WEvensBits, 899, 16, sizeof(MSA128WEvensBits), Mips::MSA128WEvensRegClassID, 1, true }, { ACC128, ACC128Bits, 104, 1, sizeof(ACC128Bits), Mips::ACC128RegClassID, 1, true }, }; // Mips Dwarf<->LLVM register mappings. extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[] = { { 0U, Mips::ZERO_64 }, { 1U, Mips::AT_64 }, { 2U, Mips::V0_64 }, { 3U, Mips::V1_64 }, { 4U, Mips::A0_64 }, { 5U, Mips::A1_64 }, { 6U, Mips::A2_64 }, { 7U, Mips::A3_64 }, { 8U, Mips::T0_64 }, { 9U, Mips::T1_64 }, { 10U, Mips::T2_64 }, { 11U, Mips::T3_64 }, { 12U, Mips::T4_64 }, { 13U, Mips::T5_64 }, { 14U, Mips::T6_64 }, { 15U, Mips::T7_64 }, { 16U, Mips::S0_64 }, { 17U, Mips::S1_64 }, { 18U, Mips::S2_64 }, { 19U, Mips::S3_64 }, { 20U, Mips::S4_64 }, { 21U, Mips::S5_64 }, { 22U, Mips::S6_64 }, { 23U, Mips::S7_64 }, { 24U, Mips::T8_64 }, { 25U, Mips::T9_64 }, { 26U, Mips::K0_64 }, { 27U, Mips::K1_64 }, { 28U, Mips::GP_64 }, { 29U, Mips::SP_64 }, { 30U, Mips::FP_64 }, { 31U, Mips::RA_64 }, { 32U, Mips::D0_64 }, { 33U, Mips::D1_64 }, { 34U, Mips::D2_64 }, { 35U, Mips::D3_64 }, { 36U, Mips::D4_64 }, { 37U, Mips::D5_64 }, { 38U, Mips::D6_64 }, { 39U, Mips::D7_64 }, { 40U, Mips::D8_64 }, { 41U, Mips::D9_64 }, { 42U, Mips::D10_64 }, { 43U, Mips::D11_64 }, { 44U, Mips::D12_64 }, { 45U, Mips::D13_64 }, { 46U, Mips::D14_64 }, { 47U, Mips::D15_64 }, { 48U, Mips::D16_64 }, { 49U, Mips::D17_64 }, { 50U, Mips::D18_64 }, { 51U, Mips::D19_64 }, { 52U, Mips::D20_64 }, { 53U, Mips::D21_64 }, { 54U, Mips::D22_64 }, { 55U, Mips::D23_64 }, { 56U, Mips::D24_64 }, { 57U, Mips::D25_64 }, { 58U, Mips::D26_64 }, { 59U, Mips::D27_64 }, { 60U, Mips::D28_64 }, { 61U, Mips::D29_64 }, { 62U, Mips::D30_64 }, { 63U, Mips::D31_64 }, { 64U, Mips::HI0 }, { 65U, Mips::LO0 }, { 176U, Mips::HI1 }, { 177U, Mips::LO1 }, { 178U, Mips::HI2 }, { 179U, Mips::LO2 }, { 180U, Mips::HI3 }, { 181U, Mips::LO3 }, }; extern const unsigned MipsDwarfFlavour0Dwarf2LSize = array_lengthof(MipsDwarfFlavour0Dwarf2L); extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[] = { { 0U, Mips::ZERO_64 }, { 1U, Mips::AT_64 }, { 2U, Mips::V0_64 }, { 3U, Mips::V1_64 }, { 4U, Mips::A0_64 }, { 5U, Mips::A1_64 }, { 6U, Mips::A2_64 }, { 7U, Mips::A3_64 }, { 8U, Mips::T0_64 }, { 9U, Mips::T1_64 }, { 10U, Mips::T2_64 }, { 11U, Mips::T3_64 }, { 12U, Mips::T4_64 }, { 13U, Mips::T5_64 }, { 14U, Mips::T6_64 }, { 15U, Mips::T7_64 }, { 16U, Mips::S0_64 }, { 17U, Mips::S1_64 }, { 18U, Mips::S2_64 }, { 19U, Mips::S3_64 }, { 20U, Mips::S4_64 }, { 21U, Mips::S5_64 }, { 22U, Mips::S6_64 }, { 23U, Mips::S7_64 }, { 24U, Mips::T8_64 }, { 25U, Mips::T9_64 }, { 26U, Mips::K0_64 }, { 27U, Mips::K1_64 }, { 28U, Mips::GP_64 }, { 29U, Mips::SP_64 }, { 30U, Mips::FP_64 }, { 31U, Mips::RA_64 }, { 32U, Mips::D0_64 }, { 33U, Mips::D1_64 }, { 34U, Mips::D2_64 }, { 35U, Mips::D3_64 }, { 36U, Mips::D4_64 }, { 37U, Mips::D5_64 }, { 38U, Mips::D6_64 }, { 39U, Mips::D7_64 }, { 40U, Mips::D8_64 }, { 41U, Mips::D9_64 }, { 42U, Mips::D10_64 }, { 43U, Mips::D11_64 }, { 44U, Mips::D12_64 }, { 45U, Mips::D13_64 }, { 46U, Mips::D14_64 }, { 47U, Mips::D15_64 }, { 48U, Mips::D16_64 }, { 49U, Mips::D17_64 }, { 50U, Mips::D18_64 }, { 51U, Mips::D19_64 }, { 52U, Mips::D20_64 }, { 53U, Mips::D21_64 }, { 54U, Mips::D22_64 }, { 55U, Mips::D23_64 }, { 56U, Mips::D24_64 }, { 57U, Mips::D25_64 }, { 58U, Mips::D26_64 }, { 59U, Mips::D27_64 }, { 60U, Mips::D28_64 }, { 61U, Mips::D29_64 }, { 62U, Mips::D30_64 }, { 63U, Mips::D31_64 }, { 64U, Mips::HI0 }, { 65U, Mips::LO0 }, { 176U, Mips::HI1 }, { 177U, Mips::LO1 }, { 178U, Mips::HI2 }, { 179U, Mips::LO2 }, { 180U, Mips::HI3 }, { 181U, Mips::LO3 }, }; extern const unsigned MipsEHFlavour0Dwarf2LSize = array_lengthof(MipsEHFlavour0Dwarf2L); extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[] = { { Mips::AT, 1U }, { Mips::FP, 30U }, { Mips::GP, 28U }, { Mips::RA, 31U }, { Mips::SP, 29U }, { Mips::ZERO, 0U }, { Mips::A0, 4U }, { Mips::A1, 5U }, { Mips::A2, 6U }, { Mips::A3, 7U }, { Mips::AT_64, 1U }, { Mips::F0, 32U }, { Mips::F1, 33U }, { Mips::F2, 34U }, { Mips::F3, 35U }, { Mips::F4, 36U }, { Mips::F5, 37U }, { Mips::F6, 38U }, { Mips::F7, 39U }, { Mips::F8, 40U }, { Mips::F9, 41U }, { Mips::F10, 42U }, { Mips::F11, 43U }, { Mips::F12, 44U }, { Mips::F13, 45U }, { Mips::F14, 46U }, { Mips::F15, 47U }, { Mips::F16, 48U }, { Mips::F17, 49U }, { Mips::F18, 50U }, { Mips::F19, 51U }, { Mips::F20, 52U }, { Mips::F21, 53U }, { Mips::F22, 54U }, { Mips::F23, 55U }, { Mips::F24, 56U }, { Mips::F25, 57U }, { Mips::F26, 58U }, { Mips::F27, 59U }, { Mips::F28, 60U }, { Mips::F29, 61U }, { Mips::F30, 62U }, { Mips::F31, 63U }, { Mips::FP_64, 30U }, { Mips::F_HI0, 32U }, { Mips::F_HI1, 33U }, { Mips::F_HI2, 34U }, { Mips::F_HI3, 35U }, { Mips::F_HI4, 36U }, { Mips::F_HI5, 37U }, { Mips::F_HI6, 38U }, { Mips::F_HI7, 39U }, { Mips::F_HI8, 40U }, { Mips::F_HI9, 41U }, { Mips::F_HI10, 42U }, { Mips::F_HI11, 43U }, { Mips::F_HI12, 44U }, { Mips::F_HI13, 45U }, { Mips::F_HI14, 46U }, { Mips::F_HI15, 47U }, { Mips::F_HI16, 48U }, { Mips::F_HI17, 49U }, { Mips::F_HI18, 50U }, { Mips::F_HI19, 51U }, { Mips::F_HI20, 52U }, { Mips::F_HI21, 53U }, { Mips::F_HI22, 54U }, { Mips::F_HI23, 55U }, { Mips::F_HI24, 56U }, { Mips::F_HI25, 57U }, { Mips::F_HI26, 58U }, { Mips::F_HI27, 59U }, { Mips::F_HI28, 60U }, { Mips::F_HI29, 61U }, { Mips::F_HI30, 62U }, { Mips::F_HI31, 63U }, { Mips::GP_64, 28U }, { Mips::HI0, 64U }, { Mips::HI1, 176U }, { Mips::HI2, 178U }, { Mips::HI3, 180U }, { Mips::K0, 26U }, { Mips::K1, 27U }, { Mips::LO0, 65U }, { Mips::LO1, 177U }, { Mips::LO2, 179U }, { Mips::LO3, 181U }, { Mips::RA_64, 31U }, { Mips::S0, 16U }, { Mips::S1, 17U }, { Mips::S2, 18U }, { Mips::S3, 19U }, { Mips::S4, 20U }, { Mips::S5, 21U }, { Mips::S6, 22U }, { Mips::S7, 23U }, { Mips::SP_64, 29U }, { Mips::T0, 8U }, { Mips::T1, 9U }, { Mips::T2, 10U }, { Mips::T3, 11U }, { Mips::T4, 12U }, { Mips::T5, 13U }, { Mips::T6, 14U }, { Mips::T7, 15U }, { Mips::T8, 24U }, { Mips::T9, 25U }, { Mips::V0, 2U }, { Mips::V1, 3U }, { Mips::W0, 32U }, { Mips::W1, 33U }, { Mips::W2, 34U }, { Mips::W3, 35U }, { Mips::W4, 36U }, { Mips::W5, 37U }, { Mips::W6, 38U }, { Mips::W7, 39U }, { Mips::W8, 40U }, { Mips::W9, 41U }, { Mips::W10, 42U }, { Mips::W11, 43U }, { Mips::W12, 44U }, { Mips::W13, 45U }, { Mips::W14, 46U }, { Mips::W15, 47U }, { Mips::W16, 48U }, { Mips::W17, 49U }, { Mips::W18, 50U }, { Mips::W19, 51U }, { Mips::W20, 52U }, { Mips::W21, 53U }, { Mips::W22, 54U }, { Mips::W23, 55U }, { Mips::W24, 56U }, { Mips::W25, 57U }, { Mips::W26, 58U }, { Mips::W27, 59U }, { Mips::W28, 60U }, { Mips::W29, 61U }, { Mips::W30, 62U }, { Mips::W31, 63U }, { Mips::ZERO_64, 0U }, { Mips::A0_64, 4U }, { Mips::A1_64, 5U }, { Mips::A2_64, 6U }, { Mips::A3_64, 7U }, { Mips::D0_64, 32U }, { Mips::D1_64, 33U }, { Mips::D2_64, 34U }, { Mips::D3_64, 35U }, { Mips::D4_64, 36U }, { Mips::D5_64, 37U }, { Mips::D6_64, 38U }, { Mips::D7_64, 39U }, { Mips::D8_64, 40U }, { Mips::D9_64, 41U }, { Mips::D10_64, 42U }, { Mips::D11_64, 43U }, { Mips::D12_64, 44U }, { Mips::D13_64, 45U }, { Mips::D14_64, 46U }, { Mips::D15_64, 47U }, { Mips::D16_64, 48U }, { Mips::D17_64, 49U }, { Mips::D18_64, 50U }, { Mips::D19_64, 51U }, { Mips::D20_64, 52U }, { Mips::D21_64, 53U }, { Mips::D22_64, 54U }, { Mips::D23_64, 55U }, { Mips::D24_64, 56U }, { Mips::D25_64, 57U }, { Mips::D26_64, 58U }, { Mips::D27_64, 59U }, { Mips::D28_64, 60U }, { Mips::D29_64, 61U }, { Mips::D30_64, 62U }, { Mips::D31_64, 63U }, { Mips::K0_64, 26U }, { Mips::K1_64, 27U }, { Mips::S0_64, 16U }, { Mips::S1_64, 17U }, { Mips::S2_64, 18U }, { Mips::S3_64, 19U }, { Mips::S4_64, 20U }, { Mips::S5_64, 21U }, { Mips::S6_64, 22U }, { Mips::S7_64, 23U }, { Mips::T0_64, 8U }, { Mips::T1_64, 9U }, { Mips::T2_64, 10U }, { Mips::T3_64, 11U }, { Mips::T4_64, 12U }, { Mips::T5_64, 13U }, { Mips::T6_64, 14U }, { Mips::T7_64, 15U }, { Mips::T8_64, 24U }, { Mips::T9_64, 25U }, { Mips::V0_64, 2U }, { Mips::V1_64, 3U }, }; extern const unsigned MipsDwarfFlavour0L2DwarfSize = array_lengthof(MipsDwarfFlavour0L2Dwarf); extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[] = { { Mips::AT, 1U }, { Mips::FP, 30U }, { Mips::GP, 28U }, { Mips::RA, 31U }, { Mips::SP, 29U }, { Mips::ZERO, 0U }, { Mips::A0, 4U }, { Mips::A1, 5U }, { Mips::A2, 6U }, { Mips::A3, 7U }, { Mips::AT_64, 1U }, { Mips::F0, 32U }, { Mips::F1, 33U }, { Mips::F2, 34U }, { Mips::F3, 35U }, { Mips::F4, 36U }, { Mips::F5, 37U }, { Mips::F6, 38U }, { Mips::F7, 39U }, { Mips::F8, 40U }, { Mips::F9, 41U }, { Mips::F10, 42U }, { Mips::F11, 43U }, { Mips::F12, 44U }, { Mips::F13, 45U }, { Mips::F14, 46U }, { Mips::F15, 47U }, { Mips::F16, 48U }, { Mips::F17, 49U }, { Mips::F18, 50U }, { Mips::F19, 51U }, { Mips::F20, 52U }, { Mips::F21, 53U }, { Mips::F22, 54U }, { Mips::F23, 55U }, { Mips::F24, 56U }, { Mips::F25, 57U }, { Mips::F26, 58U }, { Mips::F27, 59U }, { Mips::F28, 60U }, { Mips::F29, 61U }, { Mips::F30, 62U }, { Mips::F31, 63U }, { Mips::FP_64, 30U }, { Mips::F_HI0, 32U }, { Mips::F_HI1, 33U }, { Mips::F_HI2, 34U }, { Mips::F_HI3, 35U }, { Mips::F_HI4, 36U }, { Mips::F_HI5, 37U }, { Mips::F_HI6, 38U }, { Mips::F_HI7, 39U }, { Mips::F_HI8, 40U }, { Mips::F_HI9, 41U }, { Mips::F_HI10, 42U }, { Mips::F_HI11, 43U }, { Mips::F_HI12, 44U }, { Mips::F_HI13, 45U }, { Mips::F_HI14, 46U }, { Mips::F_HI15, 47U }, { Mips::F_HI16, 48U }, { Mips::F_HI17, 49U }, { Mips::F_HI18, 50U }, { Mips::F_HI19, 51U }, { Mips::F_HI20, 52U }, { Mips::F_HI21, 53U }, { Mips::F_HI22, 54U }, { Mips::F_HI23, 55U }, { Mips::F_HI24, 56U }, { Mips::F_HI25, 57U }, { Mips::F_HI26, 58U }, { Mips::F_HI27, 59U }, { Mips::F_HI28, 60U }, { Mips::F_HI29, 61U }, { Mips::F_HI30, 62U }, { Mips::F_HI31, 63U }, { Mips::GP_64, 28U }, { Mips::HI0, 64U }, { Mips::HI1, 176U }, { Mips::HI2, 178U }, { Mips::HI3, 180U }, { Mips::K0, 26U }, { Mips::K1, 27U }, { Mips::LO0, 65U }, { Mips::LO1, 177U }, { Mips::LO2, 179U }, { Mips::LO3, 181U }, { Mips::RA_64, 31U }, { Mips::S0, 16U }, { Mips::S1, 17U }, { Mips::S2, 18U }, { Mips::S3, 19U }, { Mips::S4, 20U }, { Mips::S5, 21U }, { Mips::S6, 22U }, { Mips::S7, 23U }, { Mips::SP_64, 29U }, { Mips::T0, 8U }, { Mips::T1, 9U }, { Mips::T2, 10U }, { Mips::T3, 11U }, { Mips::T4, 12U }, { Mips::T5, 13U }, { Mips::T6, 14U }, { Mips::T7, 15U }, { Mips::T8, 24U }, { Mips::T9, 25U }, { Mips::V0, 2U }, { Mips::V1, 3U }, { Mips::W0, 32U }, { Mips::W1, 33U }, { Mips::W2, 34U }, { Mips::W3, 35U }, { Mips::W4, 36U }, { Mips::W5, 37U }, { Mips::W6, 38U }, { Mips::W7, 39U }, { Mips::W8, 40U }, { Mips::W9, 41U }, { Mips::W10, 42U }, { Mips::W11, 43U }, { Mips::W12, 44U }, { Mips::W13, 45U }, { Mips::W14, 46U }, { Mips::W15, 47U }, { Mips::W16, 48U }, { Mips::W17, 49U }, { Mips::W18, 50U }, { Mips::W19, 51U }, { Mips::W20, 52U }, { Mips::W21, 53U }, { Mips::W22, 54U }, { Mips::W23, 55U }, { Mips::W24, 56U }, { Mips::W25, 57U }, { Mips::W26, 58U }, { Mips::W27, 59U }, { Mips::W28, 60U }, { Mips::W29, 61U }, { Mips::W30, 62U }, { Mips::W31, 63U }, { Mips::ZERO_64, 0U }, { Mips::A0_64, 4U }, { Mips::A1_64, 5U }, { Mips::A2_64, 6U }, { Mips::A3_64, 7U }, { Mips::D0_64, 32U }, { Mips::D1_64, 33U }, { Mips::D2_64, 34U }, { Mips::D3_64, 35U }, { Mips::D4_64, 36U }, { Mips::D5_64, 37U }, { Mips::D6_64, 38U }, { Mips::D7_64, 39U }, { Mips::D8_64, 40U }, { Mips::D9_64, 41U }, { Mips::D10_64, 42U }, { Mips::D11_64, 43U }, { Mips::D12_64, 44U }, { Mips::D13_64, 45U }, { Mips::D14_64, 46U }, { Mips::D15_64, 47U }, { Mips::D16_64, 48U }, { Mips::D17_64, 49U }, { Mips::D18_64, 50U }, { Mips::D19_64, 51U }, { Mips::D20_64, 52U }, { Mips::D21_64, 53U }, { Mips::D22_64, 54U }, { Mips::D23_64, 55U }, { Mips::D24_64, 56U }, { Mips::D25_64, 57U }, { Mips::D26_64, 58U }, { Mips::D27_64, 59U }, { Mips::D28_64, 60U }, { Mips::D29_64, 61U }, { Mips::D30_64, 62U }, { Mips::D31_64, 63U }, { Mips::K0_64, 26U }, { Mips::K1_64, 27U }, { Mips::S0_64, 16U }, { Mips::S1_64, 17U }, { Mips::S2_64, 18U }, { Mips::S3_64, 19U }, { Mips::S4_64, 20U }, { Mips::S5_64, 21U }, { Mips::S6_64, 22U }, { Mips::S7_64, 23U }, { Mips::T0_64, 8U }, { Mips::T1_64, 9U }, { Mips::T2_64, 10U }, { Mips::T3_64, 11U }, { Mips::T4_64, 12U }, { Mips::T5_64, 13U }, { Mips::T6_64, 14U }, { Mips::T7_64, 15U }, { Mips::T8_64, 24U }, { Mips::T9_64, 25U }, { Mips::V0_64, 2U }, { Mips::V1_64, 3U }, }; extern const unsigned MipsEHFlavour0L2DwarfSize = array_lengthof(MipsEHFlavour0L2Dwarf); extern const uint16_t MipsRegEncodingTable[] = { 0, 1, 0, 0, 0, 0, 0, 0, 30, 28, 2, 1, 0, 6, 4, 5, 3, 7, 0, 31, 29, 0, 4, 5, 6, 7, 0, 1, 2, 3, 1, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 0, 0, 0, 0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 30, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 28, 0, 1, 2, 3, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 26, 27, 0, 1, 2, 3, 0, 1, 2, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 0, 1, 2, 31, 16, 17, 18, 19, 20, 21, 22, 23, 29, 8, 9, 10, 11, 12, 13, 14, 15, 24, 25, 2, 3, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 0, 4, 5, 6, 7, 0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 0, 0, 26, 27, 0, 16, 17, 18, 19, 20, 21, 22, 23, 8, 9, 10, 11, 12, 13, 14, 15, 24, 25, 2, 3, }; static inline void InitMipsMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) { RI->InitMCRegisterInfo(MipsRegDesc, 442, RA, PC, MipsMCRegisterClasses, 70, MipsRegUnitRoots, 321, MipsRegDiffLists, MipsLaneMaskLists, MipsRegStrings, MipsRegClassStrings, MipsSubRegIdxLists, 12, MipsSubRegIdxRanges, MipsRegEncodingTable); switch (DwarfFlavour) { default: llvm_unreachable("Unknown DWARF flavour"); case 0: RI->mapDwarfRegsToLLVMRegs(MipsDwarfFlavour0Dwarf2L, MipsDwarfFlavour0Dwarf2LSize, false); break; } switch (EHFlavour) { default: llvm_unreachable("Unknown DWARF flavour"); case 0: RI->mapDwarfRegsToLLVMRegs(MipsEHFlavour0Dwarf2L, MipsEHFlavour0Dwarf2LSize, true); break; } switch (DwarfFlavour) { default: llvm_unreachable("Unknown DWARF flavour"); case 0: RI->mapLLVMRegsToDwarfRegs(MipsDwarfFlavour0L2Dwarf, MipsDwarfFlavour0L2DwarfSize, false); break; } switch (EHFlavour) { default: llvm_unreachable("Unknown DWARF flavour"); case 0: RI->mapLLVMRegsToDwarfRegs(MipsEHFlavour0L2Dwarf, MipsEHFlavour0L2DwarfSize, true); break; } } } // end namespace llvm #endif // GET_REGINFO_MC_DESC /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Register Information Header Fragment *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_REGINFO_HEADER #undef GET_REGINFO_HEADER #include "llvm/CodeGen/TargetRegisterInfo.h" namespace llvm { class MipsFrameLowering; struct MipsGenRegisterInfo : public TargetRegisterInfo { explicit MipsGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0, unsigned PC = 0, unsigned HwMode = 0); unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override; LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override; LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override; const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override; const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override; unsigned getRegUnitWeight(unsigned RegUnit) const override; unsigned getNumRegPressureSets() const override; const char *getRegPressureSetName(unsigned Idx) const override; unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override; const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override; const int *getRegUnitPressureSets(unsigned RegUnit) const override; ArrayRef getRegMaskNames() const override; ArrayRef getRegMasks() const override; /// Devirtualized TargetFrameLowering. static const MipsFrameLowering *getFrameLowering( const MachineFunction &MF); }; namespace Mips { // Register classes extern const TargetRegisterClass MSA128F16RegClass; extern const TargetRegisterClass CCRRegClass; extern const TargetRegisterClass COP0RegClass; extern const TargetRegisterClass COP2RegClass; extern const TargetRegisterClass COP3RegClass; extern const TargetRegisterClass DSPRRegClass; extern const TargetRegisterClass FGR32RegClass; extern const TargetRegisterClass FGRCCRegClass; extern const TargetRegisterClass GPR32RegClass; extern const TargetRegisterClass HWRegsRegClass; extern const TargetRegisterClass MSACtrlRegClass; extern const TargetRegisterClass GPR32NONZERORegClass; extern const TargetRegisterClass CPU16RegsPlusSPRegClass; extern const TargetRegisterClass CPU16RegsRegClass; extern const TargetRegisterClass FCCRegClass; extern const TargetRegisterClass GPRMM16RegClass; extern const TargetRegisterClass GPRMM16MovePRegClass; extern const TargetRegisterClass GPRMM16ZeroRegClass; extern const TargetRegisterClass CPU16Regs_and_GPRMM16ZeroRegClass; extern const TargetRegisterClass GPR32NONZERO_and_GPRMM16MovePRegClass; extern const TargetRegisterClass GPRMM16MovePPairSecondRegClass; extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePRegClass; extern const TargetRegisterClass GPRMM16MoveP_and_GPRMM16ZeroRegClass; extern const TargetRegisterClass HI32DSPRegClass; extern const TargetRegisterClass LO32DSPRegClass; extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePPairSecondRegClass; extern const TargetRegisterClass GPRMM16MovePPairFirstRegClass; extern const TargetRegisterClass GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass; extern const TargetRegisterClass GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass; extern const TargetRegisterClass CPURARegRegClass; extern const TargetRegisterClass CPUSPRegRegClass; extern const TargetRegisterClass DSPCCRegClass; extern const TargetRegisterClass GP32RegClass; extern const TargetRegisterClass GPR32ZERORegClass; extern const TargetRegisterClass HI32RegClass; extern const TargetRegisterClass LO32RegClass; extern const TargetRegisterClass SP32RegClass; extern const TargetRegisterClass FGR64RegClass; extern const TargetRegisterClass GPR64RegClass; extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERORegClass; extern const TargetRegisterClass AFGR64RegClass; extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass; extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsRegClass; extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePRegClass; extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16ZeroRegClass; extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass; extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass; extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass; extern const TargetRegisterClass ACC64DSPRegClass; extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass; extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass; extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass; extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass; extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass; extern const TargetRegisterClass OCTEON_MPLRegClass; extern const TargetRegisterClass OCTEON_PRegClass; extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass; extern const TargetRegisterClass ACC64RegClass; extern const TargetRegisterClass GP64RegClass; extern const TargetRegisterClass GPR64_with_sub_32_in_CPURARegRegClass; extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32ZERORegClass; extern const TargetRegisterClass HI64RegClass; extern const TargetRegisterClass LO64RegClass; extern const TargetRegisterClass SP64RegClass; extern const TargetRegisterClass MSA128BRegClass; extern const TargetRegisterClass MSA128DRegClass; extern const TargetRegisterClass MSA128HRegClass; extern const TargetRegisterClass MSA128WRegClass; extern const TargetRegisterClass MSA128WEvensRegClass; extern const TargetRegisterClass ACC128RegClass; } // end namespace Mips } // end namespace llvm #endif // GET_REGINFO_HEADER /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |* *| |* Target Register and Register Classes Information *| |* *| |* Automatically generated file, do not edit! *| |* *| \*===----------------------------------------------------------------------===*/ #ifdef GET_REGINFO_TARGET_DESC #undef GET_REGINFO_TARGET_DESC namespace llvm { extern const MCRegisterClass MipsMCRegisterClasses[]; static const MVT::SimpleValueType VTLists[] = { /* 0 */ MVT::i32, MVT::Other, /* 2 */ MVT::i64, MVT::Other, /* 4 */ MVT::f16, MVT::Other, /* 6 */ MVT::f32, MVT::Other, /* 8 */ MVT::f64, MVT::Other, /* 10 */ MVT::v16i8, MVT::Other, /* 12 */ MVT::v4i8, MVT::v2i16, MVT::Other, /* 15 */ MVT::v8i16, MVT::v8f16, MVT::Other, /* 18 */ MVT::v4i32, MVT::v4f32, MVT::Other, /* 21 */ MVT::v2i64, MVT::v2f64, MVT::Other, /* 24 */ MVT::Untyped, MVT::Other, }; static const char *const SubRegIndexNameTable[] = { "sub_32", "sub_64", "sub_dsp16_19", "sub_dsp20", "sub_dsp21", "sub_dsp22", "sub_dsp23", "sub_hi", "sub_lo", "sub_hi_then_sub_32", "sub_32_sub_hi_then_sub_32", "" }; static const LaneBitmask SubRegIndexLaneMaskTable[] = { LaneBitmask::getAll(), LaneBitmask(0x00000001), // sub_32 LaneBitmask(0x00000041), // sub_64 LaneBitmask(0x00000002), // sub_dsp16_19 LaneBitmask(0x00000004), // sub_dsp20 LaneBitmask(0x00000008), // sub_dsp21 LaneBitmask(0x00000010), // sub_dsp22 LaneBitmask(0x00000020), // sub_dsp23 LaneBitmask(0x00000040), // sub_hi LaneBitmask(0x00000001), // sub_lo LaneBitmask(0x00000040), // sub_hi_then_sub_32 LaneBitmask(0x00000041), // sub_32_sub_hi_then_sub_32 }; static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = { // Mode = 0 (Default) { 16, 16, 128, VTLists+4 }, // MSA128F16 { 32, 32, 32, VTLists+0 }, // CCR { 32, 32, 32, VTLists+0 }, // COP0 { 32, 32, 32, VTLists+0 }, // COP2 { 32, 32, 32, VTLists+0 }, // COP3 { 32, 32, 32, VTLists+12 }, // DSPR { 32, 32, 32, VTLists+6 }, // FGR32 { 32, 32, 32, VTLists+0 }, // FGRCC { 32, 32, 32, VTLists+0 }, // GPR32 { 32, 32, 32, VTLists+0 }, // HWRegs { 32, 32, 32, VTLists+0 }, // MSACtrl { 32, 32, 32, VTLists+0 }, // GPR32NONZERO { 32, 32, 32, VTLists+0 }, // CPU16RegsPlusSP { 32, 32, 32, VTLists+0 }, // CPU16Regs { 32, 32, 32, VTLists+0 }, // FCC { 32, 32, 32, VTLists+0 }, // GPRMM16 { 32, 32, 32, VTLists+0 }, // GPRMM16MoveP { 32, 32, 32, VTLists+0 }, // GPRMM16Zero { 32, 32, 32, VTLists+0 }, // CPU16Regs_and_GPRMM16Zero { 32, 32, 32, VTLists+0 }, // GPR32NONZERO_and_GPRMM16MoveP { 32, 32, 32, VTLists+0 }, // GPRMM16MovePPairSecond { 32, 32, 32, VTLists+0 }, // CPU16Regs_and_GPRMM16MoveP { 32, 32, 32, VTLists+0 }, // GPRMM16MoveP_and_GPRMM16Zero { 32, 32, 32, VTLists+0 }, // HI32DSP { 32, 32, 32, VTLists+0 }, // LO32DSP { 32, 32, 32, VTLists+0 }, // CPU16Regs_and_GPRMM16MovePPairSecond { 32, 32, 32, VTLists+0 }, // GPRMM16MovePPairFirst { 32, 32, 32, VTLists+0 }, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero { 32, 32, 32, VTLists+0 }, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond { 32, 32, 32, VTLists+0 }, // CPURAReg { 32, 32, 32, VTLists+0 }, // CPUSPReg { 32, 32, 32, VTLists+12 }, // DSPCC { 32, 32, 32, VTLists+0 }, // GP32 { 32, 32, 32, VTLists+0 }, // GPR32ZERO { 32, 32, 32, VTLists+0 }, // HI32 { 32, 32, 32, VTLists+0 }, // LO32 { 32, 32, 32, VTLists+0 }, // SP32 { 64, 64, 64, VTLists+8 }, // FGR64 { 64, 64, 64, VTLists+2 }, // GPR64 { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPR32NONZERO { 64, 64, 64, VTLists+8 }, // AFGR64 { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16RegsPlusSP { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16Regs { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MoveP { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16Zero { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond { 64, 64, 64, VTLists+24 }, // ACC64DSP { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero { 64, 64, 64, VTLists+2 }, // OCTEON_MPL { 64, 64, 64, VTLists+2 }, // OCTEON_P { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond { 64, 64, 64, VTLists+24 }, // ACC64 { 64, 64, 64, VTLists+2 }, // GP64 { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_CPURAReg { 64, 64, 64, VTLists+2 }, // GPR64_with_sub_32_in_GPR32ZERO { 64, 64, 64, VTLists+2 }, // HI64 { 64, 64, 64, VTLists+2 }, // LO64 { 64, 64, 64, VTLists+2 }, // SP64 { 128, 128, 128, VTLists+10 }, // MSA128B { 128, 128, 128, VTLists+21 }, // MSA128D { 128, 128, 128, VTLists+15 }, // MSA128H { 128, 128, 128, VTLists+18 }, // MSA128W { 128, 128, 128, VTLists+18 }, // MSA128WEvens { 128, 128, 128, VTLists+24 }, // ACC128 }; static const TargetRegisterClass *const NullRegClasses[] = { nullptr }; static const uint32_t MSA128F16SubClassMask[] = { 0x00000001, 0x00000000, 0x0000001f, }; static const uint32_t CCRSubClassMask[] = { 0x00000002, 0x00000000, 0x00000000, }; static const uint32_t COP0SubClassMask[] = { 0x00000004, 0x00000000, 0x00000000, }; static const uint32_t COP2SubClassMask[] = { 0x00000008, 0x00000000, 0x00000000, }; static const uint32_t COP3SubClassMask[] = { 0x00000010, 0x00000000, 0x00000000, }; static const uint32_t DSPRSubClassMask[] = { 0x7e7fb920, 0x00000013, 0x00000000, 0x00000000, 0x9d3efec0, 0x00000000, // sub_32 }; static const uint32_t FGR32SubClassMask[] = { 0x000000c0, 0x00000000, 0x00000000, 0x00000000, 0x00000100, 0x00000000, // sub_hi 0x00000001, 0x00000120, 0x0000001f, // sub_lo }; static const uint32_t FGRCCSubClassMask[] = { 0x000000c0, 0x00000000, 0x00000000, 0x00000000, 0x00000100, 0x00000000, // sub_hi 0x00000001, 0x00000120, 0x0000001f, // sub_lo }; static const uint32_t GPR32SubClassMask[] = { 0x7e7fb900, 0x00000013, 0x00000000, 0x00000000, 0x9d3efec0, 0x00000000, // sub_32 }; static const uint32_t HWRegsSubClassMask[] = { 0x00000200, 0x00000000, 0x00000000, }; static const uint32_t MSACtrlSubClassMask[] = { 0x00000400, 0x00000000, 0x00000000, }; static const uint32_t GPR32NONZEROSubClassMask[] = { 0x7e3cb800, 0x00000011, 0x00000000, 0x00000000, 0x8d3ae680, 0x00000000, // sub_32 }; static const uint32_t CPU16RegsPlusSPSubClassMask[] = { 0x5e24b000, 0x00000010, 0x00000000, 0x00000000, 0x813a2600, 0x00000000, // sub_32 }; static const uint32_t CPU16RegsSubClassMask[] = { 0x1e24a000, 0x00000000, 0x00000000, 0x00000000, 0x013a2400, 0x00000000, // sub_32 }; static const uint32_t FCCSubClassMask[] = { 0x00004000, 0x00000000, 0x00000000, }; static const uint32_t GPRMM16SubClassMask[] = { 0x1e248000, 0x00000000, 0x00000000, 0x00000000, 0x013a2400, 0x00000000, // sub_32 }; static const uint32_t GPRMM16MovePSubClassMask[] = { 0x08690000, 0x00000002, 0x00000000, 0x00000000, 0x10264800, 0x00000000, // sub_32 }; static const uint32_t GPRMM16ZeroSubClassMask[] = { 0x1e460000, 0x00000002, 0x00000000, 0x00000000, 0x113c3000, 0x00000000, // sub_32 }; static const uint32_t CPU16Regs_and_GPRMM16ZeroSubClassMask[] = { 0x1e040000, 0x00000000, 0x00000000, 0x00000000, 0x01382000, 0x00000000, // sub_32 }; static const uint32_t GPR32NONZERO_and_GPRMM16MovePSubClassMask[] = { 0x08280000, 0x00000000, 0x00000000, 0x00000000, 0x00224000, 0x00000000, // sub_32 }; static const uint32_t GPRMM16MovePPairSecondSubClassMask[] = { 0x12100000, 0x00000000, 0x00000000, 0x00000000, 0x01088000, 0x00000000, // sub_32 }; static const uint32_t CPU16Regs_and_GPRMM16MovePSubClassMask[] = { 0x08200000, 0x00000000, 0x00000000, 0x00000000, 0x00220000, 0x00000000, // sub_32 }; static const uint32_t GPRMM16MoveP_and_GPRMM16ZeroSubClassMask[] = { 0x08400000, 0x00000002, 0x00000000, 0x00000000, 0x10240000, 0x00000000, // sub_32 }; static const uint32_t HI32DSPSubClassMask[] = { 0x00800000, 0x00000004, 0x00000000, 0x00000000, 0x20000000, 0x00000000, // sub_32 0x00000000, 0x02010000, 0x00000000, // sub_hi 0x00000000, 0x00000000, 0x00000020, // sub_hi_then_sub_32 }; static const uint32_t LO32DSPSubClassMask[] = { 0x01000000, 0x00000008, 0x00000000, 0x00000000, 0x40000000, 0x00000020, // sub_32 0x00000000, 0x02010000, 0x00000000, // sub_lo }; static const uint32_t CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask[] = { 0x12000000, 0x00000000, 0x00000000, 0x00000000, 0x01080000, 0x00000000, // sub_32 }; static const uint32_t GPRMM16MovePPairFirstSubClassMask[] = { 0x14000000, 0x00000000, 0x00000000, 0x00000000, 0x01100000, 0x00000000, // sub_32 }; static const uint32_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = { 0x08000000, 0x00000000, 0x00000000, 0x00000000, 0x00200000, 0x00000000, // sub_32 }; static const uint32_t GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask[] = { 0x10000000, 0x00000000, 0x00000000, 0x00000000, 0x01000000, 0x00000000, // sub_32 }; static const uint32_t CPURARegSubClassMask[] = { 0x20000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x00000000, // sub_32 }; static const uint32_t CPUSPRegSubClassMask[] = { 0x40000000, 0x00000010, 0x00000000, 0x00000000, 0x80000000, 0x00000000, // sub_32 }; static const uint32_t DSPCCSubClassMask[] = { 0x80000000, 0x00000000, 0x00000000, }; static const uint32_t GP32SubClassMask[] = { 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x04000000, 0x00000000, // sub_32 }; static const uint32_t GPR32ZEROSubClassMask[] = { 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x10000000, 0x00000000, // sub_32 }; static const uint32_t HI32SubClassMask[] = { 0x00000000, 0x00000004, 0x00000000, 0x00000000, 0x20000000, 0x00000000, // sub_32 0x00000000, 0x02000000, 0x00000000, // sub_hi 0x00000000, 0x00000000, 0x00000020, // sub_hi_then_sub_32 }; static const uint32_t LO32SubClassMask[] = { 0x00000000, 0x00000008, 0x00000000, 0x00000000, 0x40000000, 0x00000020, // sub_32 0x00000000, 0x02000000, 0x00000000, // sub_lo }; static const uint32_t SP32SubClassMask[] = { 0x00000000, 0x00000010, 0x00000000, 0x00000000, 0x80000000, 0x00000000, // sub_32 }; static const uint32_t FGR64SubClassMask[] = { 0x00000000, 0x00000020, 0x00000000, 0x00000001, 0x00000000, 0x0000001f, // sub_64 }; static const uint32_t GPR64SubClassMask[] = { 0x00000000, 0x9d3efec0, 0x00000000, }; static const uint32_t GPR64_with_sub_32_in_GPR32NONZEROSubClassMask[] = { 0x00000000, 0x8d3ae680, 0x00000000, }; static const uint32_t AFGR64SubClassMask[] = { 0x00000000, 0x00000100, 0x00000000, }; static const uint32_t GPR64_with_sub_32_in_CPU16RegsPlusSPSubClassMask[] = { 0x00000000, 0x813a2600, 0x00000000, }; static const uint32_t GPR64_with_sub_32_in_CPU16RegsSubClassMask[] = { 0x00000000, 0x013a2400, 0x00000000, }; static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePSubClassMask[] = { 0x00000000, 0x10264800, 0x00000000, }; static const uint32_t GPR64_with_sub_32_in_GPRMM16ZeroSubClassMask[] = { 0x00000000, 0x113c3000, 0x00000000, }; static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = { 0x00000000, 0x01382000, 0x00000000, }; static const uint32_t GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSubClassMask[] = { 0x00000000, 0x00224000, 0x00000000, }; static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairSecondSubClassMask[] = { 0x00000000, 0x01088000, 0x00000000, }; static const uint32_t ACC64DSPSubClassMask[] = { 0x00000000, 0x02010000, 0x00000000, 0x00000000, 0x00000000, 0x00000020, // sub_32_sub_hi_then_sub_32 }; static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSubClassMask[] = { 0x00000000, 0x00220000, 0x00000000, }; static const uint32_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSubClassMask[] = { 0x00000000, 0x10240000, 0x00000000, }; static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask[] = { 0x00000000, 0x01080000, 0x00000000, }; static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairFirstSubClassMask[] = { 0x00000000, 0x01100000, 0x00000000, }; static const uint32_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = { 0x00000000, 0x00200000, 0x00000000, }; static const uint32_t OCTEON_MPLSubClassMask[] = { 0x00000000, 0x00400000, 0x00000000, }; static const uint32_t OCTEON_PSubClassMask[] = { 0x00000000, 0x00800000, 0x00000000, }; static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask[] = { 0x00000000, 0x01000000, 0x00000000, }; static const uint32_t ACC64SubClassMask[] = { 0x00000000, 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000020, // sub_32_sub_hi_then_sub_32 }; static const uint32_t GP64SubClassMask[] = { 0x00000000, 0x04000000, 0x00000000, }; static const uint32_t GPR64_with_sub_32_in_CPURARegSubClassMask[] = { 0x00000000, 0x08000000, 0x00000000, }; static const uint32_t GPR64_with_sub_32_in_GPR32ZEROSubClassMask[] = { 0x00000000, 0x10000000, 0x00000000, }; static const uint32_t HI64SubClassMask[] = { 0x00000000, 0x20000000, 0x00000000, 0x00000000, 0x00000000, 0x00000020, // sub_hi }; static const uint32_t LO64SubClassMask[] = { 0x00000000, 0x40000000, 0x00000000, 0x00000000, 0x00000000, 0x00000020, // sub_lo }; static const uint32_t SP64SubClassMask[] = { 0x00000000, 0x80000000, 0x00000000, }; static const uint32_t MSA128BSubClassMask[] = { 0x00000000, 0x00000000, 0x0000001f, }; static const uint32_t MSA128DSubClassMask[] = { 0x00000000, 0x00000000, 0x0000001f, }; static const uint32_t MSA128HSubClassMask[] = { 0x00000000, 0x00000000, 0x0000001f, }; static const uint32_t MSA128WSubClassMask[] = { 0x00000000, 0x00000000, 0x0000001f, }; static const uint32_t MSA128WEvensSubClassMask[] = { 0x00000000, 0x00000000, 0x00000010, }; static const uint32_t ACC128SubClassMask[] = { 0x00000000, 0x00000000, 0x00000020, }; static const uint16_t SuperRegIdxSeqs[] = { /* 0 */ 1, 0, /* 2 */ 2, 0, /* 4 */ 8, 0, /* 6 */ 1, 9, 0, /* 9 */ 8, 9, 0, /* 12 */ 1, 8, 10, 0, /* 16 */ 11, 0, }; static const TargetRegisterClass *const FGR32Superclasses[] = { &Mips::FGRCCRegClass, nullptr }; static const TargetRegisterClass *const FGRCCSuperclasses[] = { &Mips::FGR32RegClass, nullptr }; static const TargetRegisterClass *const GPR32Superclasses[] = { &Mips::DSPRRegClass, nullptr }; static const TargetRegisterClass *const GPR32NONZEROSuperclasses[] = { &Mips::DSPRRegClass, &Mips::GPR32RegClass, nullptr }; static const TargetRegisterClass *const CPU16RegsPlusSPSuperclasses[] = { &Mips::DSPRRegClass, &Mips::GPR32RegClass, &Mips::GPR32NONZERORegClass, nullptr }; static const TargetRegisterClass *const CPU16RegsSuperclasses[] = { &Mips::DSPRRegClass, &Mips::GPR32RegClass, &Mips::GPR32NONZERORegClass, &Mips::CPU16RegsPlusSPRegClass, nullptr }; static const TargetRegisterClass *const GPRMM16Superclasses[] = { &Mips::DSPRRegClass, &Mips::GPR32RegClass, &Mips::GPR32NONZERORegClass, &Mips::CPU16RegsPlusSPRegClass, &Mips::CPU16RegsRegClass, nullptr }; static const TargetRegisterClass *const GPRMM16MovePSuperclasses[] = { &Mips::DSPRRegClass, &Mips::GPR32RegClass, nullptr }; static const TargetRegisterClass *const GPRMM16ZeroSuperclasses[] = { &Mips::DSPRRegClass, &Mips::GPR32RegClass, nullptr }; static const TargetRegisterClass *const CPU16Regs_and_GPRMM16ZeroSuperclasses[] = { &Mips::DSPRRegClass, &Mips::GPR32RegClass, &Mips::GPR32NONZERORegClass, &Mips::CPU16RegsPlusSPRegClass, &Mips::CPU16RegsRegClass, &Mips::GPRMM16RegClass, &Mips::GPRMM16ZeroRegClass, nullptr }; static const TargetRegisterClass *const GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = { &Mips::DSPRRegClass, &Mips::GPR32RegClass, &Mips::GPR32NONZERORegClass, &Mips::GPRMM16MovePRegClass, nullptr }; static const TargetRegisterClass *const GPRMM16MovePPairSecondSuperclasses[] = { &Mips::DSPRRegClass, &Mips::GPR32RegClass, &Mips::GPR32NONZERORegClass, nullptr }; static const TargetRegisterClass *const CPU16Regs_and_GPRMM16MovePSuperclasses[] = { &Mips::DSPRRegClass, &Mips::GPR32RegClass, &Mips::GPR32NONZERORegClass, &Mips::CPU16RegsPlusSPRegClass, &Mips::CPU16RegsRegClass, &Mips::GPRMM16RegClass, &Mips::GPRMM16MovePRegClass, &Mips::GPR32NONZERO_and_GPRMM16MovePRegClass, nullptr }; static const TargetRegisterClass *const GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = { &Mips::DSPRRegClass, &Mips::GPR32RegClass, &Mips::GPRMM16MovePRegClass, &Mips::GPRMM16ZeroRegClass, nullptr }; static const TargetRegisterClass *const CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses[] = { &Mips::DSPRRegClass, &Mips::GPR32RegClass, &Mips::GPR32NONZERORegClass, &Mips::CPU16RegsPlusSPRegClass, &Mips::CPU16RegsRegClass, &Mips::GPRMM16RegClass, &Mips::GPRMM16ZeroRegClass, &Mips::CPU16Regs_and_GPRMM16ZeroRegClass, &Mips::GPRMM16MovePPairSecondRegClass, nullptr }; static const TargetRegisterClass *const GPRMM16MovePPairFirstSuperclasses[] = { &Mips::DSPRRegClass, &Mips::GPR32RegClass, &Mips::GPR32NONZERORegClass, &Mips::CPU16RegsPlusSPRegClass, &Mips::CPU16RegsRegClass, &Mips::GPRMM16RegClass, &Mips::GPRMM16ZeroRegClass, &Mips::CPU16Regs_and_GPRMM16ZeroRegClass, nullptr }; static const TargetRegisterClass *const GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = { &Mips::DSPRRegClass, &Mips::GPR32RegClass, &Mips::GPR32NONZERORegClass, &Mips::CPU16RegsPlusSPRegClass, &Mips::CPU16RegsRegClass, &Mips::GPRMM16RegClass, &Mips::GPRMM16MovePRegClass, &Mips::GPRMM16ZeroRegClass, &Mips::CPU16Regs_and_GPRMM16ZeroRegClass, &Mips::GPR32NONZERO_and_GPRMM16MovePRegClass, &Mips::CPU16Regs_and_GPRMM16MovePRegClass, &Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass, nullptr }; static const TargetRegisterClass *const GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses[] = { &Mips::DSPRRegClass, &Mips::GPR32RegClass, &Mips::GPR32NONZERORegClass, &Mips::CPU16RegsPlusSPRegClass, &Mips::CPU16RegsRegClass, &Mips::GPRMM16RegClass, &Mips::GPRMM16ZeroRegClass, &Mips::CPU16Regs_and_GPRMM16ZeroRegClass, &Mips::GPRMM16MovePPairSecondRegClass, &Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClass, &Mips::GPRMM16MovePPairFirstRegClass, nullptr }; static const TargetRegisterClass *const CPURARegSuperclasses[] = { &Mips::DSPRRegClass, &Mips::GPR32RegClass, &Mips::GPR32NONZERORegClass, nullptr }; static const TargetRegisterClass *const CPUSPRegSuperclasses[] = { &Mips::DSPRRegClass, &Mips::GPR32RegClass, &Mips::GPR32NONZERORegClass, &Mips::CPU16RegsPlusSPRegClass, nullptr }; static const TargetRegisterClass *const GP32Superclasses[] = { &Mips::DSPRRegClass, &Mips::GPR32RegClass, &Mips::GPR32NONZERORegClass, nullptr }; static const TargetRegisterClass *const GPR32ZEROSuperclasses[] = { &Mips::DSPRRegClass, &Mips::GPR32RegClass, &Mips::GPRMM16MovePRegClass, &Mips::GPRMM16ZeroRegClass, &Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass, nullptr }; static const TargetRegisterClass *const HI32Superclasses[] = { &Mips::HI32DSPRegClass, nullptr }; static const TargetRegisterClass *const LO32Superclasses[] = { &Mips::LO32DSPRegClass, nullptr }; static const TargetRegisterClass *const SP32Superclasses[] = { &Mips::DSPRRegClass, &Mips::GPR32RegClass, &Mips::GPR32NONZERORegClass, &Mips::CPU16RegsPlusSPRegClass, &Mips::CPUSPRegRegClass, nullptr }; static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32NONZEROSuperclasses[] = { &Mips::GPR64RegClass, nullptr }; static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses[] = { &Mips::GPR64RegClass, &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass, nullptr }; static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16RegsSuperclasses[] = { &Mips::GPR64RegClass, &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass, &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass, nullptr }; static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePSuperclasses[] = { &Mips::GPR64RegClass, nullptr }; static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16ZeroSuperclasses[] = { &Mips::GPR64RegClass, nullptr }; static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = { &Mips::GPR64RegClass, &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass, &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass, &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass, &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass, nullptr }; static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = { &Mips::GPR64RegClass, &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass, &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass, nullptr }; static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePPairSecondSuperclasses[] = { &Mips::GPR64RegClass, &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass, nullptr }; static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSuperclasses[] = { &Mips::GPR64RegClass, &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass, &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass, &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass, &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass, &Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass, nullptr }; static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = { &Mips::GPR64RegClass, &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass, &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass, nullptr }; static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses[] = { &Mips::GPR64RegClass, &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass, &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass, &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass, &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass, &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass, &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass, nullptr }; static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePPairFirstSuperclasses[] = { &Mips::GPR64RegClass, &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass, &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass, &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass, &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass, &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass, nullptr }; static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = { &Mips::GPR64RegClass, &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass, &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass, &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass, &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass, &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass, &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass, &Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass, &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass, &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass, nullptr }; static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses[] = { &Mips::GPR64RegClass, &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass, &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass, &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass, &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass, &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass, &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass, &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass, &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass, nullptr }; static const TargetRegisterClass *const ACC64Superclasses[] = { &Mips::ACC64DSPRegClass, nullptr }; static const TargetRegisterClass *const GP64Superclasses[] = { &Mips::GPR64RegClass, &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass, nullptr }; static const TargetRegisterClass *const GPR64_with_sub_32_in_CPURARegSuperclasses[] = { &Mips::GPR64RegClass, &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass, nullptr }; static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32ZEROSuperclasses[] = { &Mips::GPR64RegClass, &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass, &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass, &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass, nullptr }; static const TargetRegisterClass *const SP64Superclasses[] = { &Mips::GPR64RegClass, &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass, &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass, nullptr }; static const TargetRegisterClass *const MSA128BSuperclasses[] = { &Mips::MSA128F16RegClass, &Mips::MSA128DRegClass, &Mips::MSA128HRegClass, &Mips::MSA128WRegClass, nullptr }; static const TargetRegisterClass *const MSA128DSuperclasses[] = { &Mips::MSA128F16RegClass, &Mips::MSA128BRegClass, &Mips::MSA128HRegClass, &Mips::MSA128WRegClass, nullptr }; static const TargetRegisterClass *const MSA128HSuperclasses[] = { &Mips::MSA128F16RegClass, &Mips::MSA128BRegClass, &Mips::MSA128DRegClass, &Mips::MSA128WRegClass, nullptr }; static const TargetRegisterClass *const MSA128WSuperclasses[] = { &Mips::MSA128F16RegClass, &Mips::MSA128BRegClass, &Mips::MSA128DRegClass, &Mips::MSA128HRegClass, nullptr }; static const TargetRegisterClass *const MSA128WEvensSuperclasses[] = { &Mips::MSA128F16RegClass, &Mips::MSA128BRegClass, &Mips::MSA128DRegClass, &Mips::MSA128HRegClass, &Mips::MSA128WRegClass, nullptr }; static inline unsigned FGR32AltOrderSelect(const MachineFunction &MF) { const auto & S = MF.getSubtarget(); return S.isABI_O32() && !S.useOddSPReg(); } static ArrayRef FGR32GetRawAllocationOrder(const MachineFunction &MF) { static const MCPhysReg AltOrder1[] = { Mips::F0, Mips::F2, Mips::F4, Mips::F6, Mips::F8, Mips::F10, Mips::F12, Mips::F14, Mips::F16, Mips::F18, Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30 }; const MCRegisterClass &MCR = MipsMCRegisterClasses[Mips::FGR32RegClassID]; const ArrayRef Order[] = { makeArrayRef(MCR.begin(), MCR.getNumRegs()), makeArrayRef(AltOrder1) }; const unsigned Select = FGR32AltOrderSelect(MF); assert(Select < 2); return Order[Select]; } static inline unsigned FGR64AltOrderSelect(const MachineFunction &MF) { const auto & S = MF.getSubtarget(); return S.isABI_O32() && !S.useOddSPReg(); } static ArrayRef FGR64GetRawAllocationOrder(const MachineFunction &MF) { static const MCPhysReg AltOrder1[] = { Mips::D0_64, Mips::D2_64, Mips::D4_64, Mips::D6_64, Mips::D8_64, Mips::D10_64, Mips::D12_64, Mips::D14_64, Mips::D16_64, Mips::D18_64, Mips::D20_64, Mips::D22_64, Mips::D24_64, Mips::D26_64, Mips::D28_64, Mips::D30_64 }; const MCRegisterClass &MCR = MipsMCRegisterClasses[Mips::FGR64RegClassID]; const ArrayRef Order[] = { makeArrayRef(MCR.begin(), MCR.getNumRegs()), makeArrayRef(AltOrder1) }; const unsigned Select = FGR64AltOrderSelect(MF); assert(Select < 2); return Order[Select]; } namespace Mips { // Register class instances extern const TargetRegisterClass MSA128F16RegClass = { &MipsMCRegisterClasses[MSA128F16RegClassID], MSA128F16SubClassMask, SuperRegIdxSeqs + 1, LaneBitmask(0x00000041), 0, true, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ NullRegClasses, nullptr }; extern const TargetRegisterClass CCRRegClass = { &MipsMCRegisterClasses[CCRRegClassID], CCRSubClassMask, SuperRegIdxSeqs + 1, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ NullRegClasses, nullptr }; extern const TargetRegisterClass COP0RegClass = { &MipsMCRegisterClasses[COP0RegClassID], COP0SubClassMask, SuperRegIdxSeqs + 1, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ NullRegClasses, nullptr }; extern const TargetRegisterClass COP2RegClass = { &MipsMCRegisterClasses[COP2RegClassID], COP2SubClassMask, SuperRegIdxSeqs + 1, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ NullRegClasses, nullptr }; extern const TargetRegisterClass COP3RegClass = { &MipsMCRegisterClasses[COP3RegClassID], COP3SubClassMask, SuperRegIdxSeqs + 1, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ NullRegClasses, nullptr }; extern const TargetRegisterClass DSPRRegClass = { &MipsMCRegisterClasses[DSPRRegClassID], DSPRSubClassMask, SuperRegIdxSeqs + 0, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ NullRegClasses, nullptr }; extern const TargetRegisterClass FGR32RegClass = { &MipsMCRegisterClasses[FGR32RegClassID], FGR32SubClassMask, SuperRegIdxSeqs + 9, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ FGR32Superclasses, FGR32GetRawAllocationOrder }; extern const TargetRegisterClass FGRCCRegClass = { &MipsMCRegisterClasses[FGRCCRegClassID], FGRCCSubClassMask, SuperRegIdxSeqs + 9, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ FGRCCSuperclasses, nullptr }; extern const TargetRegisterClass GPR32RegClass = { &MipsMCRegisterClasses[GPR32RegClassID], GPR32SubClassMask, SuperRegIdxSeqs + 0, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ GPR32Superclasses, nullptr }; extern const TargetRegisterClass HWRegsRegClass = { &MipsMCRegisterClasses[HWRegsRegClassID], HWRegsSubClassMask, SuperRegIdxSeqs + 1, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ NullRegClasses, nullptr }; extern const TargetRegisterClass MSACtrlRegClass = { &MipsMCRegisterClasses[MSACtrlRegClassID], MSACtrlSubClassMask, SuperRegIdxSeqs + 1, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ NullRegClasses, nullptr }; extern const TargetRegisterClass GPR32NONZERORegClass = { &MipsMCRegisterClasses[GPR32NONZERORegClassID], GPR32NONZEROSubClassMask, SuperRegIdxSeqs + 0, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ GPR32NONZEROSuperclasses, nullptr }; extern const TargetRegisterClass CPU16RegsPlusSPRegClass = { &MipsMCRegisterClasses[CPU16RegsPlusSPRegClassID], CPU16RegsPlusSPSubClassMask, SuperRegIdxSeqs + 0, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ CPU16RegsPlusSPSuperclasses, nullptr }; extern const TargetRegisterClass CPU16RegsRegClass = { &MipsMCRegisterClasses[CPU16RegsRegClassID], CPU16RegsSubClassMask, SuperRegIdxSeqs + 0, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ CPU16RegsSuperclasses, nullptr }; extern const TargetRegisterClass FCCRegClass = { &MipsMCRegisterClasses[FCCRegClassID], FCCSubClassMask, SuperRegIdxSeqs + 1, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ NullRegClasses, nullptr }; extern const TargetRegisterClass GPRMM16RegClass = { &MipsMCRegisterClasses[GPRMM16RegClassID], GPRMM16SubClassMask, SuperRegIdxSeqs + 0, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ GPRMM16Superclasses, nullptr }; extern const TargetRegisterClass GPRMM16MovePRegClass = { &MipsMCRegisterClasses[GPRMM16MovePRegClassID], GPRMM16MovePSubClassMask, SuperRegIdxSeqs + 0, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ GPRMM16MovePSuperclasses, nullptr }; extern const TargetRegisterClass GPRMM16ZeroRegClass = { &MipsMCRegisterClasses[GPRMM16ZeroRegClassID], GPRMM16ZeroSubClassMask, SuperRegIdxSeqs + 0, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ GPRMM16ZeroSuperclasses, nullptr }; extern const TargetRegisterClass CPU16Regs_and_GPRMM16ZeroRegClass = { &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16ZeroRegClassID], CPU16Regs_and_GPRMM16ZeroSubClassMask, SuperRegIdxSeqs + 0, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ CPU16Regs_and_GPRMM16ZeroSuperclasses, nullptr }; extern const TargetRegisterClass GPR32NONZERO_and_GPRMM16MovePRegClass = { &MipsMCRegisterClasses[GPR32NONZERO_and_GPRMM16MovePRegClassID], GPR32NONZERO_and_GPRMM16MovePSubClassMask, SuperRegIdxSeqs + 0, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ GPR32NONZERO_and_GPRMM16MovePSuperclasses, nullptr }; extern const TargetRegisterClass GPRMM16MovePPairSecondRegClass = { &MipsMCRegisterClasses[GPRMM16MovePPairSecondRegClassID], GPRMM16MovePPairSecondSubClassMask, SuperRegIdxSeqs + 0, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ GPRMM16MovePPairSecondSuperclasses, nullptr }; extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePRegClass = { &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16MovePRegClassID], CPU16Regs_and_GPRMM16MovePSubClassMask, SuperRegIdxSeqs + 0, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ CPU16Regs_and_GPRMM16MovePSuperclasses, nullptr }; extern const TargetRegisterClass GPRMM16MoveP_and_GPRMM16ZeroRegClass = { &MipsMCRegisterClasses[GPRMM16MoveP_and_GPRMM16ZeroRegClassID], GPRMM16MoveP_and_GPRMM16ZeroSubClassMask, SuperRegIdxSeqs + 0, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ GPRMM16MoveP_and_GPRMM16ZeroSuperclasses, nullptr }; extern const TargetRegisterClass HI32DSPRegClass = { &MipsMCRegisterClasses[HI32DSPRegClassID], HI32DSPSubClassMask, SuperRegIdxSeqs + 12, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ NullRegClasses, nullptr }; extern const TargetRegisterClass LO32DSPRegClass = { &MipsMCRegisterClasses[LO32DSPRegClassID], LO32DSPSubClassMask, SuperRegIdxSeqs + 6, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ NullRegClasses, nullptr }; extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePPairSecondRegClass = { &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16MovePPairSecondRegClassID], CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask, SuperRegIdxSeqs + 0, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses, nullptr }; extern const TargetRegisterClass GPRMM16MovePPairFirstRegClass = { &MipsMCRegisterClasses[GPRMM16MovePPairFirstRegClassID], GPRMM16MovePPairFirstSubClassMask, SuperRegIdxSeqs + 0, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ GPRMM16MovePPairFirstSuperclasses, nullptr }; extern const TargetRegisterClass GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = { &MipsMCRegisterClasses[GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID], GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask, SuperRegIdxSeqs + 0, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses, nullptr }; extern const TargetRegisterClass GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass = { &MipsMCRegisterClasses[GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID], GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask, SuperRegIdxSeqs + 0, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses, nullptr }; extern const TargetRegisterClass CPURARegRegClass = { &MipsMCRegisterClasses[CPURARegRegClassID], CPURARegSubClassMask, SuperRegIdxSeqs + 0, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ CPURARegSuperclasses, nullptr }; extern const TargetRegisterClass CPUSPRegRegClass = { &MipsMCRegisterClasses[CPUSPRegRegClassID], CPUSPRegSubClassMask, SuperRegIdxSeqs + 0, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ CPUSPRegSuperclasses, nullptr }; extern const TargetRegisterClass DSPCCRegClass = { &MipsMCRegisterClasses[DSPCCRegClassID], DSPCCSubClassMask, SuperRegIdxSeqs + 1, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ NullRegClasses, nullptr }; extern const TargetRegisterClass GP32RegClass = { &MipsMCRegisterClasses[GP32RegClassID], GP32SubClassMask, SuperRegIdxSeqs + 0, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ GP32Superclasses, nullptr }; extern const TargetRegisterClass GPR32ZERORegClass = { &MipsMCRegisterClasses[GPR32ZERORegClassID], GPR32ZEROSubClassMask, SuperRegIdxSeqs + 0, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ GPR32ZEROSuperclasses, nullptr }; extern const TargetRegisterClass HI32RegClass = { &MipsMCRegisterClasses[HI32RegClassID], HI32SubClassMask, SuperRegIdxSeqs + 12, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ HI32Superclasses, nullptr }; extern const TargetRegisterClass LO32RegClass = { &MipsMCRegisterClasses[LO32RegClassID], LO32SubClassMask, SuperRegIdxSeqs + 6, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ LO32Superclasses, nullptr }; extern const TargetRegisterClass SP32RegClass = { &MipsMCRegisterClasses[SP32RegClassID], SP32SubClassMask, SuperRegIdxSeqs + 0, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ SP32Superclasses, nullptr }; extern const TargetRegisterClass FGR64RegClass = { &MipsMCRegisterClasses[FGR64RegClassID], FGR64SubClassMask, SuperRegIdxSeqs + 2, LaneBitmask(0x00000041), 0, true, /* HasDisjunctSubRegs */ true, /* CoveredBySubRegs */ NullRegClasses, FGR64GetRawAllocationOrder }; extern const TargetRegisterClass GPR64RegClass = { &MipsMCRegisterClasses[GPR64RegClassID], GPR64SubClassMask, SuperRegIdxSeqs + 1, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ NullRegClasses, nullptr }; extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERORegClass = { &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32NONZERORegClassID], GPR64_with_sub_32_in_GPR32NONZEROSubClassMask, SuperRegIdxSeqs + 1, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ GPR64_with_sub_32_in_GPR32NONZEROSuperclasses, nullptr }; extern const TargetRegisterClass AFGR64RegClass = { &MipsMCRegisterClasses[AFGR64RegClassID], AFGR64SubClassMask, SuperRegIdxSeqs + 1, LaneBitmask(0x00000041), 0, true, /* HasDisjunctSubRegs */ true, /* CoveredBySubRegs */ NullRegClasses, nullptr }; extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass = { &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID], GPR64_with_sub_32_in_CPU16RegsPlusSPSubClassMask, SuperRegIdxSeqs + 1, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses, nullptr }; extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsRegClass = { &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16RegsRegClassID], GPR64_with_sub_32_in_CPU16RegsSubClassMask, SuperRegIdxSeqs + 1, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ GPR64_with_sub_32_in_CPU16RegsSuperclasses, nullptr }; extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePRegClass = { &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePRegClassID], GPR64_with_sub_32_in_GPRMM16MovePSubClassMask, SuperRegIdxSeqs + 1, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ GPR64_with_sub_32_in_GPRMM16MovePSuperclasses, nullptr }; extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16ZeroRegClass = { &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16ZeroRegClassID], GPR64_with_sub_32_in_GPRMM16ZeroSubClassMask, SuperRegIdxSeqs + 1, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ GPR64_with_sub_32_in_GPRMM16ZeroSuperclasses, nullptr }; extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass = { &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID], GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSubClassMask, SuperRegIdxSeqs + 1, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSuperclasses, nullptr }; extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass = { &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID], GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSubClassMask, SuperRegIdxSeqs + 1, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSuperclasses, nullptr }; extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass = { &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID], GPR64_with_sub_32_in_GPRMM16MovePPairSecondSubClassMask, SuperRegIdxSeqs + 1, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ GPR64_with_sub_32_in_GPRMM16MovePPairSecondSuperclasses, nullptr }; extern const TargetRegisterClass ACC64DSPRegClass = { &MipsMCRegisterClasses[ACC64DSPRegClassID], ACC64DSPSubClassMask, SuperRegIdxSeqs + 16, LaneBitmask(0x00000041), 0, true, /* HasDisjunctSubRegs */ true, /* CoveredBySubRegs */ NullRegClasses, nullptr }; extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass = { &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID], GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSubClassMask, SuperRegIdxSeqs + 1, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSuperclasses, nullptr }; extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass = { &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID], GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSubClassMask, SuperRegIdxSeqs + 1, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSuperclasses, nullptr }; extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass = { &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID], GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask, SuperRegIdxSeqs + 1, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses, nullptr }; extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass = { &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID], GPR64_with_sub_32_in_GPRMM16MovePPairFirstSubClassMask, SuperRegIdxSeqs + 1, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ GPR64_with_sub_32_in_GPRMM16MovePPairFirstSuperclasses, nullptr }; extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = { &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID], GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask, SuperRegIdxSeqs + 1, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses, nullptr }; extern const TargetRegisterClass OCTEON_MPLRegClass = { &MipsMCRegisterClasses[OCTEON_MPLRegClassID], OCTEON_MPLSubClassMask, SuperRegIdxSeqs + 1, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ NullRegClasses, nullptr }; extern const TargetRegisterClass OCTEON_PRegClass = { &MipsMCRegisterClasses[OCTEON_PRegClassID], OCTEON_PSubClassMask, SuperRegIdxSeqs + 1, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ NullRegClasses, nullptr }; extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass = { &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID], GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask, SuperRegIdxSeqs + 1, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses, nullptr }; extern const TargetRegisterClass ACC64RegClass = { &MipsMCRegisterClasses[ACC64RegClassID], ACC64SubClassMask, SuperRegIdxSeqs + 16, LaneBitmask(0x00000041), 0, true, /* HasDisjunctSubRegs */ true, /* CoveredBySubRegs */ ACC64Superclasses, nullptr }; extern const TargetRegisterClass GP64RegClass = { &MipsMCRegisterClasses[GP64RegClassID], GP64SubClassMask, SuperRegIdxSeqs + 1, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ GP64Superclasses, nullptr }; extern const TargetRegisterClass GPR64_with_sub_32_in_CPURARegRegClass = { &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPURARegRegClassID], GPR64_with_sub_32_in_CPURARegSubClassMask, SuperRegIdxSeqs + 1, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ GPR64_with_sub_32_in_CPURARegSuperclasses, nullptr }; extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32ZERORegClass = { &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32ZERORegClassID], GPR64_with_sub_32_in_GPR32ZEROSubClassMask, SuperRegIdxSeqs + 1, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ GPR64_with_sub_32_in_GPR32ZEROSuperclasses, nullptr }; extern const TargetRegisterClass HI64RegClass = { &MipsMCRegisterClasses[HI64RegClassID], HI64SubClassMask, SuperRegIdxSeqs + 4, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ NullRegClasses, nullptr }; extern const TargetRegisterClass LO64RegClass = { &MipsMCRegisterClasses[LO64RegClassID], LO64SubClassMask, SuperRegIdxSeqs + 7, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ NullRegClasses, nullptr }; extern const TargetRegisterClass SP64RegClass = { &MipsMCRegisterClasses[SP64RegClassID], SP64SubClassMask, SuperRegIdxSeqs + 1, LaneBitmask(0x00000001), 0, false, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ SP64Superclasses, nullptr }; extern const TargetRegisterClass MSA128BRegClass = { &MipsMCRegisterClasses[MSA128BRegClassID], MSA128BSubClassMask, SuperRegIdxSeqs + 1, LaneBitmask(0x00000041), 0, true, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ MSA128BSuperclasses, nullptr }; extern const TargetRegisterClass MSA128DRegClass = { &MipsMCRegisterClasses[MSA128DRegClassID], MSA128DSubClassMask, SuperRegIdxSeqs + 1, LaneBitmask(0x00000041), 0, true, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ MSA128DSuperclasses, nullptr }; extern const TargetRegisterClass MSA128HRegClass = { &MipsMCRegisterClasses[MSA128HRegClassID], MSA128HSubClassMask, SuperRegIdxSeqs + 1, LaneBitmask(0x00000041), 0, true, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ MSA128HSuperclasses, nullptr }; extern const TargetRegisterClass MSA128WRegClass = { &MipsMCRegisterClasses[MSA128WRegClassID], MSA128WSubClassMask, SuperRegIdxSeqs + 1, LaneBitmask(0x00000041), 0, true, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ MSA128WSuperclasses, nullptr }; extern const TargetRegisterClass MSA128WEvensRegClass = { &MipsMCRegisterClasses[MSA128WEvensRegClassID], MSA128WEvensSubClassMask, SuperRegIdxSeqs + 1, LaneBitmask(0x00000041), 0, true, /* HasDisjunctSubRegs */ false, /* CoveredBySubRegs */ MSA128WEvensSuperclasses, nullptr }; extern const TargetRegisterClass ACC128RegClass = { &MipsMCRegisterClasses[ACC128RegClassID], ACC128SubClassMask, SuperRegIdxSeqs + 1, LaneBitmask(0x00000041), 0, true, /* HasDisjunctSubRegs */ true, /* CoveredBySubRegs */ NullRegClasses, nullptr }; } // end namespace Mips namespace { const TargetRegisterClass* const RegisterClasses[] = { &Mips::MSA128F16RegClass, &Mips::CCRRegClass, &Mips::COP0RegClass, &Mips::COP2RegClass, &Mips::COP3RegClass, &Mips::DSPRRegClass, &Mips::FGR32RegClass, &Mips::FGRCCRegClass, &Mips::GPR32RegClass, &Mips::HWRegsRegClass, &Mips::MSACtrlRegClass, &Mips::GPR32NONZERORegClass, &Mips::CPU16RegsPlusSPRegClass, &Mips::CPU16RegsRegClass, &Mips::FCCRegClass, &Mips::GPRMM16RegClass, &Mips::GPRMM16MovePRegClass, &Mips::GPRMM16ZeroRegClass, &Mips::CPU16Regs_and_GPRMM16ZeroRegClass, &Mips::GPR32NONZERO_and_GPRMM16MovePRegClass, &Mips::GPRMM16MovePPairSecondRegClass, &Mips::CPU16Regs_and_GPRMM16MovePRegClass, &Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass, &Mips::HI32DSPRegClass, &Mips::LO32DSPRegClass, &Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClass, &Mips::GPRMM16MovePPairFirstRegClass, &Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass, &Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass, &Mips::CPURARegRegClass, &Mips::CPUSPRegRegClass, &Mips::DSPCCRegClass, &Mips::GP32RegClass, &Mips::GPR32ZERORegClass, &Mips::HI32RegClass, &Mips::LO32RegClass, &Mips::SP32RegClass, &Mips::FGR64RegClass, &Mips::GPR64RegClass, &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass, &Mips::AFGR64RegClass, &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass, &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass, &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass, &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass, &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass, &Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass, &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass, &Mips::ACC64DSPRegClass, &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass, &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass, &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass, &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass, &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass, &Mips::OCTEON_MPLRegClass, &Mips::OCTEON_PRegClass, &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass, &Mips::ACC64RegClass, &Mips::GP64RegClass, &Mips::GPR64_with_sub_32_in_CPURARegRegClass, &Mips::GPR64_with_sub_32_in_GPR32ZERORegClass, &Mips::HI64RegClass, &Mips::LO64RegClass, &Mips::SP64RegClass, &Mips::MSA128BRegClass, &Mips::MSA128DRegClass, &Mips::MSA128HRegClass, &Mips::MSA128WRegClass, &Mips::MSA128WEvensRegClass, &Mips::ACC128RegClass, }; } // end anonymous namespace static const TargetRegisterInfoDesc MipsRegInfoDesc[] = { // Extra Descriptors { 0, false }, { 0, true }, { 0, true }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, true }, { 0, true }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, true }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, false }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, false }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, { 0, true }, }; unsigned MipsGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const { static const uint8_t RowMap[11] = { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, }; static const uint8_t Rows[2][11] = { { Mips::sub_hi_then_sub_32, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, 0, 0, }, { Mips::sub_32, 0, 0, 0, 0, 0, 0, Mips::sub_hi_then_sub_32, Mips::sub_32, 0, 0, }, }; --IdxA; assert(IdxA < 11); --IdxB; assert(IdxB < 11); return Rows[RowMap[IdxA]][IdxB]; } struct MaskRolOp { LaneBitmask Mask; uint8_t RotateLeft; }; static const MaskRolOp LaneMaskComposeSequences[] = { { LaneBitmask(0xFFFFFFFF), 0 }, { LaneBitmask::getNone(), 0 }, // Sequence 0 { LaneBitmask(0xFFFFFFFF), 1 }, { LaneBitmask::getNone(), 0 }, // Sequence 2 { LaneBitmask(0xFFFFFFFF), 2 }, { LaneBitmask::getNone(), 0 }, // Sequence 4 { LaneBitmask(0xFFFFFFFF), 3 }, { LaneBitmask::getNone(), 0 }, // Sequence 6 { LaneBitmask(0xFFFFFFFF), 4 }, { LaneBitmask::getNone(), 0 }, // Sequence 8 { LaneBitmask(0xFFFFFFFF), 5 }, { LaneBitmask::getNone(), 0 }, // Sequence 10 { LaneBitmask(0xFFFFFFFF), 6 }, { LaneBitmask::getNone(), 0 } // Sequence 12 }; static const MaskRolOp *const CompositeSequences[] = { &LaneMaskComposeSequences[0], // to sub_32 &LaneMaskComposeSequences[0], // to sub_64 &LaneMaskComposeSequences[2], // to sub_dsp16_19 &LaneMaskComposeSequences[4], // to sub_dsp20 &LaneMaskComposeSequences[6], // to sub_dsp21 &LaneMaskComposeSequences[8], // to sub_dsp22 &LaneMaskComposeSequences[10], // to sub_dsp23 &LaneMaskComposeSequences[12], // to sub_hi &LaneMaskComposeSequences[0], // to sub_lo &LaneMaskComposeSequences[12], // to sub_hi_then_sub_32 &LaneMaskComposeSequences[0] // to sub_32_sub_hi_then_sub_32 }; LaneBitmask MipsGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const { --IdxA; assert(IdxA < 11 && "Subregister index out of bounds"); LaneBitmask Result; for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) { LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger(); if (unsigned S = Ops->RotateLeft) Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S))); else Result |= LaneBitmask(M); } return Result; } LaneBitmask MipsGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const { LaneMask &= getSubRegIndexLaneMask(IdxA); --IdxA; assert(IdxA < 11 && "Subregister index out of bounds"); LaneBitmask Result; for (const MaskRolOp *Ops = CompositeSequences[IdxA]; Ops->Mask.any(); ++Ops) { LaneBitmask::Type M = LaneMask.getAsInteger(); if (unsigned S = Ops->RotateLeft) Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S))); else Result |= LaneBitmask(M); } return Result; } const TargetRegisterClass *MipsGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const { static const uint8_t Table[70][11] = { { // MSA128F16 0, // sub_32 1, // sub_64 -> MSA128F16 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 1, // sub_hi -> MSA128F16 1, // sub_lo -> MSA128F16 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // CCR 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // COP0 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // COP2 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // COP3 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // DSPR 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // FGR32 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // FGRCC 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // GPR32 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // HWRegs 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // MSACtrl 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // GPR32NONZERO 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // CPU16RegsPlusSP 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // CPU16Regs 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // FCC 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // GPRMM16 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // GPRMM16MoveP 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // GPRMM16Zero 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // CPU16Regs_and_GPRMM16Zero 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // GPR32NONZERO_and_GPRMM16MoveP 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // GPRMM16MovePPairSecond 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // CPU16Regs_and_GPRMM16MoveP 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // GPRMM16MoveP_and_GPRMM16Zero 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // HI32DSP 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // LO32DSP 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // CPU16Regs_and_GPRMM16MovePPairSecond 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // GPRMM16MovePPairFirst 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // CPURAReg 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // CPUSPReg 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // DSPCC 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // GP32 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // GPR32ZERO 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // HI32 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // LO32 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // SP32 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // FGR64 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 38, // sub_hi -> FGR64 38, // sub_lo -> FGR64 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // GPR64 39, // sub_32 -> GPR64 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // GPR64_with_sub_32_in_GPR32NONZERO 40, // sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // AFGR64 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 41, // sub_hi -> AFGR64 41, // sub_lo -> AFGR64 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // GPR64_with_sub_32_in_CPU16RegsPlusSP 42, // sub_32 -> GPR64_with_sub_32_in_CPU16RegsPlusSP 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // GPR64_with_sub_32_in_CPU16Regs 43, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // GPR64_with_sub_32_in_GPRMM16MoveP 44, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // GPR64_with_sub_32_in_GPRMM16Zero 45, // sub_32 -> GPR64_with_sub_32_in_GPRMM16Zero 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero 46, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP 47, // sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // GPR64_with_sub_32_in_GPRMM16MovePPairSecond 48, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairSecond 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // ACC64DSP 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 49, // sub_hi -> ACC64DSP 49, // sub_lo -> ACC64DSP 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP 50, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero 51, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond 52, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // GPR64_with_sub_32_in_GPRMM16MovePPairFirst 53, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairFirst 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero 54, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // OCTEON_MPL 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // OCTEON_P 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond 57, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // ACC64 0, // sub_32 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 58, // sub_hi -> ACC64 58, // sub_lo -> ACC64 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // GP64 59, // sub_32 -> GP64 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // GPR64_with_sub_32_in_CPURAReg 60, // sub_32 -> GPR64_with_sub_32_in_CPURAReg 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // GPR64_with_sub_32_in_GPR32ZERO 61, // sub_32 -> GPR64_with_sub_32_in_GPR32ZERO 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // HI64 62, // sub_32 -> HI64 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // LO64 63, // sub_32 -> LO64 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // SP64 64, // sub_32 -> SP64 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 0, // sub_hi 0, // sub_lo 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // MSA128B 0, // sub_32 65, // sub_64 -> MSA128B 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 65, // sub_hi -> MSA128B 65, // sub_lo -> MSA128B 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // MSA128D 0, // sub_32 66, // sub_64 -> MSA128D 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 66, // sub_hi -> MSA128D 66, // sub_lo -> MSA128D 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // MSA128H 0, // sub_32 67, // sub_64 -> MSA128H 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 67, // sub_hi -> MSA128H 67, // sub_lo -> MSA128H 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // MSA128W 0, // sub_32 68, // sub_64 -> MSA128W 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 68, // sub_hi -> MSA128W 68, // sub_lo -> MSA128W 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // MSA128WEvens 0, // sub_32 69, // sub_64 -> MSA128WEvens 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 69, // sub_hi -> MSA128WEvens 69, // sub_lo -> MSA128WEvens 0, // sub_hi_then_sub_32 0, // sub_32_sub_hi_then_sub_32 }, { // ACC128 70, // sub_32 -> ACC128 0, // sub_64 0, // sub_dsp16_19 0, // sub_dsp20 0, // sub_dsp21 0, // sub_dsp22 0, // sub_dsp23 70, // sub_hi -> ACC128 70, // sub_lo -> ACC128 70, // sub_hi_then_sub_32 -> ACC128 70, // sub_32_sub_hi_then_sub_32 -> ACC128 }, }; assert(RC && "Missing regclass"); if (!Idx) return RC; --Idx; assert(Idx < 11 && "Bad subreg"); unsigned TV = Table[RC->getID()][Idx]; return TV ? getRegClass(TV - 1) : nullptr; } /// Get the weight in units of pressure for this register class. const RegClassWeight &MipsGenRegisterInfo:: getRegClassWeight(const TargetRegisterClass *RC) const { static const RegClassWeight RCWeightTable[] = { {2, 64}, // MSA128F16 {0, 0}, // CCR {0, 0}, // COP0 {0, 0}, // COP2 {0, 0}, // COP3 {1, 32}, // DSPR {1, 32}, // FGR32 {1, 32}, // FGRCC {1, 32}, // GPR32 {0, 0}, // HWRegs {0, 0}, // MSACtrl {1, 31}, // GPR32NONZERO {1, 9}, // CPU16RegsPlusSP {1, 8}, // CPU16Regs {0, 0}, // FCC {1, 8}, // GPRMM16 {1, 8}, // GPRMM16MoveP {1, 8}, // GPRMM16Zero {1, 7}, // CPU16Regs_and_GPRMM16Zero {1, 7}, // GPR32NONZERO_and_GPRMM16MoveP {1, 5}, // GPRMM16MovePPairSecond {1, 4}, // CPU16Regs_and_GPRMM16MoveP {1, 4}, // GPRMM16MoveP_and_GPRMM16Zero {1, 4}, // HI32DSP {1, 4}, // LO32DSP {1, 3}, // CPU16Regs_and_GPRMM16MovePPairSecond {1, 3}, // GPRMM16MovePPairFirst {1, 3}, // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero {1, 2}, // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond {1, 1}, // CPURAReg {1, 1}, // CPUSPReg {1, 1}, // DSPCC {1, 1}, // GP32 {1, 1}, // GPR32ZERO {1, 1}, // HI32 {1, 1}, // LO32 {1, 1}, // SP32 {2, 64}, // FGR64 {1, 32}, // GPR64 {1, 31}, // GPR64_with_sub_32_in_GPR32NONZERO {2, 32}, // AFGR64 {1, 9}, // GPR64_with_sub_32_in_CPU16RegsPlusSP {1, 8}, // GPR64_with_sub_32_in_CPU16Regs {1, 8}, // GPR64_with_sub_32_in_GPRMM16MoveP {1, 8}, // GPR64_with_sub_32_in_GPRMM16Zero {1, 7}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero {1, 7}, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP {1, 5}, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond {2, 8}, // ACC64DSP {1, 4}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP {1, 4}, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero {1, 3}, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond {1, 3}, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst {1, 3}, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero {0, 0}, // OCTEON_MPL {0, 0}, // OCTEON_P {1, 2}, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond {2, 2}, // ACC64 {1, 1}, // GP64 {1, 1}, // GPR64_with_sub_32_in_CPURAReg {1, 1}, // GPR64_with_sub_32_in_GPR32ZERO {1, 1}, // HI64 {1, 1}, // LO64 {1, 1}, // SP64 {2, 64}, // MSA128B {2, 64}, // MSA128D {2, 64}, // MSA128H {2, 64}, // MSA128W {2, 32}, // MSA128WEvens {2, 2}, // ACC128 }; return RCWeightTable[RC->getID()]; } /// Get the weight in units of pressure for this register unit. unsigned MipsGenRegisterInfo:: getRegUnitWeight(unsigned RegUnit) const { assert(RegUnit < 321 && "invalid register unit"); // All register units have unit weight. return 1; } // Get the number of dimensions of register pressure. unsigned MipsGenRegisterInfo::getNumRegPressureSets() const { return 20; } // Get the name of this register unit pressure set. const char *MipsGenRegisterInfo:: getRegPressureSetName(unsigned Idx) const { static const char *const PressureNameTable[] = { "DSPCC", "GPR32ZERO", "GPR64_with_sub_32_in_CPURAReg", "HI32", "GPRMM16MovePPairFirst", "CPU16Regs_and_GPRMM16MoveP", "HI32DSP", "LO32DSP", "GPRMM16MovePPairSecond", "GPRMM16MoveP", "ACC64DSP", "CPU16Regs", "GPRMM16Zero+GPRMM16MovePPairSecond", "CPU16Regs+GPRMM16MovePPairSecond", "CPU16Regs+GPRMM16MoveP", "DSPR", "FGR32", "MSA128WEvens", "FGR32+MSA128WEvens", "MSA128F16", }; return PressureNameTable[Idx]; } // Get the register unit pressure limit for this dimension. // This limit must be adjusted dynamically for reserved registers. unsigned MipsGenRegisterInfo:: getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const { static const uint8_t PressureLimitTable[] = { 1, // 0: DSPCC 1, // 1: GPR32ZERO 1, // 2: GPR64_with_sub_32_in_CPURAReg 2, // 3: HI32 3, // 4: GPRMM16MovePPairFirst 5, // 5: CPU16Regs_and_GPRMM16MoveP 5, // 6: HI32DSP 5, // 7: LO32DSP 6, // 8: GPRMM16MovePPairSecond 8, // 9: GPRMM16MoveP 8, // 10: ACC64DSP 10, // 11: CPU16Regs 10, // 12: GPRMM16Zero+GPRMM16MovePPairSecond 11, // 13: CPU16Regs+GPRMM16MovePPairSecond 13, // 14: CPU16Regs+GPRMM16MoveP 32, // 15: DSPR 32, // 16: FGR32 32, // 17: MSA128WEvens 48, // 18: FGR32+MSA128WEvens 64, // 19: MSA128F16 }; return PressureLimitTable[Idx]; } /// Table of pressure sets per register class or unit. static const int RCSetsTable[] = { /* 0 */ 0, -1, /* 2 */ 6, 10, -1, /* 5 */ 3, 6, 7, 10, -1, /* 10 */ 2, 15, -1, /* 13 */ 8, 12, 13, 15, -1, /* 18 */ 9, 14, 15, -1, /* 22 */ 1, 5, 9, 11, 12, 14, 15, -1, /* 30 */ 5, 9, 11, 13, 14, 15, -1, /* 37 */ 4, 8, 11, 12, 13, 14, 15, -1, /* 45 */ 5, 9, 11, 12, 13, 14, 15, -1, /* 53 */ 16, 18, 19, -1, /* 57 */ 16, 17, 18, 19, -1, }; /// Get the dimensions of register pressure impacted by this register class. /// Returns a -1 terminated array of pressure set IDs const int* MipsGenRegisterInfo:: getRegClassPressureSets(const TargetRegisterClass *RC) const { static const uint8_t RCSetStartTable[] = { 55,1,1,1,1,11,53,53,11,1,1,11,32,32,1,32,18,25,39,18,13,30,23,2,7,38,37,45,37,1,1,0,1,22,5,5,1,55,11,11,53,32,32,18,25,39,18,13,3,30,23,38,37,45,1,1,37,5,1,10,22,5,5,1,55,55,55,55,58,5,}; return &RCSetsTable[RCSetStartTable[RC->getID()]]; } /// Get the dimensions of register pressure impacted by this register unit. /// Returns a -1 terminated array of pressure set IDs const int* MipsGenRegisterInfo:: getRegUnitPressureSets(unsigned RegUnit) const { assert(RegUnit < 321 && "invalid register unit"); static const uint8_t RUSetStartTable[] = { 11,0,1,1,1,1,1,1,1,1,1,11,11,1,1,1,1,1,1,1,1,1,10,32,22,37,37,37,38,5,5,7,2,7,2,7,2,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,11,11,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,30,45,18,18,18,13,13,11,11,11,11,11,11,11,11,11,11,11,45,45,}; return &RCSetsTable[RUSetStartTable[RegUnit]]; } extern const MCRegisterDesc MipsRegDesc[]; extern const MCPhysReg MipsRegDiffLists[]; extern const LaneBitmask MipsLaneMaskLists[]; extern const char MipsRegStrings[]; extern const char MipsRegClassStrings[]; extern const MCPhysReg MipsRegUnitRoots[][2]; extern const uint16_t MipsSubRegIdxLists[]; extern const MCRegisterInfo::SubRegCoveredBits MipsSubRegIdxRanges[]; extern const uint16_t MipsRegEncodingTable[]; // Mips Dwarf<->LLVM register mappings. extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[]; extern const unsigned MipsDwarfFlavour0Dwarf2LSize; extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[]; extern const unsigned MipsEHFlavour0Dwarf2LSize; extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[]; extern const unsigned MipsDwarfFlavour0L2DwarfSize; extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[]; extern const unsigned MipsEHFlavour0L2DwarfSize; MipsGenRegisterInfo:: MipsGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour, unsigned PC, unsigned HwMode) : TargetRegisterInfo(MipsRegInfoDesc, RegisterClasses, RegisterClasses+70, SubRegIndexNameTable, SubRegIndexLaneMaskTable, LaneBitmask(0xFFFFFF80), RegClassInfos, HwMode) { InitMCRegisterInfo(MipsRegDesc, 442, RA, PC, MipsMCRegisterClasses, 70, MipsRegUnitRoots, 321, MipsRegDiffLists, MipsLaneMaskLists, MipsRegStrings, MipsRegClassStrings, MipsSubRegIdxLists, 12, MipsSubRegIdxRanges, MipsRegEncodingTable); switch (DwarfFlavour) { default: llvm_unreachable("Unknown DWARF flavour"); case 0: mapDwarfRegsToLLVMRegs(MipsDwarfFlavour0Dwarf2L, MipsDwarfFlavour0Dwarf2LSize, false); break; } switch (EHFlavour) { default: llvm_unreachable("Unknown DWARF flavour"); case 0: mapDwarfRegsToLLVMRegs(MipsEHFlavour0Dwarf2L, MipsEHFlavour0Dwarf2LSize, true); break; } switch (DwarfFlavour) { default: llvm_unreachable("Unknown DWARF flavour"); case 0: mapLLVMRegsToDwarfRegs(MipsDwarfFlavour0L2Dwarf, MipsDwarfFlavour0L2DwarfSize, false); break; } switch (EHFlavour) { default: llvm_unreachable("Unknown DWARF flavour"); case 0: mapLLVMRegsToDwarfRegs(MipsEHFlavour0L2Dwarf, MipsEHFlavour0L2DwarfSize, true); break; } } static const MCPhysReg CSR_Interrupt_32_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, Mips::LO0, Mips::HI0, 0 }; static const uint32_t CSR_Interrupt_32_RegMask[] = { 0x07c80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00000000, 0x00000008, 0x07ffbfc0, 0x00000000, 0x00000000, 0x00000000, }; static const MCPhysReg CSR_Interrupt_32R6_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, 0 }; static const uint32_t CSR_Interrupt_32R6_RegMask[] = { 0x03c80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x07ffbfc0, 0x00000000, 0x00000000, 0x00000000, }; static const MCPhysReg CSR_Interrupt_64_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::V1_64, Mips::V0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, Mips::LO0_64, Mips::HI0_64, 0 }; static const uint32_t CSR_Interrupt_64_RegMask[] = { 0x47c80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x30000000, 0x00000000, 0x00000008, 0x07ffbfe0, 0xf0000000, 0x00000001, 0x03ffffe4, }; static const MCPhysReg CSR_Interrupt_64R6_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::V1_64, Mips::V0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, 0 }; static const uint32_t CSR_Interrupt_64R6_RegMask[] = { 0x43c80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x10000000, 0x00000000, 0x00000000, 0x07ffbfe0, 0xf0000000, 0x00000000, 0x03ffffc0, }; static const MCPhysReg CSR_Mips16RetHelper_SaveList[] = { Mips::V0, Mips::V1, Mips::FP, Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, 0 }; static const uint32_t CSR_Mips16RetHelper_RegMask[] = { 0x03c00100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x06003fc0, 0x00000000, 0x00000000, 0x00000000, }; static const MCPhysReg CSR_N32_SaveList[] = { Mips::D20_64, Mips::D22_64, Mips::D24_64, Mips::D26_64, Mips::D28_64, Mips::D30_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 }; static const uint32_t CSR_N32_RegMask[] = { 0x00080300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x08000000, 0x15550000, 0x00000000, 0x00000000, 0x00003fe0, 0x00000000, 0xaaa00000, 0x00003fc0, }; static const MCPhysReg CSR_N64_SaveList[] = { Mips::D31_64, Mips::D30_64, Mips::D29_64, Mips::D28_64, Mips::D27_64, Mips::D26_64, Mips::D25_64, Mips::D24_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 }; static const uint32_t CSR_N64_RegMask[] = { 0x00080300, 0x00000000, 0x00000000, 0x00000000, 0x00007800, 0x0007f800, 0x08000000, 0x1ff00000, 0x00000000, 0x00000000, 0x00003fe0, 0x00000000, 0xfe000000, 0x00003fc1, }; static const MCPhysReg CSR_O32_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 }; static const uint32_t CSR_O32_RegMask[] = { 0x00080100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x00000000, 0x00000000, 0x00000000, }; static const MCPhysReg CSR_O32_FP64_SaveList[] = { Mips::D30_64, Mips::D28_64, Mips::D26_64, Mips::D24_64, Mips::D22_64, Mips::D20_64, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 }; static const uint32_t CSR_O32_FP64_RegMask[] = { 0x00080100, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x00000000, 0x05550000, 0x00000000, 0x00000000, 0x00003fc0, 0x00000000, 0xaaa00000, 0x00000000, }; static const MCPhysReg CSR_O32_FPXX_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 }; static const uint32_t CSR_O32_FPXX_RegMask[] = { 0x00080100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x00000000, 0x00000000, 0x00000000, }; static const MCPhysReg CSR_SingleFloatOnly_SaveList[] = { Mips::F31, Mips::F30, Mips::F29, Mips::F28, Mips::F27, Mips::F26, Mips::F25, Mips::F24, Mips::F23, Mips::F22, Mips::F21, Mips::F20, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 }; static const uint32_t CSR_SingleFloatOnly_RegMask[] = { 0x00080100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x00000000, 0x00000000, 0x00000000, }; ArrayRef MipsGenRegisterInfo::getRegMasks() const { static const uint32_t *const Masks[] = { CSR_Interrupt_32_RegMask, CSR_Interrupt_32R6_RegMask, CSR_Interrupt_64_RegMask, CSR_Interrupt_64R6_RegMask, CSR_Mips16RetHelper_RegMask, CSR_N32_RegMask, CSR_N64_RegMask, CSR_O32_RegMask, CSR_O32_FP64_RegMask, CSR_O32_FPXX_RegMask, CSR_SingleFloatOnly_RegMask, }; return makeArrayRef(Masks); } ArrayRef MipsGenRegisterInfo::getRegMaskNames() const { static const char *const Names[] = { "CSR_Interrupt_32", "CSR_Interrupt_32R6", "CSR_Interrupt_64", "CSR_Interrupt_64R6", "CSR_Mips16RetHelper", "CSR_N32", "CSR_N64", "CSR_O32", "CSR_O32_FP64", "CSR_O32_FPXX", "CSR_SingleFloatOnly", }; return makeArrayRef(Names); } const MipsFrameLowering * MipsGenRegisterInfo::getFrameLowering(const MachineFunction &MF) { return static_cast( MF.getSubtarget().getFrameLowering()); } } // end namespace llvm #endif // GET_REGINFO_TARGET_DESC