Lines Matching refs:AddOutputOperand

43     AddOutputOperand<HalPolicy>(model0, hidl_vec<uint32_t>{1, 1});
63     AddOutputOperand<HalPolicy>(model1, hidl_vec<uint32_t>{1, 1});
74     AddOutputOperand<HalPolicy>(model1, hidl_vec<uint32_t>{1, 1});
101     AddOutputOperand<HalPolicy>(model2, hidl_vec<uint32_t>{1, 1, 3, 4});
102     AddOutputOperand<HalPolicy>(model2, hidl_vec<uint32_t>{1, 1, 3, 4});
130     AddOutputOperand<HalPolicy>(model3, hidl_vec<uint32_t>{1, 1, 3, 4});
131     AddOutputOperand<HalPolicy>(model3,
203     AddOutputOperand<HalPolicy>(model, hidl_vec<uint32_t>{1, 1, 3, 4});
204     AddOutputOperand<HalPolicy>(model,
217     AddOutputOperand<HalPolicy>(model, hidl_vec<uint32_t>{1, 1});
220     AddOutputOperand<HalPolicy>(model, hidl_vec<uint32_t>{1, 1, 3, 4});