Lines Matching +full:- +full:d
3 * SPDX-License-Identifier: BSD-3-Clause
21 "PMU1: loading 2D acsm sequence\n"
24 "PMU1: loading 1D acsm sequence\n"
27 "PMU3: %d memclocks @ %d to get half of 300ns\n"
33 "PMU3: Running 1D search for left eye edge\n"
36 "PMU1: In Phase Left Edge Search cs %d\n"
39 "PMU1: Out of Phase Left Edge Search cs %d\n"
42 "PMU3: Running 1D search for right eye edge\n"
45 "PMU1: In Phase Right Edge Search cs %d\n"
48 "PMU1: Out of Phase Right Edge Search cs %d\n"
51 "PMU1: mxRdLat training pstate %d\n"
54 "PMU1: mxRdLat search for cs %d\n"
60 "PMU4: CS %d Dbyte %d worked with DFIMRL = %d DFICLKs\n"
63 "PMU3: MaxRdLat Read Lane err mask for csn %d, DFIMRL %2d DFIClks, dbyte %d = 0x%03x\n"
66 "PMU3: MaxRdLat Read Lane err mask for csn %d DFIMRL %2d, All dbytes = 0x%03x\n"
69 …"PMU: Error: CS%d failed to find a DFIMRL setting that worked for all bytes during MaxRdLat traini…
72 "PMU3: Smallest passing DFIMRL for all dbytes in CS%d = %d DFIClks\n"
78 "PMU: Error: Dbyte %d lane %d txDqDly passing region is too small (width = %d)\n"
81 "PMU10: Adjusting rxclkdly db %d nib %d from %d+%d=%d->%d\n"
84 "PMU4: TxDqDly Passing Regions (EyeLeft EyeRight -> EyeCenter) Units=1/32 UI\n"
87 "PMU4: DB %d Lane %d: %3d %3d -> %3d\n"
90 "PMU2: TXDQ delayLeft[%2d] = %3d (DISCONNECTED)\n"
93 "PMU2: TXDQ delayLeft[%2d] = %3d oopScaled = %3d selectOop %d\n"
96 "PMU2: TXDQ delayRight[%2d] = %3d (DISCONNECTED)\n"
99 "PMU2: TXDQ delayRight[%2d] = %3d oopScaled = %3d selectOop %d\n"
102 "PMU: Error: Dbyte %d lane %d txDqDly passing region is too small (width = %d)\n"
105 "PMU4: TxDqDly Passing Regions (EyeLeft EyeRight -> EyeCenter) Units=1/32 UI\n"
108 "PMU4: DB %d Lane %d: (DISCONNECTED)\n"
111 "PMU4: DB %d Lane %d: %3d %3d -> %3d\n"
114 "PMU3: Running 1D search csn %d for DM Right/NotLeft(%d) eye edge\n"
117 "PMU3: WrDq DM byte%2d with Errcnt %d\n"
120 "PMU3: WrDq DM byte%2d avgDly 0x%04x\n"
123 "PMU1: WrDq DM byte%2d with Errcnt %d\n"
126 "PMU: Error: Dbyte %d txDqDly DM training did not start inside the eye\n"
129 "PMU4: DM TxDqDly Passing Regions (EyeLeft EyeRight -> EyeCenter) Units=1/32 UI\n"
132 "PMU4: DB %d Lane %d: (DISCONNECTED)\n"
135 "PMU4: DB %d Lane %d: %3d %3d -> %3d\n"
138 "PMU: Error: Dbyte %d lane %d txDqDly DM passing region is too small (width = %d)\n"
141 "PMU3: Errcnt for MRD/MWD search nib %2d delay = (%d, 0x%02x) = %d\n"
147 "PMU: Error: Dbyte %d nibble %d found mutliple working coarse delay setting for MRD/MWD\n"
150 "PMU4: MRD Passing Regions (coarseVal, fineLeft fineRight -> fineCenter)\n"
153 "PMU4: MWD Passing Regions (coarseVal, fineLeft fineRight -> fineCenter)\n"
156 …"PMU10: Warning: DB %d nibble %d has multiple working coarse delays, %d and %d, choosing the small…
159 "PMU: Error: Dbyte %d nibble %d MRD/MWD passing region is too small (width = %d)\n"
162 "PMU4: DB %d nibble %d: %3d, %3d %3d -> %3d\n"
165 "PMU1: Start MRD/nMWD %d for csn %d\n"
168 "PMU2: RXDQS delayLeft[%2d] = %3d (DISCONNECTED)\n"
171 "PMU2: RXDQS delayLeft[%2d] = %3d delayOop[%2d] = %3d OopScaled %4d, selectOop %d\n"
174 "PMU2: RXDQS delayRight[%2d] = %3d (DISCONNECTED)\n"
177 "PMU2: RXDQS delayRight[%2d] = %3d delayOop[%2d] = %4d OopScaled %4d, selectOop %d\n"
180 "PMU4: RxClkDly Passing Regions (EyeLeft EyeRight -> EyeCenter)\n"
183 "PMU4: DB %d nibble %d: (DISCONNECTED)\n"
186 "PMU4: DB %d nibble %d: %3d %3d -> %3d\n"
189 "PMU: Error: Dbyte %d nibble %d rxClkDly passing region is too small (width = %d)\n"
192 "PMU0: goodbar = %d for RDWR_BLEN %d\n"
195 "PMU3: RxClkDly = %d\n"
198 "PMU0: db %d l %d absLane %d -> bottom %d top %d\n"
201 "PMU3: BYTE %d - %3d %3d %3d %3d %3d %3d %3d %3d\n"
204 "PMU: Error: dbyte %d lane %d's per-lane vrefDAC's had no passing region\n"
207 "PMU0: db%d l%d - %d %d\n"
210 "PMU0: goodbar = %d for RDWR_BLEN %d\n"
213 "PMU3: db%d l%d saw %d issues at rxClkDly %d\n"
216 "PMU3: db%d l%d first saw a pass->fail edge at rxClkDly %d\n"
219 "PMU3: lane %d PBD = %d\n"
222 "PMU3: db%d l%d first saw a DBI pass->fail edge at rxClkDly %d\n"
225 "PMU2: db%d l%d already passed rxPBD = %d\n"
228 "PMU0: db%d l%d, PBD = %d\n"
231 "PMU: Error: dbyte %d lane %d failed read deskew\n"
234 "PMU0: db%d l%d, inc PBD = %d\n"
237 "PMU1: Running lane deskew on pstate %d csn %d rdDBIEn %d\n"
243 "PMU1: AcsmCsMapCtrl%02d 0x%04x\n"
246 "PMU1: AcsmCsMapCtrl%02d 0x%04x\n"
267 "PMU10: PHY TOTALS - NUM_DBYTES %d NUM_NIBBLES %d NUM_ANIBS %d\n"
270 …"PMU10: CSA=0x%02x, CSB=0x%02x, TSTAGES=0x%04x, HDTOUT=%d, MMISC=%d DRAMFreq=%dMT DramType=LPDDR3\…
273 …"PMU10: CSA=0x%02x, CSB=0x%02x, TSTAGES=0x%04x, HDTOUT=%d, MMISC=%d DRAMFreq=%dMT DramType=LPDDR4\…
276 …"PMU10: CS=0x%02x, TSTAGES=0x%04x, HDTOUT=%d, 2T=%d, MMISC=%d AddrMirror=%d DRAMFreq=%dMT DramType…
279 "PMU10: Pstate%d MR0=0x%04x MR1=0x%04x MR2=0x%04x\n"
282 …"PMU10: Pstate%d MRS MR0=0x%04x MR1=0x%04x MR2=0x%04x MR3=0x%04x MR4=0x%04x MR5=0x%04x MR6=0x%04x\…
285 "PMU10: Pstate%d MRS MR1_A0=0x%04x MR2_A0=0x%04x MR3_A0=0x%04x MR11_A0=0x%04x\n"
291 "PMU10: Pstate%d MRS MR01_A0=0x%02x MR02_A0=0x%02x MR03_A0=0x%02x MR11_A0=0x%02x\n"
294 "PMU10: Pstate%d MRS MR12_A0=0x%02x MR13_A0=0x%02x MR14_A0=0x%02x MR22_A0=0x%02x\n"
297 "PMU10: Pstate%d MRS MR01_A1=0x%02x MR02_A1=0x%02x MR03_A1=0x%02x MR11_A1=0x%02x\n"
300 "PMU10: Pstate%d MRS MR12_A1=0x%02x MR13_A1=0x%02x MR14_A1=0x%02x MR22_A1=0x%02x\n"
303 "PMU10: Pstate%d MRS MR01_B0=0x%02x MR02_B0=0x%02x MR03_B0=0x%02x MR11_B0=0x%02x\n"
306 "PMU10: Pstate%d MRS MR12_B0=0x%02x MR13_B0=0x%02x MR14_B0=0x%02x MR22_B0=0x%02x\n"
309 "PMU10: Pstate%d MRS MR01_B1=0x%02x MR02_B1=0x%02x MR03_B1=0x%02x MR11_B1=0x%02x\n"
312 "PMU10: Pstate%d MRS MR12_B1=0x%02x MR13_B1=0x%02x MR14_B1=0x%02x MR22_B1=0x%02x\n"
315 "PMU1: AcsmOdtCtrl%02d 0x%02x\n"
318 "PMU1: AcsmCsMapCtrl%02d 0x%04x\n"
321 "PMU1: AcsmCsMapCtrl%02d 0x%04x\n"
327 "PMU3: DDR4 infinite preamble enter/exit mode %d\n"
330 "PMU1: In rxenb_train() csn=%d pstate=%d\n"
345 "PMU3: Preamble search pass=%d anyfail=%d\n"
351 "PMU3: Found DQS pre-amble\n"
354 "PMU: Error: Dbyte %d couldn't find the rising edge of DQS during RxEn Training\n"
360 "PMU3: Decreasing RxEn delay by %d fine step to allow full capture of reads\n"
363 "PMU3: MREP Delay = %d\n"
366 "PMU3: Errcnt for MREP nib %2d delay = %2d is %d\n"
369 "PMU3: MREP nibble %d sampled a 1 at data buffer delay %d\n"
372 "PMU3: MREP nibble %d saw a 0 to 1 transition at data buffer delay %d\n"
378 "PMU2: Rising edge found in alias window, setting rxDly for nibble %d = %d\n"
381 "PMU: Error: Failed MREP for nib %d with %d one\n"
384 "PMU2: Rising edge not found in alias window with %d one, leaving rxDly for nibble %d = %d\n"
387 "PMU3: Training DIMM %d CSn %d\n"
408 "PMU3: DEBUG enterCAtrain_lp4 3: Put dbyte %d in async mode\n"
414 "PMU3: DEBUG enterCAtrain_lp4 7: idx = %d vref = %x mr12 = %x\n"
420 "PMU3: Phase %d CAreadbackA db:%d %x xo:%x\n"
423 "PMU3: DEBUG lp4SetCatrVref 1: cs=%d chan=%d mr12=%x vref=%d.%d%%\n"
426 "PMU3: DEBUG lp4SetCatrVref 3: mr12 = %x send vref= %x to db=%d\n"
432 "PMU4:mr12:%2x cs:%d chan %d r:%4x\n"
435 "PMU3: i:%2d bstr:%2d bsto:%2d st:%d r:%d\n"
438 "Failed to find sufficient CA Vref Passing Region for CS %d ch. %d\n"
441 "PMU3:Found %d.%d%% MR12:%x for cs:%d chan %d\n"
444 "PMU3:Calculated %d for AtxImpedence from acx %d.\n"
450 "PMU3:Calculated %d.%d%% for Vref MR12=0x%x.\n"
459 "PMU3: CAtrain_lp testing dly %d\n"
465 "PMU5: CAA%d "
472 "PMU5: CAB%d "
479 "PMU3: anibi=%d, anibichan[anibi]=%d ,chan=%d\n"
485 {0x009e0002, "\nPMU3:ATxDly setting:%x margin:%d\n"
487 {0x009f0002, "\nPMU3:InvClk ATxDly setting:%x margin:%d\n"
492 "PMU3: 2 anibi=%d, anibichan[anibi]=%d ,chan=%d"
494 {0x00a20002, "\nPMU3: no neg clock => CA setting anib=%d, :%d\n"
497 "PMU3:Normal margin:%d\n"
500 "PMU3:Inverted margin:%d\n"
509 "PMU3: 3 anibi=%d, anibichan[anibi]=%d ,chan=%d\n"
521 "PMU4:Using MR12 values from 1D CA VREF training.\n"
533 "PMU10: Setting boot clock divider to %d\n"
548 "PMU10: **** Executing 2D Image ****\n"
566 "PMU10: **** Testchip %d Specific Firmware ****\n"
614 "PMU2: Starting SI friendly 1d RdDqs training for all ranks\n"
620 "PMU2: Starting 1d WrDq training for all ranks\n"
629 "PMU2: Starting 1d RdDqs training for all ranks\n"
632 "PMU2: Starting again 1d WrDq training for all ranks\n"
638 "PMU2: Starting 2d WrDq training for all ranks\n"
641 "PMU2: Starting 2d RdDqs training for all ranks\n"
656 "PMU3: fixRxEnBackOff csn:%d db:%d dn:%d bo:%d dly:%x\n"
668 "PMU3:Dbyte Detect: db%d received %x\n"
671 "PMU3:getDqs2Dq read %x from dbyte %d\n"
674 "PMU3:getDqs2Dq(2) read %x from dbyte %d\n"
677 "PMU: Error: Dbyte %d read 0 from the DQS oscillator it is connected to\n"
680 "PMU4: Dbyte %d dqs2dq = %d/32 UI\n"
683 "PMU3:getDqs2Dq set dqs2dq:%d/32 ui (%d ps) from dbyte %d\n"
686 "PMU3: Setting coarse delay in AtxDly chiplet %d from 0x%02x to 0x%02x\n"
689 "PMU3: Clearing coarse delay in AtxDly chiplet %d from 0x%02x to 0x%02x\n"
707 "PMU1: DDR4 update Rx DBI Setting disable %d\n"
710 "PMU1: DDR4 update 2nCk WPre Setting disable %d\n"
713 "PMU1: read_delay: db%d lane%d delays[%2d] = 0x%02x (max 0x%02x)\n"
716 "PMU1: write_delay: db%d lane%d delays[%2d] = 0x%04x\n"
719 "PMU5: ID=%d -- db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 --\n"
722 "PMU5: [%d]:0x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x\n"
725 "PMU2: dump delays - pstate=%d dimm=%d csn=%d\n"
728 "PMU3: Printing Mid-Training Delay Information\n"
731 "PMU5: CS%d <<KEY>> 0 TrainingCntr <<KEY>> coarse(15:10) fine(9:0)\n"
734 "PMU5: CS%d <<KEY>> 0 RxEnDly, 1 RxClkDly <<KEY>> coarse(10:6) fine(5:0)\n"
737 "PMU5: CS%d <<KEY>> 0 TxDqsDly, 1 TxDqDly <<KEY>> coarse(9:6) fine(5:0)\n"
740 "PMU5: CS%d <<KEY>> 0 RxPBDly <<KEY>> 1 Delay Unit ~= 7ps\n"
755 "PMU2: getMaxRxen(): maxDly %d maxTg %d maxNib %d\n"
758 "PMU2: getRankMaxRxen(): maxDly %d Tg %d maxNib %d\n"
761 "PMU1: skipping CDD calculation in 2D image\n"
764 "PMU3: Calculating CDDs for pstate %d\n"
767 "PMU3: rxFromDly[%d][%d] = %d\n"
770 "PMU3: rxToDly [%d][%d] = %d\n"
773 "PMU3: rxDly [%d][%d] = %d\n"
776 "PMU3: txDly [%d][%d] = %d\n"
779 "PMU3: allFine CDD_RR_%d_%d = %d\n"
782 "PMU3: allFine CDD_WW_%d_%d = %d\n"
785 "PMU3: CDD_RR_%d_%d = %d\n"
788 "PMU3: CDD_WW_%d_%d = %d\n"
791 "PMU3: allFine CDD_RW_%d_%d = %d\n"
794 "PMU3: allFine CDD_WR_%d_%d = %d\n"
797 "PMU3: CDD_RW_%d_%d = %d\n"
800 "PMU3: CDD_WR_%d_%d = %d\n"
803 "PMU3: F%dBC2x_B%d_D%d = 0x%02x\n"
806 "PMU3: F%dBC3x_B%d_D%d = 0x%02x\n"
809 "PMU3: F%dBC4x_B%d_D%d = 0x%02x\n"
812 "PMU3: F%dBC5x_B%d_D%d = 0x%02x\n"
815 "PMU3: F%dBC8x_B%d_D%d = 0x%02x\n"
818 "PMU3: F%dBC9x_B%d_D%d = 0x%02x\n"
821 "PMU3: F%dBCAx_B%d_D%d = 0x%02x\n"
824 "PMU3: F%dBCBx_B%d_D%d = 0x%02x\n"
830 "PMU10: context_switch_postamble is enabled for DIMM %d, RC0A=0x%x, RC3x=0x%x\n"
851 "PMU1: enter_lp3: DEBUG: pstate = %d\n"
854 "PMU1: enter_lp3: DEBUG: dfifreqxlat_pstate = %d\n"
857 "PMU1: enter_lp3: DEBUG: pllbypass = %d\n"
860 "PMU1: enter_lp3: DEBUG: forcecal = %d\n"
875 "PMU3: Setting DataBuffer function space of dimmcs 0x%02x to %d\n"
884 "PMU1: DDR4 update Rd Pre Setting disable %d\n"
899 "PMU4: BCW value for dimm %d, fspace %d, addr 0x%04x\n"
902 "PMU4: DB %d, value 0x%02x\n"
905 "PMU6: WARNING MREP underflow, set to min value -2 coarse, 0 fine\n"
908 … Writing final data buffer fine delay value nib %2d, trainDly %3d, fineDly code %2d, new MREP fine…
911 …"PMU6: LRDIMM Writing final data buffer fine delay value nib %2d, trainDly %3d, fineDly code %2d\n"
914 "PMU6: LRDIMM Writing data buffer fine delay type %d nib %2d, code %2d\n"
917 "PMU6: Writing final data buffer coarse delay value dbyte %2d, coarse = 0x%02x\n"
932 "PMU3: Update BC00, BC01, BC02 for rank-dimm 0x%02x\n"
935 "PMU3: Writing D4 RDIMM RCD Control words F0RC00 -> F0RC0F\n"
941 "PMU3: Writing D4 RDIMM RCD Control words F1RC00 -> F1RC05\n"
944 "PMU3: Writing D4 RDIMM RCD Control words F1RC1x -> F1RC9x\n"
947 "PMU3: Writing D4 Data buffer Control words BC00 -> BC0E\n"
950 "PMU1: setAltCL Sending MR0 0x%x cl=%d\n"
953 "PMU1: restoreFromAltCL Sending MR0 0x%x cl=%d\n"
956 "PMU1: restoreAcsmFromAltCL Sending MR0 0x%x cl=%d\n"
959 "PMU2: Setting D3R RC%d = 0x%01x\n"
962 "PMU3: Writing D3 RDIMM RCD Control words RC0 -> RC11\n"
965 "PMU0: VrefDAC0/1 vddqStart %d dacToVddq %d\n"
974 "PMU0: PHY VREF @ (%d/1000) VDDQ\n"
977 "PMU0: initalizing phy vrefDacs to %d ExtVrefRange %x\n"
980 "PMU0: initalizing global vref to %d range %d\n"
983 "PMU4: Setting initial device vrefDQ for CS%d to MR6 = 0x%04x\n"
986 "PMU1: In write_level_fine() csn=%d dimm=%d pstate=%d\n"
995 "PMU4: WL margin for nib %2d: %08x%08x%08x%08x%08x%08x\n"
1004 "PMU3: got %d for cl in load_wrlvl_acsm\n"
1007 "PMU1: In write_level_coarse() csn=%d dimm=%d pstate=%d\n"
1010 "PMU3: left eye edge search db:%d ln:%d dly:0x%x\n"
1013 "PMU3: right eye edge search db:%d ln:%d dly:0x%x\n"
1016 "PMU3: eye center db:%d ln:%d dly:0x%x (maxdq:%x)\n"
1019 "PMU3: Wrote to TxDqDly db:%d ln:%d dly:0x%x\n"
1022 "PMU3: Wrote to TxDqDly db:%d ln:%d dly:0x%x\n"
1025 "PMU3: Coarse write leveling dbyte%2d is still failing for TxDqsDly=0x%04x\n"
1028 "PMU4: Coarse write leveling iteration %d saw %d data miscompares across the entire phy\n"
1034 "PMU3: got %d for cl in load_wrlvl_acsm\n"
1037 "PMU3: In write_level_coarse() csn=%d dimm=%d pstate=%d\n"
1040 "PMU3: left eye edge search db:%d ln:%d dly:0x%x\n"
1043 "PMU3: right eye edge search db: %d ln: %d dly: 0x%x\n"
1046 "PMU3: eye center db: %d ln: %d dly: 0x%x (maxdq: 0x%x)\n"
1049 "PMU3: Wrote to TxDqDly db: %d ln: %d dly: 0x%x\n"
1052 "PMU3: Wrote to TxDqDly db: %d ln: %d dly: 0x%x\n"
1055 "PMU3: Coarse write leveling nibble%2d is still failing for TxDqsDly=0x%04x\n"
1058 "PMU4: Coarse write leveling iteration %d saw %d data miscompares across the entire phy\n"
1067 "PMU4: WL margin for nib %2d: %08x%08x%08x%08x%08x%08x%08x%08x\n"
1073 "PMU8: Adjust margin after WL coarse to be larger than %d\n"
1076 "PMU: Error: All margin after write leveling coarse are smaller than minMargin %d\n"
1079 "PMU8: Decrement nib %d TxDqsDly by %d fine step\n"
1082 "PMU3: In write_level_coarse() csn=%d dimm=%d pstate=%d\n"
1085 "PMU2: Write level: dbyte %d nib%d dq/dmbi %2d dqsfine 0x%04x dqDly 0x%04x\n"
1088 "PMU3: Coarse write leveling nibble%2d is still failing for TxDqsDly=0x%04x\n"
1091 "PMU4: Coarse write leveling iteration %d saw %d data miscompares across the entire phy\n"
1097 "PMU3: DWL delay = %d\n"
1100 "PMU3: Errcnt for DWL nib %2d delay = %2d is %d\n"
1103 "PMU3: DWL nibble %d sampled a 1 at delay %d\n"
1106 "PMU3: DWL nibble %d passed at delay %d. Rising edge was at %d\n"
1112 "PMU2: Rising edge found in alias window, setting wrlvlDly for nibble %d = %d\n"
1115 "PMU: Error: Failed DWL for nib %d with %d one\n"
1118 "PMU2: Rising edge not found in alias window with %d one, leaving wrlvlDly for nibble %d = %d\n"
1127 "PMU: ***** Assertion Error - terminating *****\n"
1130 "PMU1: swapByte db %d by %d\n"
1133 "PMU3: get_cmd_dly max(%d ps, %d memclk) = %d\n"
1139 "PMU0: hwt_init_ppgc_prbs(): Polynomial: %x, Deg: %d\n"
1142 "PMU: Error: acsm_set_cmd to non existent instruction address %d\n"
1163 "PMU: Error: setAcsmCLCWL: cl and cwl must be each >= 2 and 5, resp. CL=%d CWL=%d\n"
1166 "PMU: Error: setAcsmCLCWL: cl and cwl must be each >= 5. CL=%d CWL=%d\n"
1169 "PMU1: setAcsmCLCWL: CASL %04d WCASL %04d\n"
1184 "PMU: Error: Boot clock divider setting of %d is too small\n"
1190 "PMU3: Writing MR%d OP=%x\n"
1208 "PMU2: Use PDA mode to set MR%d with value 0x%02x\n"
1220 "PMU1: lock_pll_dll: DEBUG: pstate = %d\n"
1223 "PMU1: lock_pll_dll: DEBUG: dfifreqxlat_pstate = %d\n"
1226 "PMU1: lock_pll_dll: DEBUG: pllbypass = %d\n"
1229 "PMU3: SaveLcdlSeed: Saving seed %d\n"
1235 "PMU3: ACXConf:%d MaxNumDbytes:%d NumDfi:%d\n"
1238 "PMU1: setAltAcsmCLCWL setting cl=%d cwl=%d\n"
1244 "PMU0: Converting %d into an MR\n"
1247 "PMU DEBUG: vref_idx %d -= %d, range_idx = %d\n"
1250 "PMU0: vrefIdx. Passing range %d, remaining vrefidx = %d\n"
1253 "PMU0: VrefIdx %d -> MR[6:0] 0x%02x\n"
1259 "PMU0: DAC %d Range %d\n"
1262 "PMU0: Range %d, Range_idx %d, vref_idx offset %d\n"
1265 "PMU0: MR 0x%04x -> VrefIdx %d\n"
1268 "PMU: Error: Illegal timing group number ,%d, in getPtrVrefDq\n"
1271 "PMU1: VrefDqR%dNib%d = %d\n"
1274 "PMU0: VrefDqR%dNib%d = %d\n"
1277 "PMU0: ----------------MARGINS-------\n"
1280 "PMU0: R%d_RxClkDly_Margin = %d\n"
1283 "PMU0: R%d_VrefDac_Margin = %d\n"
1286 "PMU0: R%d_TxDqDly_Margin = %d\n"
1289 "PMU0: R%d_DeviceVref_Margin = %d\n"
1292 "PMU0: -----------------------\n"
1295 "PMU0: eye %d's for all TG's is [%d ... %d]\n"
1298 "PMU0: ------- settingWeight -----\n"
1301 "PMU0: Weight %d @ Setting %d\n"
1304 …"PMU4: %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d >%3d< %3d %3d %3d %3d %3d %3d %…
1307 "PMU3: Voltage Range = [%d, %d]\n"
1310 "PMU4: -- DB%d L%d -- centers: delay = %d, voltage = %d\n"
1313 "PMU5: <<KEY>> 0 TxDqDlyTg%d <<KEY>> coarse(6:6) fine(5:0)\n"
1316 "PMU5: <<KEY>> 0 messageBlock VrefDqR%d <<KEY>> MR6(6:0)\n"
1319 "PMU5: <<KEY>> 0 RxClkDlyTg%d <<KEY>> fine(5:0)\n"
1322 "PMU0: tgToCsn: tg %d + 0x%04x -> csn %d\n"
1325 "PMU: Error: LP4 rank %d cannot be mapped on tg %d\n"
1328 "PMU3: Sending vref %d, Mr = 0X%05x, to all devices\n"
1331 "PMU4: -------- %dD Write Scanning TG %d (CS 0x%x) Lanes 0x%03x --------\n"
1337 "PMU4: ------- 2D-DFE Read Scanning TG %d (CS 0x%x) Lanes 0x%03x -------\n"
1340 "PMU4: ------- %dD Read Scanning TG %d (CS 0x%x) Lanes 0x%03x -------\n"
1343 "PMU4: TG%d MR1[13,6,5]=0x%x MR6[13,9,8]=0x%x\n"
1349 "PMU4: ------- 2D-DFE Read Scanning TG %d (CS 0x%x) Lanes 0x%03x -------\n"
1352 "PMU4: ------- %dD Read Scanning TG %d (CS 0x%x) Lanes 0x%03x -------\n"
1358 "PMU3: Sending vref %d, Mr = 0X%05x, to all devices\n"
1361 "PMU4: -------- %dD Write Scanning TG %d (CS 0x%x) Lanes 0x%03x --------\n"
1364 "PMU0: input %d\n"
1367 "PMU4: Programmed Voltage Search Range [%d, %d]\n"
1370 "PMU3: Delay Stepsize = %d Fine, Voltage Stepsize = %d DAC\n"
1373 "PMU4: Delay Weight = %d, Voltage Weight = %d\n"
1376 "PMU0: raw 0x%x allFine %d incDec %d"
1379 "PMU0: db%d l%d, voltage 0x%x (u_r %d) delay 0x%x (u_r %d) - lcdl %d mask 0x%x\n"
1382 "PMU0: DB%d L%d, Eye %d, Seed = (0x%x, 0x%x)\n"
1385 "PMU3: 2D Enables : %d, 1, %d\n"
1388 "PMU3: 2D Delay Ranges: OOPL[0x%04x,0x%04x], IP[0x%04x,0x%04x], OOPR[0x%04x,0x%04x]\n"
1391 "PMU3: 2D Voltage Search Range : [%d, %d]\n"
1394 "PMU4: Found Voltage Search Range [%d, %d]\n"
1397 "PMU0: User Weight = %d, Voltage Weight = %d\n"
1400 "PMU0: D(%d,%d) V(%d,%d | %d)\n"
1403 "PMU0: Norm Weight = %d, Voltage Weight = %d\n"
1406 "PMU0: seed 0 = (%d,%d) (center)\n"
1409 "PMU0: seed 1 = (%d,%d).min edge at idx %d\n"
1412 "PMU0: seed 2 = (%d,%d) max edge at idx %d\n"
1415 "PMU0: Search point %d = (%d,%d)\n"
1418 "PMU0: YMARGIN: ^ %d, - %d, v %d. rate %d = %d\n"
1421 "PMU0: XMARGIN: center %d, edge %d. = %d\n"
1424 "PMU0: ----------- weighting (%d,%d) ----------------\n"
1427 "PMU0: X margin - L %d R %d - Min %d\n"
1430 "PMU0: Y margin - L %d R %d - Min %d\n"
1433 "PMU0: center (%d,%d) weight = %d\n"
1436 "PMU4: Eye argest blob area %d from %d to %d\n"
1439 "PMU0: Compute centroid min_x %d max_x %d\n"
1442 "PMU0: Compute centroid sumLnDlyWidth %d sumLnVrefWidth %d sumLnWidht %d\n"
1448 "PMU0: Centroid ( %d, %d ) found with sumLnWidht %d\n"
1451 "PMU0: Optimal allFine Center ( %d + %d ,%d )\n"
1454 "PMU3: point %d starting at (%d,%d)\n"
1457 "PMU0: picking left (%d > %d)\n"
1460 "PMU0: picking right (%d > %d)\n"
1463 "PMU0: picking down (%d > %d)\n"
1466 "PMU0: picking up (%d > %d)\n"
1469 "PMU3: new center @ (%3d, %3d). Moved (%2i, %2i) -- L %d, R %d, C %d, U %d, D %d\n"
1472 "PMU3: cordNum %d imporved %d to %d\n"
1478 "PMU0: Optimal allFine Center ( %d + %d ,%d ), found with weight %d.\n"
1481 "PMU0: merging lanes=%d..%d, centerMerge_t %d\n"
1484 "PMU0: laneVal %d is disable\n"
1487 "PMU0: checking common center %d against current center %d\n"
1490 "PMU: Error: getCompoundEye Called on lane%d eye with non-compatible centers\n"
1493 "PMU0: laneItr %d is disable\n"
1496 "PMU0: lane %d, data_idx %d, offset_idx %d, = [%d..%d]\n"
1499 "PMU0: lane %d, data_idx %d, offset_idx %d, offset_idx out of range!\n"
1502 "PMU0: mergeData[%d] = max_v_low %d, min_v_high %d\n"
1505 "PMU1: writing merged center (%d,%d) back to dataBlock[%d]. doDelay %d, doVoltage %d\n"
1508 "PMU0: applying relative (%i,%i) back to dataBlock[%d]. doDelay %d, doVoltage %d\n"
1511 "PMU0: drvstren %x is idx %d in the table\n"
1517 "PMU5: Weak 1 changed to pull-up %5d ohms, pull-down %5d ohms\n"
1520 "PMU5: Weak 0 changed to pull-up %5d ohms, pull-down %5d ohms\n"
1523 "PMU0: dlyMargin L %02d R %02d, min %02d\n"
1526 "PMU0: vrefMargin T %02d B %02d, min %02d\n"
1529 "PMU3: new minimum VrefMargin (%d < %d) recorded\n"
1532 "PMU3: new minimum DlyMargin (%d < %d) recorded\n"
1535 "PMU0: RX finding the per-nibble, per-tg rxClkDly values\n"
1538 "PMU0: Merging collected eyes [%d..%d) and analyzing for nibble %d's optimal rxClkDly\n"
1541 "PMU0: -- centers: delay = %d, voltage = %d\n"
1544 "PMU0: dumping optimized eye -- centers: delay = %d (%d), voltage = %d\n"
1550 "PMU3: Analyzing collected eye %d for a lane's optimal TxDqDly\n"
1553 "PMU0: eye-lane %d is disable\n"
1559 "PMU0: Merging collected eyes [%d..%d) and analyzing for optimal device txVref\n"
1562 "PMU0: -- centers: delay = %d, voltage = %d\n"
1565 "PMU0: dumping optimized eye -- centers: delay = %d (%d), voltage = %d\n"
1568 "PMU4: VrefDac (compound all TG) Bottom Top -> Center\n"
1571 "PMU4: DB%d L%d %3d %3d -> %3d (DISCONNECTED)\n"
1574 "PMU4: DB%d L%d %3d %3d -> %3d\n"
1577 "PMU0: writing rxClkDelay for tg%d db%1d nib%1d to 0x%02x from eye[%02d] (DISCONNECTED)\n"
1580 "PMU: Error: Dbyte %d nibble %d's optimal rxClkDly of 0x%x is out of bounds\n"
1583 "PMU0: writing rxClkDelay for tg%d db%1d nib%1d to 0x%02x from eye[%02d]\n"
1586 "PMU0: tx voltage for tg%2d nib%2d to %3d (%d) from eye[%02d]\n"
1589 "PMU0: vref Sum = %d\n"
1592 "PMU0: tx voltage total is %d/%d -> %d -> %d\n"
1595 …"PMU0: writing txDqDelay for tg%1d db%1d ln%1d to 0x%02x (%d coarse, %d fine) from eye[%02d] (DIS…
1598 "PMU: Error: Dbyte %d lane %d's optimal txDqDly of 0x%x is out of bounds\n"
1601 "PMU0: writing txDqDelay for tg%1d db%1d l%1d to 0x%02x (%d coarse, %d fine) from eye[%02d]\n"
1604 "PMU0: %d (0=tx, 1=rx) TgMask for this simulation: %x\n"
1607 "PMU0: eye-byte %d is disable\n"
1610 "PMU0: eye-lane %d is disable\n"
1613 "PMU10: Start d4_2d_lrdimm_rx_dfe dimm %d nbTap %d biasStepMode %d\n"
1622 "PMU8: Start d4_2d_lrdimm_rx_dfe for tap %d biasStepInc %d\n"
1628 "PMU6: d4_2d_lrdimm_rx_dfe db %d lane %d area %d\n"
1631 "PMU7: d4_2d_lrdimm_rx_dfe db %d lane %d max area %d best bias 0x%0x\n"
1634 "PMU0: eye-lane %d is disable\n"
1637 "PMU5: Setting 0x%x improved rank weight (%4d < %4d)\n"
1643 "PMU5: ---- Training CS%d MR%d DRAM Equalization ----\n"
1646 "PMU0: eye-lane %d is disable\n"
1649 "PMU0: eye %d weight %d allTgWeight %d\n"
1652 "PMU5: FFE figure of merit improved from %d to %d\n"
1655 "PMU: Error: LP4 rank %d cannot be mapped on tg %d\n"
1658 "PMU4: Adjusting vrefDac0 for just 1->x transitions\n"
1661 "PMU4: Adjusting vrefDac1 for just 0->x transitions\n"
1664 "PMU5: Strong 1, pull-up %d ohms\n"
1667 "PMU5: Strong 0, pull-down %d ohms\n"
1682 "PMU0: targeting CsX = %d and CsY = %d\n"
1688 "PMU1: loading 2D acsm sequence\n"
1691 "PMU1: loading 1D acsm sequence\n"
1694 "PMU3: %d memclocks @ %d to get half of 300ns\n"
1700 "PMU3: Running 1D search for left eye edge\n"
1703 "PMU1: In Phase Left Edge Search cs %d\n"
1706 "PMU1: Out of Phase Left Edge Search cs %d\n"
1709 "PMU3: Running 1D search for right eye edge\n"
1712 "PMU1: In Phase Right Edge Search cs %d\n"
1715 "PMU1: Out of Phase Right Edge Search cs %d\n"
1718 "PMU1: mxRdLat training pstate %d\n"
1721 "PMU1: mxRdLat search for cs %d\n"
1727 "PMU4: CS %d Dbyte %d worked with DFIMRL = %d DFICLKs\n"
1730 "PMU3: MaxRdLat Read Lane err mask for csn %d, DFIMRL %2d DFIClks, dbyte %d = 0x%03x\n"
1733 "PMU3: MaxRdLat Read Lane err mask for csn %d DFIMRL %2d, All dbytes = 0x%03x\n"
1736 …"PMU: Error: CS%d failed to find a DFIMRL setting that worked for all bytes during MaxRdLat traini…
1739 "PMU3: Smallest passing DFIMRL for all dbytes in CS%d = %d DFIClks\n"
1745 "PMU: Error: Dbyte %d lane %d txDqDly passing region is too small (width = %d)\n"
1748 "PMU10: Adjusting rxclkdly db %d nib %d from %d+%d=%d->%d\n"
1751 "PMU4: TxDqDly Passing Regions (EyeLeft EyeRight -> EyeCenter) Units=1/32 UI\n"
1754 "PMU4: DB %d Lane %d: %3d %3d -> %3d\n"
1757 "PMU2: TXDQ delayLeft[%2d] = %3d (DISCONNECTED)\n"
1760 "PMU2: TXDQ delayLeft[%2d] = %3d oopScaled = %3d selectOop %d\n"
1763 "PMU2: TXDQ delayRight[%2d] = %3d (DISCONNECTED)\n"
1766 "PMU2: TXDQ delayRight[%2d] = %3d oopScaled = %3d selectOop %d\n"
1769 "PMU: Error: Dbyte %d lane %d txDqDly passing region is too small (width = %d)\n"
1772 "PMU4: TxDqDly Passing Regions (EyeLeft EyeRight -> EyeCenter) Units=1/32 UI\n"
1775 "PMU4: DB %d Lane %d: (DISCONNECTED)\n"
1778 "PMU4: DB %d Lane %d: %3d %3d -> %3d\n"
1781 "PMU3: Running 1D search csn %d for DM Right/NotLeft(%d) eye edge\n"
1784 "PMU3: WrDq DM byte%2d with Errcnt %d\n"
1787 "PMU3: WrDq DM byte%2d avgDly 0x%04x\n"
1790 "PMU1: WrDq DM byte%2d with Errcnt %d\n"
1793 "PMU: Error: Dbyte %d txDqDly DM training did not start inside the eye\n"
1796 "PMU4: DM TxDqDly Passing Regions (EyeLeft EyeRight -> EyeCenter) Units=1/32 UI\n"
1799 "PMU4: DB %d Lane %d: (DISCONNECTED)\n"
1802 "PMU4: DB %d Lane %d: %3d %3d -> %3d\n"
1805 "PMU: Error: Dbyte %d lane %d txDqDly DM passing region is too small (width = %d)\n"
1808 "PMU3: Errcnt for MRD/MWD search nib %2d delay = (%d, 0x%02x) = %d\n"
1814 "PMU: Error: Dbyte %d nibble %d found mutliple working coarse delay setting for MRD/MWD\n"
1817 "PMU4: MRD Passing Regions (coarseVal, fineLeft fineRight -> fineCenter)\n"
1820 "PMU4: MWD Passing Regions (coarseVal, fineLeft fineRight -> fineCenter)\n"
1823 …"PMU10: Warning: DB %d nibble %d has multiple working coarse delays, %d and %d, choosing the small…
1826 "PMU: Error: Dbyte %d nibble %d MRD/MWD passing region is too small (width = %d)\n"
1829 "PMU4: DB %d nibble %d: %3d, %3d %3d -> %3d\n"
1832 "PMU1: Start MRD/nMWD %d for csn %d\n"
1835 "PMU2: RXDQS delayLeft[%2d] = %3d (DISCONNECTED)\n"
1838 "PMU2: RXDQS delayLeft[%2d] = %3d delayOop[%2d] = %3d OopScaled %4d, selectOop %d\n"
1841 "PMU2: RXDQS delayRight[%2d] = %3d (DISCONNECTED)\n"
1844 "PMU2: RXDQS delayRight[%2d] = %3d delayOop[%2d] = %4d OopScaled %4d, selectOop %d\n"
1847 "PMU4: RxClkDly Passing Regions (EyeLeft EyeRight -> EyeCenter)\n"
1850 "PMU4: DB %d nibble %d: (DISCONNECTED)\n"
1853 "PMU4: DB %d nibble %d: %3d %3d -> %3d\n"
1856 "PMU: Error: Dbyte %d nibble %d rxClkDly passing region is too small (width = %d)\n"
1859 "PMU0: goodbar = %d for RDWR_BLEN %d\n"
1862 "PMU3: RxClkDly = %d\n"
1865 "PMU0: db %d l %d absLane %d -> bottom %d top %d\n"
1868 "PMU3: BYTE %d - %3d %3d %3d %3d %3d %3d %3d %3d\n"
1871 "PMU: Error: dbyte %d lane %d's per-lane vrefDAC's had no passing region\n"
1874 "PMU0: db%d l%d - %d %d\n"
1877 "PMU0: goodbar = %d for RDWR_BLEN %d\n"
1880 "PMU3: db%d l%d saw %d issues at rxClkDly %d\n"
1883 "PMU3: db%d l%d first saw a pass->fail edge at rxClkDly %d\n"
1886 "PMU3: lane %d PBD = %d\n"
1889 "PMU3: db%d l%d first saw a DBI pass->fail edge at rxClkDly %d\n"
1892 "PMU2: db%d l%d already passed rxPBD = %d\n"
1895 "PMU0: db%d l%d, PBD = %d\n"
1898 "PMU: Error: dbyte %d lane %d failed read deskew\n"
1901 "PMU0: db%d l%d, inc PBD = %d\n"
1904 "PMU1: Running lane deskew on pstate %d csn %d rdDBIEn %d\n"
1910 "PMU1: AcsmCsMapCtrl%02d 0x%04x\n"
1913 "PMU1: AcsmCsMapCtrl%02d 0x%04x\n"
1934 "PMU10: PHY TOTALS - NUM_DBYTES %d NUM_NIBBLES %d NUM_ANIBS %d\n"
1937 …"PMU10: CSA=0x%02x, CSB=0x%02x, TSTAGES=0x%04x, HDTOUT=%d, MMISC=%d DRAMFreq=%dMT DramType=LPDDR3\…
1940 …"PMU10: CSA=0x%02x, CSB=0x%02x, TSTAGES=0x%04x, HDTOUT=%d, MMISC=%d DRAMFreq=%dMT DramType=LPDDR4\…
1943 …"PMU10: CS=0x%02x, TSTAGES=0x%04x, HDTOUT=%d, 2T=%d, MMISC=%d AddrMirror=%d DRAMFreq=%dMT DramType…
1946 "PMU10: Pstate%d MR0=0x%04x MR1=0x%04x MR2=0x%04x\n"
1949 …"PMU10: Pstate%d MRS MR0=0x%04x MR1=0x%04x MR2=0x%04x MR3=0x%04x MR4=0x%04x MR5=0x%04x MR6=0x%04x\…
1952 "PMU10: Pstate%d MRS MR1_A0=0x%04x MR2_A0=0x%04x MR3_A0=0x%04x MR11_A0=0x%04x\n"
1958 "PMU10: Pstate%d MRS MR01_A0=0x%02x MR02_A0=0x%02x MR03_A0=0x%02x MR11_A0=0x%02x\n"
1961 "PMU10: Pstate%d MRS MR12_A0=0x%02x MR13_A0=0x%02x MR14_A0=0x%02x MR22_A0=0x%02x\n"
1964 "PMU10: Pstate%d MRS MR01_A1=0x%02x MR02_A1=0x%02x MR03_A1=0x%02x MR11_A1=0x%02x\n"
1967 "PMU10: Pstate%d MRS MR12_A1=0x%02x MR13_A1=0x%02x MR14_A1=0x%02x MR22_A1=0x%02x\n"
1970 "PMU10: Pstate%d MRS MR01_B0=0x%02x MR02_B0=0x%02x MR03_B0=0x%02x MR11_B0=0x%02x\n"
1973 "PMU10: Pstate%d MRS MR12_B0=0x%02x MR13_B0=0x%02x MR14_B0=0x%02x MR22_B0=0x%02x\n"
1976 "PMU10: Pstate%d MRS MR01_B1=0x%02x MR02_B1=0x%02x MR03_B1=0x%02x MR11_B1=0x%02x\n"
1979 "PMU10: Pstate%d MRS MR12_B1=0x%02x MR13_B1=0x%02x MR14_B1=0x%02x MR22_B1=0x%02x\n"
1982 "PMU1: AcsmOdtCtrl%02d 0x%02x\n"
1985 "PMU1: AcsmCsMapCtrl%02d 0x%04x\n"
1988 "PMU1: AcsmCsMapCtrl%02d 0x%04x\n"
1994 "PMU3: DDR4 infinite preamble enter/exit mode %d\n"
1997 "PMU1: In rxenb_train() csn=%d pstate=%d\n"
2012 "PMU3: Preamble search pass=%d anyfail=%d\n"
2018 "PMU3: Found DQS pre-amble\n"
2021 "PMU: Error: Dbyte %d couldn't find the rising edge of DQS during RxEn Training\n"
2027 "PMU3: Decreasing RxEn delay by %d fine step to allow full capture of reads\n"
2030 "PMU3: MREP Delay = %d\n"
2033 "PMU3: Errcnt for MREP nib %2d delay = %2d is %d\n"
2036 "PMU3: MREP nibble %d sampled a 1 at data buffer delay %d\n"
2039 "PMU3: MREP nibble %d saw a 0 to 1 transition at data buffer delay %d\n"
2045 "PMU2: Rising edge found in alias window, setting rxDly for nibble %d = %d\n"
2048 "PMU: Error: Failed MREP for nib %d with %d one\n"
2051 "PMU2: Rising edge not found in alias window with %d one, leaving rxDly for nibble %d = %d\n"
2054 "PMU3: Training DIMM %d CSn %d\n"
2075 "PMU3: DEBUG enterCAtrain_lp4 3: Put dbyte %d in async mode\n"
2081 "PMU3: DEBUG enterCAtrain_lp4 7: idx = %d vref = %x mr12 = %x\n"
2087 "PMU3: Phase %d CAreadbackA db:%d %x xo:%x\n"
2090 "PMU3: DEBUG lp4SetCatrVref 1: cs=%d chan=%d mr12=%x vref=%d.%d%%\n"
2093 "PMU3: DEBUG lp4SetCatrVref 3: mr12 = %x send vref= %x to db=%d\n"
2099 "PMU4:mr12:%2x cs:%d chan %d r:%4x\n"
2102 "PMU3: i:%2d bstr:%2d bsto:%2d st:%d r:%d\n"
2105 "Failed to find sufficient CA Vref Passing Region for CS %d ch. %d\n"
2108 "PMU3:Found %d.%d%% MR12:%x for cs:%d chan %d\n"
2111 "PMU3:Calculated %d for AtxImpedence from acx %d.\n"
2117 "PMU3:Calculated %d.%d%% for Vref MR12=0x%x.\n"
2126 "PMU3: CAtrain_lp testing dly %d\n"
2132 "PMU5: CAA%d "
2139 "PMU5: CAB%d "
2146 "PMU3: anibi=%d, anibichan[anibi]=%d ,chan=%d\n"
2152 {0x01310002, "\nPMU3:ATxDly setting:%x margin:%d\n"
2154 {0x01320002, "\nPMU3:InvClk ATxDly setting:%x margin:%d\n"
2159 "PMU3: 2 anibi=%d, anibichan[anibi]=%d ,chan=%d"
2161 {0x01350002, "\nPMU3: no neg clock => CA setting anib=%d, :%d\n"
2164 "PMU3:Normal margin:%d\n"
2167 "PMU3:Inverted margin:%d\n"
2176 "PMU3: 3 anibi=%d, anibichan[anibi]=%d ,chan=%d\n"
2188 "PMU4:Using MR12 values from 1D CA VREF training.\n"
2200 "PMU10: Setting boot clock divider to %d\n"
2215 "PMU10: **** Executing 2D Image ****\n"
2233 "PMU10: **** Testchip %d Specific Firmware ****\n"
2281 "PMU2: Starting SI friendly 1d RdDqs training for all ranks\n"
2287 "PMU2: Starting 1d WrDq training for all ranks\n"
2296 "PMU2: Starting 1d RdDqs training for all ranks\n"
2299 "PMU2: Starting again 1d WrDq training for all ranks\n"
2305 "PMU2: Starting 2d WrDq training for all ranks\n"
2308 "PMU2: Starting 2d RdDqs training for all ranks\n"
2323 "PMU3: fixRxEnBackOff csn:%d db:%d dn:%d bo:%d dly:%x\n"
2335 "PMU3:Dbyte Detect: db%d received %x\n"
2338 "PMU3:getDqs2Dq read %x from dbyte %d\n"
2341 "PMU3:getDqs2Dq(2) read %x from dbyte %d\n"
2344 "PMU: Error: Dbyte %d read 0 from the DQS oscillator it is connected to\n"
2347 "PMU4: Dbyte %d dqs2dq = %d/32 UI\n"
2350 "PMU3:getDqs2Dq set dqs2dq:%d/32 ui (%d ps) from dbyte %d\n"
2353 "PMU3: Setting coarse delay in AtxDly chiplet %d from 0x%02x to 0x%02x\n"
2356 "PMU3: Clearing coarse delay in AtxDly chiplet %d from 0x%02x to 0x%02x\n"
2374 "PMU1: DDR4 update Rx DBI Setting disable %d\n"
2377 "PMU1: DDR4 update 2nCk WPre Setting disable %d\n"
2380 "PMU1: read_delay: db%d lane%d delays[%2d] = 0x%02x (max 0x%02x)\n"
2383 "PMU1: write_delay: db%d lane%d delays[%2d] = 0x%04x\n"
2386 "PMU5: ID=%d -- db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 --\n"
2389 "PMU5: [%d]:0x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x\n"
2392 "PMU2: dump delays - pstate=%d dimm=%d csn=%d\n"
2395 "PMU3: Printing Mid-Training Delay Information\n"
2398 "PMU5: CS%d <<KEY>> 0 TrainingCntr <<KEY>> coarse(15:10) fine(9:0)\n"
2401 "PMU5: CS%d <<KEY>> 0 RxEnDly, 1 RxClkDly <<KEY>> coarse(10:6) fine(5:0)\n"
2404 "PMU5: CS%d <<KEY>> 0 TxDqsDly, 1 TxDqDly <<KEY>> coarse(9:6) fine(5:0)\n"
2407 "PMU5: CS%d <<KEY>> 0 RxPBDly <<KEY>> 1 Delay Unit ~= 7ps\n"
2422 "PMU2: getMaxRxen(): maxDly %d maxTg %d maxNib %d\n"
2425 "PMU2: getRankMaxRxen(): maxDly %d Tg %d maxNib %d\n"
2428 "PMU1: skipping CDD calculation in 2D image\n"
2431 "PMU3: Calculating CDDs for pstate %d\n"
2434 "PMU3: rxFromDly[%d][%d] = %d\n"
2437 "PMU3: rxToDly [%d][%d] = %d\n"
2440 "PMU3: rxDly [%d][%d] = %d\n"
2443 "PMU3: txDly [%d][%d] = %d\n"
2446 "PMU3: allFine CDD_RR_%d_%d = %d\n"
2449 "PMU3: allFine CDD_WW_%d_%d = %d\n"
2452 "PMU3: CDD_RR_%d_%d = %d\n"
2455 "PMU3: CDD_WW_%d_%d = %d\n"
2458 "PMU3: allFine CDD_RW_%d_%d = %d\n"
2461 "PMU3: allFine CDD_WR_%d_%d = %d\n"
2464 "PMU3: CDD_RW_%d_%d = %d\n"
2467 "PMU3: CDD_WR_%d_%d = %d\n"
2470 "PMU3: F%dBC2x_B%d_D%d = 0x%02x\n"
2473 "PMU3: F%dBC3x_B%d_D%d = 0x%02x\n"
2476 "PMU3: F%dBC4x_B%d_D%d = 0x%02x\n"
2479 "PMU3: F%dBC5x_B%d_D%d = 0x%02x\n"
2482 "PMU3: F%dBC8x_B%d_D%d = 0x%02x\n"
2485 "PMU3: F%dBC9x_B%d_D%d = 0x%02x\n"
2488 "PMU3: F%dBCAx_B%d_D%d = 0x%02x\n"
2491 "PMU3: F%dBCBx_B%d_D%d = 0x%02x\n"
2497 "PMU10: context_switch_postamble is enabled for DIMM %d, RC0A=0x%x, RC3x=0x%x\n"
2518 "PMU1: enter_lp3: DEBUG: pstate = %d\n"
2521 "PMU1: enter_lp3: DEBUG: dfifreqxlat_pstate = %d\n"
2524 "PMU1: enter_lp3: DEBUG: pllbypass = %d\n"
2527 "PMU1: enter_lp3: DEBUG: forcecal = %d\n"
2542 "PMU3: Setting DataBuffer function space of dimmcs 0x%02x to %d\n"
2551 "PMU1: DDR4 update Rd Pre Setting disable %d\n"
2566 "PMU4: BCW value for dimm %d, fspace %d, addr 0x%04x\n"
2569 "PMU4: DB %d, value 0x%02x\n"
2572 "PMU6: WARNING MREP underflow, set to min value -2 coarse, 0 fine\n"
2575 … Writing final data buffer fine delay value nib %2d, trainDly %3d, fineDly code %2d, new MREP fine…
2578 …"PMU6: LRDIMM Writing final data buffer fine delay value nib %2d, trainDly %3d, fineDly code %2d\n"
2581 "PMU6: LRDIMM Writing data buffer fine delay type %d nib %2d, code %2d\n"
2584 "PMU6: Writing final data buffer coarse delay value dbyte %2d, coarse = 0x%02x\n"
2599 "PMU3: Update BC00, BC01, BC02 for rank-dimm 0x%02x\n"
2602 "PMU3: Writing D4 RDIMM RCD Control words F0RC00 -> F0RC0F\n"
2608 "PMU3: Writing D4 RDIMM RCD Control words F1RC00 -> F1RC05\n"
2611 "PMU3: Writing D4 RDIMM RCD Control words F1RC1x -> F1RC9x\n"
2614 "PMU3: Writing D4 Data buffer Control words BC00 -> BC0E\n"
2617 "PMU1: setAltCL Sending MR0 0x%x cl=%d\n"
2620 "PMU1: restoreFromAltCL Sending MR0 0x%x cl=%d\n"
2623 "PMU1: restoreAcsmFromAltCL Sending MR0 0x%x cl=%d\n"
2626 "PMU2: Setting D3R RC%d = 0x%01x\n"
2629 "PMU3: Writing D3 RDIMM RCD Control words RC0 -> RC11\n"
2632 "PMU0: VrefDAC0/1 vddqStart %d dacToVddq %d\n"
2641 "PMU0: PHY VREF @ (%d/1000) VDDQ\n"
2644 "PMU0: initalizing phy vrefDacs to %d ExtVrefRange %x\n"
2647 "PMU0: initalizing global vref to %d range %d\n"
2650 "PMU4: Setting initial device vrefDQ for CS%d to MR6 = 0x%04x\n"
2653 "PMU1: In write_level_fine() csn=%d dimm=%d pstate=%d\n"
2662 "PMU4: WL margin for nib %2d: %08x%08x%08x%08x%08x%08x\n"
2671 "PMU3: got %d for cl in load_wrlvl_acsm\n"
2674 "PMU1: In write_level_coarse() csn=%d dimm=%d pstate=%d\n"
2677 "PMU3: left eye edge search db:%d ln:%d dly:0x%x\n"
2680 "PMU3: right eye edge search db:%d ln:%d dly:0x%x\n"
2683 "PMU3: eye center db:%d ln:%d dly:0x%x (maxdq:%x)\n"
2686 "PMU3: Wrote to TxDqDly db:%d ln:%d dly:0x%x\n"
2689 "PMU3: Wrote to TxDqDly db:%d ln:%d dly:0x%x\n"
2692 "PMU3: Coarse write leveling dbyte%2d is still failing for TxDqsDly=0x%04x\n"
2695 "PMU4: Coarse write leveling iteration %d saw %d data miscompares across the entire phy\n"
2701 "PMU3: got %d for cl in load_wrlvl_acsm\n"
2704 "PMU3: In write_level_coarse() csn=%d dimm=%d pstate=%d\n"
2707 "PMU3: left eye edge search db:%d ln:%d dly:0x%x\n"
2710 "PMU3: right eye edge search db: %d ln: %d dly: 0x%x\n"
2713 "PMU3: eye center db: %d ln: %d dly: 0x%x (maxdq: 0x%x)\n"
2716 "PMU3: Wrote to TxDqDly db: %d ln: %d dly: 0x%x\n"
2719 "PMU3: Wrote to TxDqDly db: %d ln: %d dly: 0x%x\n"
2722 "PMU3: Coarse write leveling nibble%2d is still failing for TxDqsDly=0x%04x\n"
2725 "PMU4: Coarse write leveling iteration %d saw %d data miscompares across the entire phy\n"
2734 "PMU4: WL margin for nib %2d: %08x%08x%08x%08x%08x%08x%08x%08x\n"
2740 "PMU8: Adjust margin after WL coarse to be larger than %d\n"
2743 "PMU: Error: All margin after write leveling coarse are smaller than minMargin %d\n"
2746 "PMU8: Decrement nib %d TxDqsDly by %d fine step\n"
2749 "PMU3: In write_level_coarse() csn=%d dimm=%d pstate=%d\n"
2752 "PMU2: Write level: dbyte %d nib%d dq/dmbi %2d dqsfine 0x%04x dqDly 0x%04x\n"
2755 "PMU3: Coarse write leveling nibble%2d is still failing for TxDqsDly=0x%04x\n"
2758 "PMU4: Coarse write leveling iteration %d saw %d data miscompares across the entire phy\n"
2764 "PMU3: DWL delay = %d\n"
2767 "PMU3: Errcnt for DWL nib %2d delay = %2d is %d\n"
2770 "PMU3: DWL nibble %d sampled a 1 at delay %d\n"
2773 "PMU3: DWL nibble %d passed at delay %d. Rising edge was at %d\n"
2779 "PMU2: Rising edge found in alias window, setting wrlvlDly for nibble %d = %d\n"
2782 "PMU: Error: Failed DWL for nib %d with %d one\n"
2785 "PMU2: Rising edge not found in alias window with %d one, leaving wrlvlDly for nibble %d = %d\n"
2794 "PMU: ***** Assertion Error - terminating *****\n"
2797 "PMU1: swapByte db %d by %d\n"
2800 "PMU3: get_cmd_dly max(%d ps, %d memclk) = %d\n"
2806 "PMU0: hwt_init_ppgc_prbs(): Polynomial: %x, Deg: %d\n"
2809 "PMU: Error: acsm_set_cmd to non existent instruction address %d\n"
2830 "PMU: Error: setAcsmCLCWL: cl and cwl must be each >= 2 and 5, resp. CL=%d CWL=%d\n"
2833 "PMU: Error: setAcsmCLCWL: cl and cwl must be each >= 5. CL=%d CWL=%d\n"
2836 "PMU1: setAcsmCLCWL: CASL %04d WCASL %04d\n"
2851 "PMU: Error: Boot clock divider setting of %d is too small\n"
2857 "PMU3: Writing MR%d OP=%x\n"
2875 "PMU2: Use PDA mode to set MR%d with value 0x%02x\n"
2887 "PMU1: lock_pll_dll: DEBUG: pstate = %d\n"
2890 "PMU1: lock_pll_dll: DEBUG: dfifreqxlat_pstate = %d\n"
2893 "PMU1: lock_pll_dll: DEBUG: pllbypass = %d\n"
2896 "PMU3: SaveLcdlSeed: Saving seed %d\n"
2902 "PMU3: ACXConf:%d MaxNumDbytes:%d NumDfi:%d\n"
2905 "PMU1: setAltAcsmCLCWL setting cl=%d cwl=%d\n"