Lines Matching +full:0 +full:d
17 {0x00000001,
20 {0x00010000,
21 "PMU1: loading 2D acsm sequence\n"
23 {0x00020000,
24 "PMU1: loading 1D acsm sequence\n"
26 {0x00030002,
27 "PMU3: %d memclocks @ %d to get half of 300ns\n"
29 {0x00040000,
32 {0x00050000,
33 "PMU3: Running 1D search for left eye edge\n"
35 {0x00060001,
36 "PMU1: In Phase Left Edge Search cs %d\n"
38 {0x00070001,
39 "PMU1: Out of Phase Left Edge Search cs %d\n"
41 {0x00080000,
42 "PMU3: Running 1D search for right eye edge\n"
44 {0x00090001,
45 "PMU1: In Phase Right Edge Search cs %d\n"
47 {0x000a0001,
48 "PMU1: Out of Phase Right Edge Search cs %d\n"
50 {0x000b0001,
51 "PMU1: mxRdLat training pstate %d\n"
53 {0x000c0001,
54 "PMU1: mxRdLat search for cs %d\n"
56 {0x000d0001,
57 "PMU0: MaxRdLat non consistent DtsmLoThldXingInd 0x%03x\n"
59 {0x000e0003,
60 "PMU4: CS %d Dbyte %d worked with DFIMRL = %d DFICLKs\n"
62 {0x000f0004,
63 "PMU3: MaxRdLat Read Lane err mask for csn %d, DFIMRL %2d DFIClks, dbyte %d = 0x%03x\n"
65 {0x00100003,
66 "PMU3: MaxRdLat Read Lane err mask for csn %d DFIMRL %2d, All dbytes = 0x%03x\n"
68 {0x00110001,
69 …"PMU: Error: CS%d failed to find a DFIMRL setting that worked for all bytes during MaxRdLat traini…
71 {0x00120002,
72 "PMU3: Smallest passing DFIMRL for all dbytes in CS%d = %d DFIClks\n"
74 {0x00130000,
77 {0x00140003,
78 "PMU: Error: Dbyte %d lane %d txDqDly passing region is too small (width = %d)\n"
80 {0x00150006,
81 "PMU10: Adjusting rxclkdly db %d nib %d from %d+%d=%d->%d\n"
83 {0x00160000,
86 {0x00170005,
87 "PMU4: DB %d Lane %d: %3d %3d -> %3d\n"
89 {0x00180002,
90 "PMU2: TXDQ delayLeft[%2d] = %3d (DISCONNECTED)\n"
92 {0x00190004,
93 "PMU2: TXDQ delayLeft[%2d] = %3d oopScaled = %3d selectOop %d\n"
95 {0x001a0002,
96 "PMU2: TXDQ delayRight[%2d] = %3d (DISCONNECTED)\n"
98 {0x001b0004,
99 "PMU2: TXDQ delayRight[%2d] = %3d oopScaled = %3d selectOop %d\n"
101 {0x001c0003,
102 "PMU: Error: Dbyte %d lane %d txDqDly passing region is too small (width = %d)\n"
104 {0x001d0000,
107 {0x001e0002,
108 "PMU4: DB %d Lane %d: (DISCONNECTED)\n"
110 {0x001f0005,
111 "PMU4: DB %d Lane %d: %3d %3d -> %3d\n"
113 {0x00200002,
114 "PMU3: Running 1D search csn %d for DM Right/NotLeft(%d) eye edge\n"
116 {0x00210002,
117 "PMU3: WrDq DM byte%2d with Errcnt %d\n"
119 {0x00220002,
120 "PMU3: WrDq DM byte%2d avgDly 0x%04x\n"
122 {0x00230002,
123 "PMU1: WrDq DM byte%2d with Errcnt %d\n"
125 {0x00240001,
126 "PMU: Error: Dbyte %d txDqDly DM training did not start inside the eye\n"
128 {0x00250000,
131 {0x00260002,
132 "PMU4: DB %d Lane %d: (DISCONNECTED)\n"
134 {0x00270005,
135 "PMU4: DB %d Lane %d: %3d %3d -> %3d\n"
137 {0x00280003,
138 "PMU: Error: Dbyte %d lane %d txDqDly DM passing region is too small (width = %d)\n"
140 {0x00290004,
141 "PMU3: Errcnt for MRD/MWD search nib %2d delay = (%d, 0x%02x) = %d\n"
143 {0x002a0000,
146 {0x002b0002,
147 "PMU: Error: Dbyte %d nibble %d found mutliple working coarse delay setting for MRD/MWD\n"
149 {0x002c0000,
152 {0x002d0000,
155 {0x002e0004,
156 …"PMU10: Warning: DB %d nibble %d has multiple working coarse delays, %d and %d, choosing the small…
158 {0x002f0003,
159 "PMU: Error: Dbyte %d nibble %d MRD/MWD passing region is too small (width = %d)\n"
161 {0x00300006,
162 "PMU4: DB %d nibble %d: %3d, %3d %3d -> %3d\n"
164 {0x00310002,
165 "PMU1: Start MRD/nMWD %d for csn %d\n"
167 {0x00320002,
168 "PMU2: RXDQS delayLeft[%2d] = %3d (DISCONNECTED)\n"
170 {0x00330006,
171 "PMU2: RXDQS delayLeft[%2d] = %3d delayOop[%2d] = %3d OopScaled %4d, selectOop %d\n"
173 {0x00340002,
174 "PMU2: RXDQS delayRight[%2d] = %3d (DISCONNECTED)\n"
176 {0x00350006,
177 "PMU2: RXDQS delayRight[%2d] = %3d delayOop[%2d] = %4d OopScaled %4d, selectOop %d\n"
179 {0x00360000,
182 {0x00370002,
183 "PMU4: DB %d nibble %d: (DISCONNECTED)\n"
185 {0x00380005,
186 "PMU4: DB %d nibble %d: %3d %3d -> %3d\n"
188 {0x00390003,
189 "PMU: Error: Dbyte %d nibble %d rxClkDly passing region is too small (width = %d)\n"
191 {0x003a0002,
192 "PMU0: goodbar = %d for RDWR_BLEN %d\n"
194 {0x003b0001,
195 "PMU3: RxClkDly = %d\n"
197 {0x003c0005,
198 "PMU0: db %d l %d absLane %d -> bottom %d top %d\n"
200 {0x003d0009,
201 "PMU3: BYTE %d - %3d %3d %3d %3d %3d %3d %3d %3d\n"
203 {0x003e0002,
204 "PMU: Error: dbyte %d lane %d's per-lane vrefDAC's had no passing region\n"
206 {0x003f0004,
207 "PMU0: db%d l%d - %d %d\n"
209 {0x00400002,
210 "PMU0: goodbar = %d for RDWR_BLEN %d\n"
212 {0x00410004,
213 "PMU3: db%d l%d saw %d issues at rxClkDly %d\n"
215 {0x00420003,
216 "PMU3: db%d l%d first saw a pass->fail edge at rxClkDly %d\n"
218 {0x00430002,
219 "PMU3: lane %d PBD = %d\n"
221 {0x00440003,
222 "PMU3: db%d l%d first saw a DBI pass->fail edge at rxClkDly %d\n"
224 {0x00450003,
225 "PMU2: db%d l%d already passed rxPBD = %d\n"
227 {0x00460003,
228 "PMU0: db%d l%d, PBD = %d\n"
230 {0x00470002,
231 "PMU: Error: dbyte %d lane %d failed read deskew\n"
233 {0x00480003,
234 "PMU0: db%d l%d, inc PBD = %d\n"
236 {0x00490003,
237 "PMU1: Running lane deskew on pstate %d csn %d rdDBIEn %d\n"
239 {0x004a0000,
242 {0x004b0002,
243 "PMU1: AcsmCsMapCtrl%02d 0x%04x\n"
245 {0x004c0002,
246 "PMU1: AcsmCsMapCtrl%02d 0x%04x\n"
248 {0x004d0001,
249 …"PMU: Error: Wrong PMU image loaded. message Block DramType = 0x%02x, but image built for D3U Type…
251 {0x004e0001,
252 …"PMU: Error: Wrong PMU image loaded. message Block DramType = 0x%02x, but image built for D3R Type…
254 {0x004f0001,
255 …"PMU: Error: Wrong PMU image loaded. message Block DramType = 0x%02x, but image built for D4U Type…
257 {0x00500001,
258 …"PMU: Error: Wrong PMU image loaded. message Block DramType = 0x%02x, but image built for D4R Type…
260 {0x00510001,
261 …"PMU: Error: Wrong PMU image loaded. message Block DramType = 0x%02x, but image built for D4LR Typ…
263 {0x00520000,
266 {0x00530003,
267 "PMU10: PHY TOTALS - NUM_DBYTES %d NUM_NIBBLES %d NUM_ANIBS %d\n"
269 {0x00540006,
270 …"PMU10: CSA=0x%02x, CSB=0x%02x, TSTAGES=0x%04x, HDTOUT=%d, MMISC=%d DRAMFreq=%dMT DramType=LPDDR3\…
272 {0x00550006,
273 …"PMU10: CSA=0x%02x, CSB=0x%02x, TSTAGES=0x%04x, HDTOUT=%d, MMISC=%d DRAMFreq=%dMT DramType=LPDDR4\…
275 {0x00560008,
276 …"PMU10: CS=0x%02x, TSTAGES=0x%04x, HDTOUT=%d, 2T=%d, MMISC=%d AddrMirror=%d DRAMFreq=%dMT DramType…
278 {0x00570004,
279 "PMU10: Pstate%d MR0=0x%04x MR1=0x%04x MR2=0x%04x\n"
281 {0x00580008,
282 …"PMU10: Pstate%d MRS MR0=0x%04x MR1=0x%04x MR2=0x%04x MR3=0x%04x MR4=0x%04x MR5=0x%04x MR6=0x%04x\…
284 {0x00590005,
285 "PMU10: Pstate%d MRS MR1_A0=0x%04x MR2_A0=0x%04x MR3_A0=0x%04x MR11_A0=0x%04x\n"
287 {0x005a0000,
290 {0x005b0005,
291 "PMU10: Pstate%d MRS MR01_A0=0x%02x MR02_A0=0x%02x MR03_A0=0x%02x MR11_A0=0x%02x\n"
293 {0x005c0005,
294 "PMU10: Pstate%d MRS MR12_A0=0x%02x MR13_A0=0x%02x MR14_A0=0x%02x MR22_A0=0x%02x\n"
296 {0x005d0005,
297 "PMU10: Pstate%d MRS MR01_A1=0x%02x MR02_A1=0x%02x MR03_A1=0x%02x MR11_A1=0x%02x\n"
299 {0x005e0005,
300 "PMU10: Pstate%d MRS MR12_A1=0x%02x MR13_A1=0x%02x MR14_A1=0x%02x MR22_A1=0x%02x\n"
302 {0x005f0005,
303 "PMU10: Pstate%d MRS MR01_B0=0x%02x MR02_B0=0x%02x MR03_B0=0x%02x MR11_B0=0x%02x\n"
305 {0x00600005,
306 "PMU10: Pstate%d MRS MR12_B0=0x%02x MR13_B0=0x%02x MR14_B0=0x%02x MR22_B0=0x%02x\n"
308 {0x00610005,
309 "PMU10: Pstate%d MRS MR01_B1=0x%02x MR02_B1=0x%02x MR03_B1=0x%02x MR11_B1=0x%02x\n"
311 {0x00620005,
312 "PMU10: Pstate%d MRS MR12_B1=0x%02x MR13_B1=0x%02x MR14_B1=0x%02x MR22_B1=0x%02x\n"
314 {0x00630002,
315 "PMU1: AcsmOdtCtrl%02d 0x%02x\n"
317 {0x00640002,
318 "PMU1: AcsmCsMapCtrl%02d 0x%04x\n"
320 {0x00650002,
321 "PMU1: AcsmCsMapCtrl%02d 0x%04x\n"
323 {0x00660000,
326 {0x00670001,
327 "PMU3: DDR4 infinite preamble enter/exit mode %d\n"
329 {0x00680002,
330 "PMU1: In rxenb_train() csn=%d pstate=%d\n"
332 {0x00690000,
335 {0x006a0000,
338 {0x006b0009,
341 {0x006c0009,
344 {0x006d0002,
345 "PMU3: Preamble search pass=%d anyfail=%d\n"
347 {0x006e0000,
350 {0x006f0000,
353 {0x00700001,
354 "PMU: Error: Dbyte %d couldn't find the rising edge of DQS during RxEn Training\n"
356 {0x00710000,
359 {0x00720001,
360 "PMU3: Decreasing RxEn delay by %d fine step to allow full capture of reads\n"
362 {0x00730001,
363 "PMU3: MREP Delay = %d\n"
365 {0x00740003,
366 "PMU3: Errcnt for MREP nib %2d delay = %2d is %d\n"
368 {0x00750002,
369 "PMU3: MREP nibble %d sampled a 1 at data buffer delay %d\n"
371 {0x00760002,
372 "PMU3: MREP nibble %d saw a 0 to 1 transition at data buffer delay %d\n"
374 {0x00770000,
375 …"PMU2: MREP did not find a 0 to 1 transition for all nibbles. Failing nibbles assumed to have ris…
377 {0x00780002,
378 "PMU2: Rising edge found in alias window, setting rxDly for nibble %d = %d\n"
380 {0x00790002,
381 "PMU: Error: Failed MREP for nib %d with %d one\n"
383 {0x007a0003,
384 "PMU2: Rising edge not found in alias window with %d one, leaving rxDly for nibble %d = %d\n"
386 {0x007b0002,
387 "PMU3: Training DIMM %d CSn %d\n"
389 {0x007c0001,
390 "PMU3: exitCAtrain_lp3 cs 0x%x\n"
392 {0x007d0001,
393 "PMU3: enterCAtrain_lp3 cs 0x%x\n"
395 {0x007e0001,
396 "PMU3: CAtrain_switchmsb_lp3 cs 0x%x\n"
398 {0x007f0001,
401 {0x00800000,
404 {0x00810001,
405 "PMU3: DEBUG enterCAtrain_lp4 1: cs 0x%x\n"
407 {0x00820001,
408 "PMU3: DEBUG enterCAtrain_lp4 3: Put dbyte %d in async mode\n"
410 {0x00830000,
413 {0x00840003,
414 "PMU3: DEBUG enterCAtrain_lp4 7: idx = %d vref = %x mr12 = %x\n"
416 {0x00850001,
419 {0x00860004,
420 "PMU3: Phase %d CAreadbackA db:%d %x xo:%x\n"
422 {0x00870005,
423 "PMU3: DEBUG lp4SetCatrVref 1: cs=%d chan=%d mr12=%x vref=%d.%d%%\n"
425 {0x00880003,
426 "PMU3: DEBUG lp4SetCatrVref 3: mr12 = %x send vref= %x to db=%d\n"
428 {0x00890000,
431 {0x008a0004,
432 "PMU4:mr12:%2x cs:%d chan %d r:%4x\n"
434 {0x008b0005,
435 "PMU3: i:%2d bstr:%2d bsto:%2d st:%d r:%d\n"
437 {0x008c0002,
438 "Failed to find sufficient CA Vref Passing Region for CS %d ch. %d\n"
440 {0x008d0005,
441 "PMU3:Found %d.%d%% MR12:%x for cs:%d chan %d\n"
443 {0x008e0002,
444 "PMU3:Calculated %d for AtxImpedence from acx %d.\n"
446 {0x008f0000,
447 "PMU3:CA Odt impedence ==0. Use default vref.\n"
449 {0x00900003,
450 "PMU3:Calculated %d.%d%% for Vref MR12=0x%x.\n"
452 {0x00910000,
455 {0x00920000,
458 {0x00930001,
459 "PMU3: CAtrain_lp testing dly %d\n"
461 {0x00940001,
464 {0x00950001,
465 "PMU5: CAA%d "
467 {0x00960001, "%02x"
469 {0x00970000, "\n"
471 {0x00980001,
472 "PMU5: CAB%d "
474 {0x00990001, "%02x"
476 {0x009a0000, "\n"
478 {0x009b0003,
479 "PMU3: anibi=%d, anibichan[anibi]=%d ,chan=%d\n"
481 {0x009c0001, "%02x"
483 {0x009d0001, "\nPMU3:Raw CA setting :%x"
485 {0x009e0002, "\nPMU3:ATxDly setting:%x margin:%d\n"
487 {0x009f0002, "\nPMU3:InvClk ATxDly setting:%x margin:%d\n"
489 {0x00a00000, "\nPMU3:No Range found!\n"
491 {0x00a10003,
492 "PMU3: 2 anibi=%d, anibichan[anibi]=%d ,chan=%d"
494 {0x00a20002, "\nPMU3: no neg clock => CA setting anib=%d, :%d\n"
496 {0x00a30001,
497 "PMU3:Normal margin:%d\n"
499 {0x00a40001,
500 "PMU3:Inverted margin:%d\n"
502 {0x00a50000,
505 {0x00a60000,
508 {0x00a70003,
509 "PMU3: 3 anibi=%d, anibichan[anibi]=%d ,chan=%d\n"
511 {0x00a80002,
514 {0x00a90000,
517 {0x00aa0000,
520 {0x00ab0000,
521 "PMU4:Using MR12 values from 1D CA VREF training.\n"
523 {0x00ac0000,
526 {0x00ad0000,
529 {0x00ae0000,
532 {0x00af0001,
533 "PMU10: Setting boot clock divider to %d\n"
535 {0x00b00000,
538 {0x00b10000,
541 {0x00b20000,
544 {0x00b30000,
547 {0x00b40000,
548 "PMU10: **** Executing 2D Image ****\n"
550 {0x00b50001,
551 "PMU10: **** Start DDR4 Training. PMU Firmware Revision 0x%04x ****\n"
553 {0x00b60001,
554 "PMU10: **** Start DDR3 Training. PMU Firmware Revision 0x%04x ****\n"
556 {0x00b70001,
557 "PMU10: **** Start LPDDR3 Training. PMU Firmware Revision 0x%04x ****\n"
559 {0x00b80001,
560 "PMU10: **** Start LPDDR4 Training. PMU Firmware Revision 0x%04x ****\n"
562 {0x00b90000,
565 {0x00ba0001,
566 "PMU10: **** Testchip %d Specific Firmware ****\n"
568 {0x00bb0000,
571 {0x00bc0000,
574 {0x00bd0000,
577 {0x00be0000,
580 {0x00bf0000,
583 {0x00c00000,
586 {0x00c10000,
589 {0x00c20000,
592 {0x00c30000,
595 {0x00c40000,
598 {0x00c50000,
601 {0x00c60000,
604 {0x00c70000,
607 {0x00c80000,
610 {0x00c90000,
613 {0x00ca0000,
614 "PMU2: Starting SI friendly 1d RdDqs training for all ranks\n"
616 {0x00cb0000,
619 {0x00cc0000,
620 "PMU2: Starting 1d WrDq training for all ranks\n"
622 {0x00cd0000,
625 {0x00ce0000,
628 {0x00cf0000,
629 "PMU2: Starting 1d RdDqs training for all ranks\n"
631 {0x00d00000,
632 "PMU2: Starting again 1d WrDq training for all ranks\n"
634 {0x00d10000,
637 {0x00d20000,
638 "PMU2: Starting 2d WrDq training for all ranks\n"
640 {0x00d30000,
641 "PMU2: Starting 2d RdDqs training for all ranks\n"
643 {0x00d40002,
646 {0x00d50001,
647 "PMU: Error: Invalid PhyDrvImpedance of 0x%x specified in message block.\n"
649 {0x00d60001,
650 "PMU: Error: Invalid PhyOdtImpedance of 0x%x specified in message block.\n"
652 {0x00d70001,
653 "PMU: Error: Invalid BPZNResVal of 0x%x specified in message block.\n"
655 {0x00d80005,
656 "PMU3: fixRxEnBackOff csn:%d db:%d dn:%d bo:%d dly:%x\n"
658 {0x00d90001,
661 {0x00da0000,
664 {0x00db0000,
667 {0x00dc0002,
668 "PMU3:Dbyte Detect: db%d received %x\n"
670 {0x00dd0002,
671 "PMU3:getDqs2Dq read %x from dbyte %d\n"
673 {0x00de0002,
674 "PMU3:getDqs2Dq(2) read %x from dbyte %d\n"
676 {0x00df0001,
677 "PMU: Error: Dbyte %d read 0 from the DQS oscillator it is connected to\n"
679 {0x00e00002,
680 "PMU4: Dbyte %d dqs2dq = %d/32 UI\n"
682 {0x00e10003,
683 "PMU3:getDqs2Dq set dqs2dq:%d/32 ui (%d ps) from dbyte %d\n"
685 {0x00e20003,
686 "PMU3: Setting coarse delay in AtxDly chiplet %d from 0x%02x to 0x%02x\n"
688 {0x00e30003,
689 "PMU3: Clearing coarse delay in AtxDly chiplet %d from 0x%02x to 0x%02x\n"
691 {0x00e40000,
694 {0x00e50000,
697 {0x00e60000,
700 {0x00e70000,
703 {0x00e80000,
706 {0x00e90001,
707 "PMU1: DDR4 update Rx DBI Setting disable %d\n"
709 {0x00ea0001,
710 "PMU1: DDR4 update 2nCk WPre Setting disable %d\n"
712 {0x00eb0005,
713 "PMU1: read_delay: db%d lane%d delays[%2d] = 0x%02x (max 0x%02x)\n"
715 {0x00ec0004,
716 "PMU1: write_delay: db%d lane%d delays[%2d] = 0x%04x\n"
718 {0x00ed0001,
719 "PMU5: ID=%d -- db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 --\n"
721 {0x00ee000b,
722 "PMU5: [%d]:0x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x\n"
724 {0x00ef0003,
725 "PMU2: dump delays - pstate=%d dimm=%d csn=%d\n"
727 {0x00f00000,
730 {0x00f10001,
731 "PMU5: CS%d <<KEY>> 0 TrainingCntr <<KEY>> coarse(15:10) fine(9:0)\n"
733 {0x00f20001,
734 "PMU5: CS%d <<KEY>> 0 RxEnDly, 1 RxClkDly <<KEY>> coarse(10:6) fine(5:0)\n"
736 {0x00f30001,
737 "PMU5: CS%d <<KEY>> 0 TxDqsDly, 1 TxDqDly <<KEY>> coarse(9:6) fine(5:0)\n"
739 {0x00f40001,
740 "PMU5: CS%d <<KEY>> 0 RxPBDly <<KEY>> 1 Delay Unit ~= 7ps\n"
742 {0x00f50000,
743 "PMU5: all CS <<KEY>> 0 DFIMRL <<KEY>> Units = DFI clocks\n"
745 {0x00f60000,
746 "PMU5: all CS <<KEY>> VrefDACs <<KEY>> DAC(6:0)\n"
748 {0x00f70000,
751 {0x00f80000,
754 {0x00f90003,
755 "PMU2: getMaxRxen(): maxDly %d maxTg %d maxNib %d\n"
757 {0x00fa0003,
758 "PMU2: getRankMaxRxen(): maxDly %d Tg %d maxNib %d\n"
760 {0x00fb0000,
761 "PMU1: skipping CDD calculation in 2D image\n"
763 {0x00fc0001,
764 "PMU3: Calculating CDDs for pstate %d\n"
766 {0x00fd0003,
767 "PMU3: rxFromDly[%d][%d] = %d\n"
769 {0x00fe0003,
770 "PMU3: rxToDly [%d][%d] = %d\n"
772 {0x00ff0003,
773 "PMU3: rxDly [%d][%d] = %d\n"
775 {0x01000003,
776 "PMU3: txDly [%d][%d] = %d\n"
778 {0x01010003,
779 "PMU3: allFine CDD_RR_%d_%d = %d\n"
781 {0x01020003,
782 "PMU3: allFine CDD_WW_%d_%d = %d\n"
784 {0x01030003,
785 "PMU3: CDD_RR_%d_%d = %d\n"
787 {0x01040003,
788 "PMU3: CDD_WW_%d_%d = %d\n"
790 {0x01050003,
791 "PMU3: allFine CDD_RW_%d_%d = %d\n"
793 {0x01060003,
794 "PMU3: allFine CDD_WR_%d_%d = %d\n"
796 {0x01070003,
797 "PMU3: CDD_RW_%d_%d = %d\n"
799 {0x01080003,
800 "PMU3: CDD_WR_%d_%d = %d\n"
802 {0x01090004,
803 "PMU3: F%dBC2x_B%d_D%d = 0x%02x\n"
805 {0x010a0004,
806 "PMU3: F%dBC3x_B%d_D%d = 0x%02x\n"
808 {0x010b0004,
809 "PMU3: F%dBC4x_B%d_D%d = 0x%02x\n"
811 {0x010c0004,
812 "PMU3: F%dBC5x_B%d_D%d = 0x%02x\n"
814 {0x010d0004,
815 "PMU3: F%dBC8x_B%d_D%d = 0x%02x\n"
817 {0x010e0004,
818 "PMU3: F%dBC9x_B%d_D%d = 0x%02x\n"
820 {0x010f0004,
821 "PMU3: F%dBCAx_B%d_D%d = 0x%02x\n"
823 {0x01100004,
824 "PMU3: F%dBCBx_B%d_D%d = 0x%02x\n"
826 {0x01110000,
829 {0x01120003,
830 "PMU10: context_switch_postamble is enabled for DIMM %d, RC0A=0x%x, RC3x=0x%x\n"
832 {0x01130000,
833 "PMU10: Setting bcw fspace 0\n"
835 {0x01140001,
836 "PMU10: Sending BC0A = 0x%x\n"
838 {0x01150001,
839 "PMU10: Sending BC6x = 0x%x\n"
841 {0x01160001,
842 "PMU10: Sending RC0A = 0x%x\n"
844 {0x01170001,
845 "PMU10: Sending RC3x = 0x%x\n"
847 {0x01180001,
848 "PMU10: Sending RC0A = 0x%x\n"
850 {0x01190001,
851 "PMU1: enter_lp3: DEBUG: pstate = %d\n"
853 {0x011a0001,
854 "PMU1: enter_lp3: DEBUG: dfifreqxlat_pstate = %d\n"
856 {0x011b0001,
857 "PMU1: enter_lp3: DEBUG: pllbypass = %d\n"
859 {0x011c0001,
860 "PMU1: enter_lp3: DEBUG: forcecal = %d\n"
862 {0x011d0001,
863 "PMU1: enter_lp3: DEBUG: pllmaxrange = 0x%x\n"
865 {0x011e0001,
866 "PMU1: enter_lp3: DEBUG: dacval_out = 0x%x\n"
868 {0x011f0001,
869 "PMU1: enter_lp3: DEBUG: pllctrl3 = 0x%x\n"
871 {0x01200000,
874 {0x01210002,
875 "PMU3: Setting DataBuffer function space of dimmcs 0x%02x to %d\n"
877 {0x01220002,
878 "PMU4: Setting RCW FxRC%Xx = 0x%02x\n"
880 {0x01230002,
881 "PMU4: Setting RCW FxRC%02x = 0x%02x\n"
883 {0x01240001,
884 "PMU1: DDR4 update Rd Pre Setting disable %d\n"
886 {0x01250002,
887 "PMU2: Setting BCW FxBC%Xx = 0x%02x\n"
889 {0x01260002,
890 "PMU2: Setting BCW BC%02x = 0x%02x\n"
892 {0x01270002,
893 "PMU2: Setting BCW PBA mode FxBC%Xx = 0x%02x\n"
895 {0x01280002,
896 "PMU2: Setting BCW PBA mode BC%02x = 0x%02x\n"
898 {0x01290003,
899 "PMU4: BCW value for dimm %d, fspace %d, addr 0x%04x\n"
901 {0x012a0002,
902 "PMU4: DB %d, value 0x%02x\n"
904 {0x012b0000,
905 "PMU6: WARNING MREP underflow, set to min value -2 coarse, 0 fine\n"
907 {0x012c0004,
908 … Writing final data buffer fine delay value nib %2d, trainDly %3d, fineDly code %2d, new MREP fine…
910 {0x012d0003,
911 …"PMU6: LRDIMM Writing final data buffer fine delay value nib %2d, trainDly %3d, fineDly code %2d\n"
913 {0x012e0003,
914 "PMU6: LRDIMM Writing data buffer fine delay type %d nib %2d, code %2d\n"
916 {0x012f0002,
917 "PMU6: Writing final data buffer coarse delay value dbyte %2d, coarse = 0x%02x\n"
919 {0x01300003,
920 "PMU4: data 0x%04x at MB addr 0x%08x saved at CSR addr 0x%08x\n"
922 {0x01310003,
923 "PMU4: data 0x%04x at MB addr 0x%08x restored from CSR addr 0x%08x\n"
925 {0x01320003,
926 "PMU4: data 0x%04x at MB addr 0x%08x saved at CSR addr 0x%08x\n"
928 {0x01330003,
929 "PMU4: data 0x%04x at MB addr 0x%08x restored from CSR addr 0x%08x\n"
931 {0x01340001,
932 "PMU3: Update BC00, BC01, BC02 for rank-dimm 0x%02x\n"
934 {0x01350000,
937 {0x01360000,
940 {0x01370000,
943 {0x01380000,
946 {0x01390000,
949 {0x013a0002,
950 "PMU1: setAltCL Sending MR0 0x%x cl=%d\n"
952 {0x013b0002,
953 "PMU1: restoreFromAltCL Sending MR0 0x%x cl=%d\n"
955 {0x013c0002,
956 "PMU1: restoreAcsmFromAltCL Sending MR0 0x%x cl=%d\n"
958 {0x013d0002,
959 "PMU2: Setting D3R RC%d = 0x%01x\n"
961 {0x013e0000,
964 {0x013f0002,
965 "PMU0: VrefDAC0/1 vddqStart %d dacToVddq %d\n"
967 {0x01400001,
968 …"PMU: Error: Messageblock phyVref=0x%x is above the limit for TSMC28's attenuated LPDDR4 receivers…
970 {0x01410001,
971 …"PMU: Error: Messageblock phyVref=0x%x is above the limit for TSMC28's attenuated DDR4 receivers. …
973 {0x01420001,
974 "PMU0: PHY VREF @ (%d/1000) VDDQ\n"
976 {0x01430002,
977 "PMU0: initalizing phy vrefDacs to %d ExtVrefRange %x\n"
979 {0x01440002,
980 "PMU0: initalizing global vref to %d range %d\n"
982 {0x01450002,
983 "PMU4: Setting initial device vrefDQ for CS%d to MR6 = 0x%04x\n"
985 {0x01460003,
986 "PMU1: In write_level_fine() csn=%d dimm=%d pstate=%d\n"
988 {0x01470000,
991 {0x01480000,
994 {0x01490007,
995 "PMU4: WL margin for nib %2d: %08x%08x%08x%08x%08x%08x\n"
997 {0x014a0000,
1000 {0x014b0000,
1003 {0x014c0001,
1004 "PMU3: got %d for cl in load_wrlvl_acsm\n"
1006 {0x014d0003,
1007 "PMU1: In write_level_coarse() csn=%d dimm=%d pstate=%d\n"
1009 {0x014e0003,
1010 "PMU3: left eye edge search db:%d ln:%d dly:0x%x\n"
1012 {0x014f0003,
1013 "PMU3: right eye edge search db:%d ln:%d dly:0x%x\n"
1015 {0x01500004,
1016 "PMU3: eye center db:%d ln:%d dly:0x%x (maxdq:%x)\n"
1018 {0x01510003,
1019 "PMU3: Wrote to TxDqDly db:%d ln:%d dly:0x%x\n"
1021 {0x01520003,
1022 "PMU3: Wrote to TxDqDly db:%d ln:%d dly:0x%x\n"
1024 {0x01530002,
1025 "PMU3: Coarse write leveling dbyte%2d is still failing for TxDqsDly=0x%04x\n"
1027 {0x01540002,
1028 "PMU4: Coarse write leveling iteration %d saw %d data miscompares across the entire phy\n"
1030 {0x01550000,
1033 {0x01560001,
1034 "PMU3: got %d for cl in load_wrlvl_acsm\n"
1036 {0x01570003,
1037 "PMU3: In write_level_coarse() csn=%d dimm=%d pstate=%d\n"
1039 {0x01580003,
1040 "PMU3: left eye edge search db:%d ln:%d dly:0x%x\n"
1042 {0x01590003,
1043 "PMU3: right eye edge search db: %d ln: %d dly: 0x%x\n"
1045 {0x015a0004,
1046 "PMU3: eye center db: %d ln: %d dly: 0x%x (maxdq: 0x%x)\n"
1048 {0x015b0003,
1049 "PMU3: Wrote to TxDqDly db: %d ln: %d dly: 0x%x\n"
1051 {0x015c0003,
1052 "PMU3: Wrote to TxDqDly db: %d ln: %d dly: 0x%x\n"
1054 {0x015d0002,
1055 "PMU3: Coarse write leveling nibble%2d is still failing for TxDqsDly=0x%04x\n"
1057 {0x015e0002,
1058 "PMU4: Coarse write leveling iteration %d saw %d data miscompares across the entire phy\n"
1060 {0x015f0000,
1063 {0x01600000,
1066 {0x01610009,
1067 "PMU4: WL margin for nib %2d: %08x%08x%08x%08x%08x%08x%08x%08x\n"
1069 {0x01620000,
1072 {0x01630001,
1073 "PMU8: Adjust margin after WL coarse to be larger than %d\n"
1075 {0x01640001,
1076 "PMU: Error: All margin after write leveling coarse are smaller than minMargin %d\n"
1078 {0x01650002,
1079 "PMU8: Decrement nib %d TxDqsDly by %d fine step\n"
1081 {0x01660003,
1082 "PMU3: In write_level_coarse() csn=%d dimm=%d pstate=%d\n"
1084 {0x01670005,
1085 "PMU2: Write level: dbyte %d nib%d dq/dmbi %2d dqsfine 0x%04x dqDly 0x%04x\n"
1087 {0x01680002,
1088 "PMU3: Coarse write leveling nibble%2d is still failing for TxDqsDly=0x%04x\n"
1090 {0x01690002,
1091 "PMU4: Coarse write leveling iteration %d saw %d data miscompares across the entire phy\n"
1093 {0x016a0000,
1096 {0x016b0001,
1097 "PMU3: DWL delay = %d\n"
1099 {0x016c0003,
1100 "PMU3: Errcnt for DWL nib %2d delay = %2d is %d\n"
1102 {0x016d0002,
1103 "PMU3: DWL nibble %d sampled a 1 at delay %d\n"
1105 {0x016e0003,
1106 "PMU3: DWL nibble %d passed at delay %d. Rising edge was at %d\n"
1108 {0x016f0000,
1111 {0x01700002,
1112 "PMU2: Rising edge found in alias window, setting wrlvlDly for nibble %d = %d\n"
1114 {0x01710002,
1115 "PMU: Error: Failed DWL for nib %d with %d one\n"
1117 {0x01720003,
1118 "PMU2: Rising edge not found in alias window with %d one, leaving wrlvlDly for nibble %d = %d\n"
1120 {0x04000000,
1123 {0x04010000,
1126 {0x04020000,
1129 {0x04030002,
1130 "PMU1: swapByte db %d by %d\n"
1132 {0x04040003,
1133 "PMU3: get_cmd_dly max(%d ps, %d memclk) = %d\n"
1135 {0x04050002,
1136 "PMU0: Write CSR 0x%06x 0x%04x\n"
1138 {0x04060002,
1139 "PMU0: hwt_init_ppgc_prbs(): Polynomial: %x, Deg: %d\n"
1141 {0x04070001,
1142 "PMU: Error: acsm_set_cmd to non existent instruction address %d\n"
1144 {0x04080001,
1145 "PMU: Error: acsm_set_cmd with unknown ddr cmd 0x%x\n"
1147 {0x0409000c,
1150 {0x040a0000,
1153 {0x040b0000,
1156 {0x040c0000,
1159 {0x040d0002,
1162 {0x040e0002,
1163 "PMU: Error: setAcsmCLCWL: cl and cwl must be each >= 2 and 5, resp. CL=%d CWL=%d\n"
1165 {0x040f0002,
1166 "PMU: Error: setAcsmCLCWL: cl and cwl must be each >= 5. CL=%d CWL=%d\n"
1168 {0x04100002,
1169 "PMU1: setAcsmCLCWL: CASL %04d WCASL %04d\n"
1171 {0x04110001,
1172 "PMU: Error: Reserved value of register F0RC0F found in message block: 0x%04x\n"
1174 {0x04120001,
1175 "PMU3: Written MRS to CS=0x%02x\n"
1177 {0x04130001,
1178 "PMU3: Written MRS to CS=0x%02x\n"
1180 {0x04140000,
1183 {0x04150001,
1184 "PMU: Error: Boot clock divider setting of %d is too small\n"
1186 {0x04160000,
1189 {0x04170002,
1190 "PMU3: Writing MR%d OP=%x\n"
1192 {0x04180000,
1195 {0x04190001,
1196 "PMU3: Written MRS to CS=0x%02x\n"
1198 {0x041a0000,
1201 {0x041b0000,
1204 {0x041c0000,
1207 {0x041d0002,
1208 "PMU2: Use PDA mode to set MR%d with value 0x%02x\n"
1210 {0x041e0001,
1211 "PMU3: Written Vref with PDA to CS=0x%02x\n"
1213 {0x041f0000,
1216 {0x04200000,
1217 "PMU1: start_cal: DEBUG: setting CalRun to 0\n"
1219 {0x04210001,
1220 "PMU1: lock_pll_dll: DEBUG: pstate = %d\n"
1222 {0x04220001,
1223 "PMU1: lock_pll_dll: DEBUG: dfifreqxlat_pstate = %d\n"
1225 {0x04230001,
1226 "PMU1: lock_pll_dll: DEBUG: pllbypass = %d\n"
1228 {0x04240001,
1229 "PMU3: SaveLcdlSeed: Saving seed %d\n"
1231 {0x04250000,
1234 {0x04260003,
1235 "PMU3: ACXConf:%d MaxNumDbytes:%d NumDfi:%d\n"
1237 {0x04270005,
1238 "PMU1: setAltAcsmCLCWL setting cl=%d cwl=%d\n"
1243 {0x00000001,
1244 "PMU0: Converting %d into an MR\n"
1246 {0x00010003,
1247 "PMU DEBUG: vref_idx %d -= %d, range_idx = %d\n"
1249 {0x00020002,
1250 "PMU0: vrefIdx. Passing range %d, remaining vrefidx = %d\n"
1252 {0x00030002,
1253 "PMU0: VrefIdx %d -> MR[6:0] 0x%02x\n"
1255 {0x00040001,
1256 "PMU0: Converting MR 0x%04x to vrefIdx\n"
1258 {0x00050002,
1259 "PMU0: DAC %d Range %d\n"
1261 {0x00060003,
1262 "PMU0: Range %d, Range_idx %d, vref_idx offset %d\n"
1264 {0x00070002,
1265 "PMU0: MR 0x%04x -> VrefIdx %d\n"
1267 {0x00080001,
1268 "PMU: Error: Illegal timing group number ,%d, in getPtrVrefDq\n"
1270 {0x00090003,
1271 "PMU1: VrefDqR%dNib%d = %d\n"
1273 {0x000a0003,
1274 "PMU0: VrefDqR%dNib%d = %d\n"
1276 {0x000b0000,
1279 {0x000c0002,
1280 "PMU0: R%d_RxClkDly_Margin = %d\n"
1282 {0x000d0002,
1283 "PMU0: R%d_VrefDac_Margin = %d\n"
1285 {0x000e0002,
1286 "PMU0: R%d_TxDqDly_Margin = %d\n"
1288 {0x000f0002,
1289 "PMU0: R%d_DeviceVref_Margin = %d\n"
1291 {0x00100000,
1294 {0x00110003,
1295 "PMU0: eye %d's for all TG's is [%d ... %d]\n"
1297 {0x00120000,
1300 {0x00130002,
1301 "PMU0: Weight %d @ Setting %d\n"
1303 {0x0014001f,
1304 …"PMU4: %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d >%3d< %3d %3d %3d %3d %3d %3d %…
1306 {0x00150002,
1307 "PMU3: Voltage Range = [%d, %d]\n"
1309 {0x00160004,
1310 "PMU4: -- DB%d L%d -- centers: delay = %d, voltage = %d\n"
1312 {0x00170001,
1313 "PMU5: <<KEY>> 0 TxDqDlyTg%d <<KEY>> coarse(6:6) fine(5:0)\n"
1315 {0x00180001,
1316 "PMU5: <<KEY>> 0 messageBlock VrefDqR%d <<KEY>> MR6(6:0)\n"
1318 {0x00190001,
1319 "PMU5: <<KEY>> 0 RxClkDlyTg%d <<KEY>> fine(5:0)\n"
1321 {0x001a0003,
1322 "PMU0: tgToCsn: tg %d + 0x%04x -> csn %d\n"
1324 {0x001b0002,
1325 "PMU: Error: LP4 rank %d cannot be mapped on tg %d\n"
1327 {0x001c0002,
1328 "PMU3: Sending vref %d, Mr = 0X%05x, to all devices\n"
1330 {0x001d0004,
1331 "PMU4: -------- %dD Write Scanning TG %d (CS 0x%x) Lanes 0x%03x --------\n"
1333 {0x001e0002,
1334 "PMU0: training lanes 0x%03x using lanes 0x%03x\n"
1336 {0x001f0003,
1337 "PMU4: ------- 2D-DFE Read Scanning TG %d (CS 0x%x) Lanes 0x%03x -------\n"
1339 {0x00200004,
1340 "PMU4: ------- %dD Read Scanning TG %d (CS 0x%x) Lanes 0x%03x -------\n"
1342 {0x00210003,
1343 "PMU4: TG%d MR1[13,6,5]=0x%x MR6[13,9,8]=0x%x\n"
1345 {0x00220002,
1346 "PMU0: training lanes 0x%03x using lanes 0x%03x\n"
1348 {0x00230003,
1349 "PMU4: ------- 2D-DFE Read Scanning TG %d (CS 0x%x) Lanes 0x%03x -------\n"
1351 {0x00240004,
1352 "PMU4: ------- %dD Read Scanning TG %d (CS 0x%x) Lanes 0x%03x -------\n"
1354 {0x00250002,
1355 "PMU0: training lanes 0x%03x using lanes 0x%03x\n"
1357 {0x00260002,
1358 "PMU3: Sending vref %d, Mr = 0X%05x, to all devices\n"
1360 {0x00270004,
1361 "PMU4: -------- %dD Write Scanning TG %d (CS 0x%x) Lanes 0x%03x --------\n"
1363 {0x00280001,
1364 "PMU0: input %d\n"
1366 {0x00290002,
1367 "PMU4: Programmed Voltage Search Range [%d, %d]\n"
1369 {0x002a0002,
1370 "PMU3: Delay Stepsize = %d Fine, Voltage Stepsize = %d DAC\n"
1372 {0x002b0002,
1373 "PMU4: Delay Weight = %d, Voltage Weight = %d\n"
1375 {0x002c0003,
1376 "PMU0: raw 0x%x allFine %d incDec %d"
1378 {0x002d0008,
1379 "PMU0: db%d l%d, voltage 0x%x (u_r %d) delay 0x%x (u_r %d) - lcdl %d mask 0x%x\n"
1381 {0x002e0005,
1382 "PMU0: DB%d L%d, Eye %d, Seed = (0x%x, 0x%x)\n"
1384 {0x002f0002,
1385 "PMU3: 2D Enables : %d, 1, %d\n"
1387 {0x00300006,
1388 "PMU3: 2D Delay Ranges: OOPL[0x%04x,0x%04x], IP[0x%04x,0x%04x], OOPR[0x%04x,0x%04x]\n"
1390 {0x00310002,
1391 "PMU3: 2D Voltage Search Range : [%d, %d]\n"
1393 {0x00320002,
1394 "PMU4: Found Voltage Search Range [%d, %d]\n"
1396 {0x00330002,
1397 "PMU0: User Weight = %d, Voltage Weight = %d\n"
1399 {0x00340005,
1400 "PMU0: D(%d,%d) V(%d,%d | %d)\n"
1402 {0x00350002,
1403 "PMU0: Norm Weight = %d, Voltage Weight = %d\n"
1405 {0x00360002,
1406 "PMU0: seed 0 = (%d,%d) (center)\n"
1408 {0x00370003,
1409 "PMU0: seed 1 = (%d,%d).min edge at idx %d\n"
1411 {0x00380003,
1412 "PMU0: seed 2 = (%d,%d) max edge at idx %d\n"
1414 {0x00390003,
1415 "PMU0: Search point %d = (%d,%d)\n"
1417 {0x003a0005,
1418 "PMU0: YMARGIN: ^ %d, - %d, v %d. rate %d = %d\n"
1420 {0x003b0003,
1421 "PMU0: XMARGIN: center %d, edge %d. = %d\n"
1423 {0x003c0002,
1424 "PMU0: ----------- weighting (%d,%d) ----------------\n"
1426 {0x003d0003,
1427 "PMU0: X margin - L %d R %d - Min %d\n"
1429 {0x003e0003,
1430 "PMU0: Y margin - L %d R %d - Min %d\n"
1432 {0x003f0003,
1433 "PMU0: center (%d,%d) weight = %d\n"
1435 {0x00400003,
1436 "PMU4: Eye argest blob area %d from %d to %d\n"
1438 {0x00410002,
1439 "PMU0: Compute centroid min_x %d max_x %d\n"
1441 {0x00420003,
1442 "PMU0: Compute centroid sumLnDlyWidth %d sumLnVrefWidth %d sumLnWidht %d\n"
1444 {0x00430000,
1447 {0x00440003,
1448 "PMU0: Centroid ( %d, %d ) found with sumLnWidht %d\n"
1450 {0x00450003,
1451 "PMU0: Optimal allFine Center ( %d + %d ,%d )\n"
1453 {0x00460003,
1454 "PMU3: point %d starting at (%d,%d)\n"
1456 {0x00470002,
1457 "PMU0: picking left (%d > %d)\n"
1459 {0x00480002,
1460 "PMU0: picking right (%d > %d)\n"
1462 {0x00490002,
1463 "PMU0: picking down (%d > %d)\n"
1465 {0x004a0002,
1466 "PMU0: picking up (%d > %d)\n"
1468 {0x004b0009,
1469 "PMU3: new center @ (%3d, %3d). Moved (%2i, %2i) -- L %d, R %d, C %d, U %d, D %d\n"
1471 {0x004c0003,
1472 "PMU3: cordNum %d imporved %d to %d\n"
1474 {0x004d0000,
1477 {0x004e0004,
1478 "PMU0: Optimal allFine Center ( %d + %d ,%d ), found with weight %d.\n"
1480 {0x004f0003,
1481 "PMU0: merging lanes=%d..%d, centerMerge_t %d\n"
1483 {0x00500001,
1484 "PMU0: laneVal %d is disable\n"
1486 {0x00510002,
1487 "PMU0: checking common center %d against current center %d\n"
1489 {0x00520001,
1490 "PMU: Error: getCompoundEye Called on lane%d eye with non-compatible centers\n"
1492 {0x00530001,
1493 "PMU0: laneItr %d is disable\n"
1495 {0x00540005,
1496 "PMU0: lane %d, data_idx %d, offset_idx %d, = [%d..%d]\n"
1498 {0x00550003,
1499 "PMU0: lane %d, data_idx %d, offset_idx %d, offset_idx out of range!\n"
1501 {0x00560003,
1502 "PMU0: mergeData[%d] = max_v_low %d, min_v_high %d\n"
1504 {0x00570005,
1505 "PMU1: writing merged center (%d,%d) back to dataBlock[%d]. doDelay %d, doVoltage %d\n"
1507 {0x00580005,
1508 "PMU0: applying relative (%i,%i) back to dataBlock[%d]. doDelay %d, doVoltage %d\n"
1510 {0x00590002,
1511 "PMU0: drvstren %x is idx %d in the table\n"
1513 {0x005a0000,
1516 {0x005b0002,
1517 "PMU5: Weak 1 changed to pull-up %5d ohms, pull-down %5d ohms\n"
1519 {0x005c0002,
1520 "PMU5: Weak 0 changed to pull-up %5d ohms, pull-down %5d ohms\n"
1522 {0x005d0003,
1523 "PMU0: dlyMargin L %02d R %02d, min %02d\n"
1525 {0x005e0003,
1526 "PMU0: vrefMargin T %02d B %02d, min %02d\n"
1528 {0x005f0002,
1529 "PMU3: new minimum VrefMargin (%d < %d) recorded\n"
1531 {0x00600002,
1532 "PMU3: new minimum DlyMargin (%d < %d) recorded\n"
1534 {0x00610000,
1537 {0x00620003,
1538 "PMU0: Merging collected eyes [%d..%d) and analyzing for nibble %d's optimal rxClkDly\n"
1540 {0x00630002,
1541 "PMU0: -- centers: delay = %d, voltage = %d\n"
1543 {0x00640003,
1544 "PMU0: dumping optimized eye -- centers: delay = %d (%d), voltage = %d\n"
1546 {0x00650000,
1549 {0x00660001,
1550 "PMU3: Analyzing collected eye %d for a lane's optimal TxDqDly\n"
1552 {0x00670001,
1553 "PMU0: eye-lane %d is disable\n"
1555 {0x00680000,
1558 {0x00690002,
1559 "PMU0: Merging collected eyes [%d..%d) and analyzing for optimal device txVref\n"
1561 {0x006a0002,
1562 "PMU0: -- centers: delay = %d, voltage = %d\n"
1564 {0x006b0003,
1565 "PMU0: dumping optimized eye -- centers: delay = %d (%d), voltage = %d\n"
1567 {0x006c0000,
1570 {0x006d0005,
1571 "PMU4: DB%d L%d %3d %3d -> %3d (DISCONNECTED)\n"
1573 {0x006e0005,
1574 "PMU4: DB%d L%d %3d %3d -> %3d\n"
1576 {0x006f0005,
1577 "PMU0: writing rxClkDelay for tg%d db%1d nib%1d to 0x%02x from eye[%02d] (DISCONNECTED)\n"
1579 {0x00700003,
1580 "PMU: Error: Dbyte %d nibble %d's optimal rxClkDly of 0x%x is out of bounds\n"
1582 {0x00710005,
1583 "PMU0: writing rxClkDelay for tg%d db%1d nib%1d to 0x%02x from eye[%02d]\n"
1585 {0x00720005,
1586 "PMU0: tx voltage for tg%2d nib%2d to %3d (%d) from eye[%02d]\n"
1588 {0x00730001,
1589 "PMU0: vref Sum = %d\n"
1591 {0x00740004,
1592 "PMU0: tx voltage total is %d/%d -> %d -> %d\n"
1594 {0x00750007,
1595 …"PMU0: writing txDqDelay for tg%1d db%1d ln%1d to 0x%02x (%d coarse, %d fine) from eye[%02d] (DIS…
1597 {0x00760003,
1598 "PMU: Error: Dbyte %d lane %d's optimal txDqDly of 0x%x is out of bounds\n"
1600 {0x00770007,
1601 "PMU0: writing txDqDelay for tg%1d db%1d l%1d to 0x%02x (%d coarse, %d fine) from eye[%02d]\n"
1603 {0x00780002,
1604 "PMU0: %d (0=tx, 1=rx) TgMask for this simulation: %x\n"
1606 {0x00790001,
1607 "PMU0: eye-byte %d is disable\n"
1609 {0x007a0001,
1610 "PMU0: eye-lane %d is disable\n"
1612 {0x007b0003,
1613 "PMU10: Start d4_2d_lrdimm_rx_dfe dimm %d nbTap %d biasStepMode %d\n"
1615 {0x007c0001,
1616 "PMU10: DB DFE feature not fully supported, F2BCEx value is 0x%02x\n"
1618 {0x007d0001,
1619 "PMU10: DB DFE feature fully supported, F2BCEx value is 0x%02x\n"
1621 {0x007e0002,
1622 "PMU8: Start d4_2d_lrdimm_rx_dfe for tap %d biasStepInc %d\n"
1624 {0x007f0001,
1625 "PMU7: Start d4_2d_lrdimm_rx_dfe tapCoff 0x%0x\n"
1627 {0x00800003,
1628 "PMU6: d4_2d_lrdimm_rx_dfe db %d lane %d area %d\n"
1630 {0x00810004,
1631 "PMU7: d4_2d_lrdimm_rx_dfe db %d lane %d max area %d best bias 0x%0x\n"
1633 {0x00820001,
1634 "PMU0: eye-lane %d is disable\n"
1636 {0x00830003,
1637 "PMU5: Setting 0x%x improved rank weight (%4d < %4d)\n"
1639 {0x00840001,
1640 "PMU4: Setting 0x%x still optimal\n"
1642 {0x00850002,
1643 "PMU5: ---- Training CS%d MR%d DRAM Equalization ----\n"
1645 {0x00860001,
1646 "PMU0: eye-lane %d is disable\n"
1648 {0x00870003,
1649 "PMU0: eye %d weight %d allTgWeight %d\n"
1651 {0x00880002,
1652 "PMU5: FFE figure of merit improved from %d to %d\n"
1654 {0x00890002,
1655 "PMU: Error: LP4 rank %d cannot be mapped on tg %d\n"
1657 {0x008a0000,
1660 {0x008b0000,
1661 "PMU4: Adjusting vrefDac1 for just 0->x transitions\n"
1663 {0x008c0001,
1664 "PMU5: Strong 1, pull-up %d ohms\n"
1666 {0x008d0001,
1667 "PMU5: Strong 0, pull-down %d ohms\n"
1669 {0x008e0000,
1672 {0x008f0000,
1675 {0x00900000,
1678 {0x00910000,
1681 {0x00920002,
1682 "PMU0: targeting CsX = %d and CsY = %d\n"
1684 {0x00930001,
1687 {0x00940000,
1688 "PMU1: loading 2D acsm sequence\n"
1690 {0x00950000,
1691 "PMU1: loading 1D acsm sequence\n"
1693 {0x00960002,
1694 "PMU3: %d memclocks @ %d to get half of 300ns\n"
1696 {0x00970000,
1699 {0x00980000,
1700 "PMU3: Running 1D search for left eye edge\n"
1702 {0x00990001,
1703 "PMU1: In Phase Left Edge Search cs %d\n"
1705 {0x009a0001,
1706 "PMU1: Out of Phase Left Edge Search cs %d\n"
1708 {0x009b0000,
1709 "PMU3: Running 1D search for right eye edge\n"
1711 {0x009c0001,
1712 "PMU1: In Phase Right Edge Search cs %d\n"
1714 {0x009d0001,
1715 "PMU1: Out of Phase Right Edge Search cs %d\n"
1717 {0x009e0001,
1718 "PMU1: mxRdLat training pstate %d\n"
1720 {0x009f0001,
1721 "PMU1: mxRdLat search for cs %d\n"
1723 {0x00a00001,
1724 "PMU0: MaxRdLat non consistent DtsmLoThldXingInd 0x%03x\n"
1726 {0x00a10003,
1727 "PMU4: CS %d Dbyte %d worked with DFIMRL = %d DFICLKs\n"
1729 {0x00a20004,
1730 "PMU3: MaxRdLat Read Lane err mask for csn %d, DFIMRL %2d DFIClks, dbyte %d = 0x%03x\n"
1732 {0x00a30003,
1733 "PMU3: MaxRdLat Read Lane err mask for csn %d DFIMRL %2d, All dbytes = 0x%03x\n"
1735 {0x00a40001,
1736 …"PMU: Error: CS%d failed to find a DFIMRL setting that worked for all bytes during MaxRdLat traini…
1738 {0x00a50002,
1739 "PMU3: Smallest passing DFIMRL for all dbytes in CS%d = %d DFIClks\n"
1741 {0x00a60000,
1744 {0x00a70003,
1745 "PMU: Error: Dbyte %d lane %d txDqDly passing region is too small (width = %d)\n"
1747 {0x00a80006,
1748 "PMU10: Adjusting rxclkdly db %d nib %d from %d+%d=%d->%d\n"
1750 {0x00a90000,
1753 {0x00aa0005,
1754 "PMU4: DB %d Lane %d: %3d %3d -> %3d\n"
1756 {0x00ab0002,
1757 "PMU2: TXDQ delayLeft[%2d] = %3d (DISCONNECTED)\n"
1759 {0x00ac0004,
1760 "PMU2: TXDQ delayLeft[%2d] = %3d oopScaled = %3d selectOop %d\n"
1762 {0x00ad0002,
1763 "PMU2: TXDQ delayRight[%2d] = %3d (DISCONNECTED)\n"
1765 {0x00ae0004,
1766 "PMU2: TXDQ delayRight[%2d] = %3d oopScaled = %3d selectOop %d\n"
1768 {0x00af0003,
1769 "PMU: Error: Dbyte %d lane %d txDqDly passing region is too small (width = %d)\n"
1771 {0x00b00000,
1774 {0x00b10002,
1775 "PMU4: DB %d Lane %d: (DISCONNECTED)\n"
1777 {0x00b20005,
1778 "PMU4: DB %d Lane %d: %3d %3d -> %3d\n"
1780 {0x00b30002,
1781 "PMU3: Running 1D search csn %d for DM Right/NotLeft(%d) eye edge\n"
1783 {0x00b40002,
1784 "PMU3: WrDq DM byte%2d with Errcnt %d\n"
1786 {0x00b50002,
1787 "PMU3: WrDq DM byte%2d avgDly 0x%04x\n"
1789 {0x00b60002,
1790 "PMU1: WrDq DM byte%2d with Errcnt %d\n"
1792 {0x00b70001,
1793 "PMU: Error: Dbyte %d txDqDly DM training did not start inside the eye\n"
1795 {0x00b80000,
1798 {0x00b90002,
1799 "PMU4: DB %d Lane %d: (DISCONNECTED)\n"
1801 {0x00ba0005,
1802 "PMU4: DB %d Lane %d: %3d %3d -> %3d\n"
1804 {0x00bb0003,
1805 "PMU: Error: Dbyte %d lane %d txDqDly DM passing region is too small (width = %d)\n"
1807 {0x00bc0004,
1808 "PMU3: Errcnt for MRD/MWD search nib %2d delay = (%d, 0x%02x) = %d\n"
1810 {0x00bd0000,
1813 {0x00be0002,
1814 "PMU: Error: Dbyte %d nibble %d found mutliple working coarse delay setting for MRD/MWD\n"
1816 {0x00bf0000,
1819 {0x00c00000,
1822 {0x00c10004,
1823 …"PMU10: Warning: DB %d nibble %d has multiple working coarse delays, %d and %d, choosing the small…
1825 {0x00c20003,
1826 "PMU: Error: Dbyte %d nibble %d MRD/MWD passing region is too small (width = %d)\n"
1828 {0x00c30006,
1829 "PMU4: DB %d nibble %d: %3d, %3d %3d -> %3d\n"
1831 {0x00c40002,
1832 "PMU1: Start MRD/nMWD %d for csn %d\n"
1834 {0x00c50002,
1835 "PMU2: RXDQS delayLeft[%2d] = %3d (DISCONNECTED)\n"
1837 {0x00c60006,
1838 "PMU2: RXDQS delayLeft[%2d] = %3d delayOop[%2d] = %3d OopScaled %4d, selectOop %d\n"
1840 {0x00c70002,
1841 "PMU2: RXDQS delayRight[%2d] = %3d (DISCONNECTED)\n"
1843 {0x00c80006,
1844 "PMU2: RXDQS delayRight[%2d] = %3d delayOop[%2d] = %4d OopScaled %4d, selectOop %d\n"
1846 {0x00c90000,
1849 {0x00ca0002,
1850 "PMU4: DB %d nibble %d: (DISCONNECTED)\n"
1852 {0x00cb0005,
1853 "PMU4: DB %d nibble %d: %3d %3d -> %3d\n"
1855 {0x00cc0003,
1856 "PMU: Error: Dbyte %d nibble %d rxClkDly passing region is too small (width = %d)\n"
1858 {0x00cd0002,
1859 "PMU0: goodbar = %d for RDWR_BLEN %d\n"
1861 {0x00ce0001,
1862 "PMU3: RxClkDly = %d\n"
1864 {0x00cf0005,
1865 "PMU0: db %d l %d absLane %d -> bottom %d top %d\n"
1867 {0x00d00009,
1868 "PMU3: BYTE %d - %3d %3d %3d %3d %3d %3d %3d %3d\n"
1870 {0x00d10002,
1871 "PMU: Error: dbyte %d lane %d's per-lane vrefDAC's had no passing region\n"
1873 {0x00d20004,
1874 "PMU0: db%d l%d - %d %d\n"
1876 {0x00d30002,
1877 "PMU0: goodbar = %d for RDWR_BLEN %d\n"
1879 {0x00d40004,
1880 "PMU3: db%d l%d saw %d issues at rxClkDly %d\n"
1882 {0x00d50003,
1883 "PMU3: db%d l%d first saw a pass->fail edge at rxClkDly %d\n"
1885 {0x00d60002,
1886 "PMU3: lane %d PBD = %d\n"
1888 {0x00d70003,
1889 "PMU3: db%d l%d first saw a DBI pass->fail edge at rxClkDly %d\n"
1891 {0x00d80003,
1892 "PMU2: db%d l%d already passed rxPBD = %d\n"
1894 {0x00d90003,
1895 "PMU0: db%d l%d, PBD = %d\n"
1897 {0x00da0002,
1898 "PMU: Error: dbyte %d lane %d failed read deskew\n"
1900 {0x00db0003,
1901 "PMU0: db%d l%d, inc PBD = %d\n"
1903 {0x00dc0003,
1904 "PMU1: Running lane deskew on pstate %d csn %d rdDBIEn %d\n"
1906 {0x00dd0000,
1909 {0x00de0002,
1910 "PMU1: AcsmCsMapCtrl%02d 0x%04x\n"
1912 {0x00df0002,
1913 "PMU1: AcsmCsMapCtrl%02d 0x%04x\n"
1915 {0x00e00001,
1916 …"PMU: Error: Wrong PMU image loaded. message Block DramType = 0x%02x, but image built for D3U Type…
1918 {0x00e10001,
1919 …"PMU: Error: Wrong PMU image loaded. message Block DramType = 0x%02x, but image built for D3R Type…
1921 {0x00e20001,
1922 …"PMU: Error: Wrong PMU image loaded. message Block DramType = 0x%02x, but image built for D4U Type…
1924 {0x00e30001,
1925 …"PMU: Error: Wrong PMU image loaded. message Block DramType = 0x%02x, but image built for D4R Type…
1927 {0x00e40001,
1928 …"PMU: Error: Wrong PMU image loaded. message Block DramType = 0x%02x, but image built for D4LR Typ…
1930 {0x00e50000,
1933 {0x00e60003,
1934 "PMU10: PHY TOTALS - NUM_DBYTES %d NUM_NIBBLES %d NUM_ANIBS %d\n"
1936 {0x00e70006,
1937 …"PMU10: CSA=0x%02x, CSB=0x%02x, TSTAGES=0x%04x, HDTOUT=%d, MMISC=%d DRAMFreq=%dMT DramType=LPDDR3\…
1939 {0x00e80006,
1940 …"PMU10: CSA=0x%02x, CSB=0x%02x, TSTAGES=0x%04x, HDTOUT=%d, MMISC=%d DRAMFreq=%dMT DramType=LPDDR4\…
1942 {0x00e90008,
1943 …"PMU10: CS=0x%02x, TSTAGES=0x%04x, HDTOUT=%d, 2T=%d, MMISC=%d AddrMirror=%d DRAMFreq=%dMT DramType…
1945 {0x00ea0004,
1946 "PMU10: Pstate%d MR0=0x%04x MR1=0x%04x MR2=0x%04x\n"
1948 {0x00eb0008,
1949 …"PMU10: Pstate%d MRS MR0=0x%04x MR1=0x%04x MR2=0x%04x MR3=0x%04x MR4=0x%04x MR5=0x%04x MR6=0x%04x\…
1951 {0x00ec0005,
1952 "PMU10: Pstate%d MRS MR1_A0=0x%04x MR2_A0=0x%04x MR3_A0=0x%04x MR11_A0=0x%04x\n"
1954 {0x00ed0000,
1957 {0x00ee0005,
1958 "PMU10: Pstate%d MRS MR01_A0=0x%02x MR02_A0=0x%02x MR03_A0=0x%02x MR11_A0=0x%02x\n"
1960 {0x00ef0005,
1961 "PMU10: Pstate%d MRS MR12_A0=0x%02x MR13_A0=0x%02x MR14_A0=0x%02x MR22_A0=0x%02x\n"
1963 {0x00f00005,
1964 "PMU10: Pstate%d MRS MR01_A1=0x%02x MR02_A1=0x%02x MR03_A1=0x%02x MR11_A1=0x%02x\n"
1966 {0x00f10005,
1967 "PMU10: Pstate%d MRS MR12_A1=0x%02x MR13_A1=0x%02x MR14_A1=0x%02x MR22_A1=0x%02x\n"
1969 {0x00f20005,
1970 "PMU10: Pstate%d MRS MR01_B0=0x%02x MR02_B0=0x%02x MR03_B0=0x%02x MR11_B0=0x%02x\n"
1972 {0x00f30005,
1973 "PMU10: Pstate%d MRS MR12_B0=0x%02x MR13_B0=0x%02x MR14_B0=0x%02x MR22_B0=0x%02x\n"
1975 {0x00f40005,
1976 "PMU10: Pstate%d MRS MR01_B1=0x%02x MR02_B1=0x%02x MR03_B1=0x%02x MR11_B1=0x%02x\n"
1978 {0x00f50005,
1979 "PMU10: Pstate%d MRS MR12_B1=0x%02x MR13_B1=0x%02x MR14_B1=0x%02x MR22_B1=0x%02x\n"
1981 {0x00f60002,
1982 "PMU1: AcsmOdtCtrl%02d 0x%02x\n"
1984 {0x00f70002,
1985 "PMU1: AcsmCsMapCtrl%02d 0x%04x\n"
1987 {0x00f80002,
1988 "PMU1: AcsmCsMapCtrl%02d 0x%04x\n"
1990 {0x00f90000,
1993 {0x00fa0001,
1994 "PMU3: DDR4 infinite preamble enter/exit mode %d\n"
1996 {0x00fb0002,
1997 "PMU1: In rxenb_train() csn=%d pstate=%d\n"
1999 {0x00fc0000,
2002 {0x00fd0000,
2005 {0x00fe0009,
2008 {0x00ff0009,
2011 {0x01000002,
2012 "PMU3: Preamble search pass=%d anyfail=%d\n"
2014 {0x01010000,
2017 {0x01020000,
2020 {0x01030001,
2021 "PMU: Error: Dbyte %d couldn't find the rising edge of DQS during RxEn Training\n"
2023 {0x01040000,
2026 {0x01050001,
2027 "PMU3: Decreasing RxEn delay by %d fine step to allow full capture of reads\n"
2029 {0x01060001,
2030 "PMU3: MREP Delay = %d\n"
2032 {0x01070003,
2033 "PMU3: Errcnt for MREP nib %2d delay = %2d is %d\n"
2035 {0x01080002,
2036 "PMU3: MREP nibble %d sampled a 1 at data buffer delay %d\n"
2038 {0x01090002,
2039 "PMU3: MREP nibble %d saw a 0 to 1 transition at data buffer delay %d\n"
2041 {0x010a0000,
2042 …"PMU2: MREP did not find a 0 to 1 transition for all nibbles. Failing nibbles assumed to have ris…
2044 {0x010b0002,
2045 "PMU2: Rising edge found in alias window, setting rxDly for nibble %d = %d\n"
2047 {0x010c0002,
2048 "PMU: Error: Failed MREP for nib %d with %d one\n"
2050 {0x010d0003,
2051 "PMU2: Rising edge not found in alias window with %d one, leaving rxDly for nibble %d = %d\n"
2053 {0x010e0002,
2054 "PMU3: Training DIMM %d CSn %d\n"
2056 {0x010f0001,
2057 "PMU3: exitCAtrain_lp3 cs 0x%x\n"
2059 {0x01100001,
2060 "PMU3: enterCAtrain_lp3 cs 0x%x\n"
2062 {0x01110001,
2063 "PMU3: CAtrain_switchmsb_lp3 cs 0x%x\n"
2065 {0x01120001,
2068 {0x01130000,
2071 {0x01140001,
2072 "PMU3: DEBUG enterCAtrain_lp4 1: cs 0x%x\n"
2074 {0x01150001,
2075 "PMU3: DEBUG enterCAtrain_lp4 3: Put dbyte %d in async mode\n"
2077 {0x01160000,
2080 {0x01170003,
2081 "PMU3: DEBUG enterCAtrain_lp4 7: idx = %d vref = %x mr12 = %x\n"
2083 {0x01180001,
2086 {0x01190004,
2087 "PMU3: Phase %d CAreadbackA db:%d %x xo:%x\n"
2089 {0x011a0005,
2090 "PMU3: DEBUG lp4SetCatrVref 1: cs=%d chan=%d mr12=%x vref=%d.%d%%\n"
2092 {0x011b0003,
2093 "PMU3: DEBUG lp4SetCatrVref 3: mr12 = %x send vref= %x to db=%d\n"
2095 {0x011c0000,
2098 {0x011d0004,
2099 "PMU4:mr12:%2x cs:%d chan %d r:%4x\n"
2101 {0x011e0005,
2102 "PMU3: i:%2d bstr:%2d bsto:%2d st:%d r:%d\n"
2104 {0x011f0002,
2105 "Failed to find sufficient CA Vref Passing Region for CS %d ch. %d\n"
2107 {0x01200005,
2108 "PMU3:Found %d.%d%% MR12:%x for cs:%d chan %d\n"
2110 {0x01210002,
2111 "PMU3:Calculated %d for AtxImpedence from acx %d.\n"
2113 {0x01220000,
2114 "PMU3:CA Odt impedence ==0. Use default vref.\n"
2116 {0x01230003,
2117 "PMU3:Calculated %d.%d%% for Vref MR12=0x%x.\n"
2119 {0x01240000,
2122 {0x01250000,
2125 {0x01260001,
2126 "PMU3: CAtrain_lp testing dly %d\n"
2128 {0x01270001,
2131 {0x01280001,
2132 "PMU5: CAA%d "
2134 {0x01290001, "%02x"
2136 {0x012a0000, "\n"
2138 {0x012b0001,
2139 "PMU5: CAB%d "
2141 {0x012c0001, "%02x"
2143 {0x012d0000, "\n"
2145 {0x012e0003,
2146 "PMU3: anibi=%d, anibichan[anibi]=%d ,chan=%d\n"
2148 {0x012f0001, "%02x"
2150 {0x01300001, "\nPMU3:Raw CA setting :%x"
2152 {0x01310002, "\nPMU3:ATxDly setting:%x margin:%d\n"
2154 {0x01320002, "\nPMU3:InvClk ATxDly setting:%x margin:%d\n"
2156 {0x01330000, "\nPMU3:No Range found!\n"
2158 {0x01340003,
2159 "PMU3: 2 anibi=%d, anibichan[anibi]=%d ,chan=%d"
2161 {0x01350002, "\nPMU3: no neg clock => CA setting anib=%d, :%d\n"
2163 {0x01360001,
2164 "PMU3:Normal margin:%d\n"
2166 {0x01370001,
2167 "PMU3:Inverted margin:%d\n"
2169 {0x01380000,
2172 {0x01390000,
2175 {0x013a0003,
2176 "PMU3: 3 anibi=%d, anibichan[anibi]=%d ,chan=%d\n"
2178 {0x013b0002,
2181 {0x013c0000,
2184 {0x013d0000,
2187 {0x013e0000,
2188 "PMU4:Using MR12 values from 1D CA VREF training.\n"
2190 {0x013f0000,
2193 {0x01400000,
2196 {0x01410000,
2199 {0x01420001,
2200 "PMU10: Setting boot clock divider to %d\n"
2202 {0x01430000,
2205 {0x01440000,
2208 {0x01450000,
2211 {0x01460000,
2214 {0x01470000,
2215 "PMU10: **** Executing 2D Image ****\n"
2217 {0x01480001,
2218 "PMU10: **** Start DDR4 Training. PMU Firmware Revision 0x%04x ****\n"
2220 {0x01490001,
2221 "PMU10: **** Start DDR3 Training. PMU Firmware Revision 0x%04x ****\n"
2223 {0x014a0001,
2224 "PMU10: **** Start LPDDR3 Training. PMU Firmware Revision 0x%04x ****\n"
2226 {0x014b0001,
2227 "PMU10: **** Start LPDDR4 Training. PMU Firmware Revision 0x%04x ****\n"
2229 {0x014c0000,
2232 {0x014d0001,
2233 "PMU10: **** Testchip %d Specific Firmware ****\n"
2235 {0x014e0000,
2238 {0x014f0000,
2241 {0x01500000,
2244 {0x01510000,
2247 {0x01520000,
2250 {0x01530000,
2253 {0x01540000,
2256 {0x01550000,
2259 {0x01560000,
2262 {0x01570000,
2265 {0x01580000,
2268 {0x01590000,
2271 {0x015a0000,
2274 {0x015b0000,
2277 {0x015c0000,
2280 {0x015d0000,
2281 "PMU2: Starting SI friendly 1d RdDqs training for all ranks\n"
2283 {0x015e0000,
2286 {0x015f0000,
2287 "PMU2: Starting 1d WrDq training for all ranks\n"
2289 {0x01600000,
2292 {0x01610000,
2295 {0x01620000,
2296 "PMU2: Starting 1d RdDqs training for all ranks\n"
2298 {0x01630000,
2299 "PMU2: Starting again 1d WrDq training for all ranks\n"
2301 {0x01640000,
2304 {0x01650000,
2305 "PMU2: Starting 2d WrDq training for all ranks\n"
2307 {0x01660000,
2308 "PMU2: Starting 2d RdDqs training for all ranks\n"
2310 {0x01670002,
2313 {0x01680001,
2314 "PMU: Error: Invalid PhyDrvImpedance of 0x%x specified in message block.\n"
2316 {0x01690001,
2317 "PMU: Error: Invalid PhyOdtImpedance of 0x%x specified in message block.\n"
2319 {0x016a0001,
2320 "PMU: Error: Invalid BPZNResVal of 0x%x specified in message block.\n"
2322 {0x016b0005,
2323 "PMU3: fixRxEnBackOff csn:%d db:%d dn:%d bo:%d dly:%x\n"
2325 {0x016c0001,
2328 {0x016d0000,
2331 {0x016e0000,
2334 {0x016f0002,
2335 "PMU3:Dbyte Detect: db%d received %x\n"
2337 {0x01700002,
2338 "PMU3:getDqs2Dq read %x from dbyte %d\n"
2340 {0x01710002,
2341 "PMU3:getDqs2Dq(2) read %x from dbyte %d\n"
2343 {0x01720001,
2344 "PMU: Error: Dbyte %d read 0 from the DQS oscillator it is connected to\n"
2346 {0x01730002,
2347 "PMU4: Dbyte %d dqs2dq = %d/32 UI\n"
2349 {0x01740003,
2350 "PMU3:getDqs2Dq set dqs2dq:%d/32 ui (%d ps) from dbyte %d\n"
2352 {0x01750003,
2353 "PMU3: Setting coarse delay in AtxDly chiplet %d from 0x%02x to 0x%02x\n"
2355 {0x01760003,
2356 "PMU3: Clearing coarse delay in AtxDly chiplet %d from 0x%02x to 0x%02x\n"
2358 {0x01770000,
2361 {0x01780000,
2364 {0x01790000,
2367 {0x017a0000,
2370 {0x017b0000,
2373 {0x017c0001,
2374 "PMU1: DDR4 update Rx DBI Setting disable %d\n"
2376 {0x017d0001,
2377 "PMU1: DDR4 update 2nCk WPre Setting disable %d\n"
2379 {0x017e0005,
2380 "PMU1: read_delay: db%d lane%d delays[%2d] = 0x%02x (max 0x%02x)\n"
2382 {0x017f0004,
2383 "PMU1: write_delay: db%d lane%d delays[%2d] = 0x%04x\n"
2385 {0x01800001,
2386 "PMU5: ID=%d -- db0 db1 db2 db3 db4 db5 db6 db7 db8 db9 --\n"
2388 {0x0181000b,
2389 "PMU5: [%d]:0x %04x %04x %04x %04x %04x %04x %04x %04x %04x %04x\n"
2391 {0x01820003,
2392 "PMU2: dump delays - pstate=%d dimm=%d csn=%d\n"
2394 {0x01830000,
2397 {0x01840001,
2398 "PMU5: CS%d <<KEY>> 0 TrainingCntr <<KEY>> coarse(15:10) fine(9:0)\n"
2400 {0x01850001,
2401 "PMU5: CS%d <<KEY>> 0 RxEnDly, 1 RxClkDly <<KEY>> coarse(10:6) fine(5:0)\n"
2403 {0x01860001,
2404 "PMU5: CS%d <<KEY>> 0 TxDqsDly, 1 TxDqDly <<KEY>> coarse(9:6) fine(5:0)\n"
2406 {0x01870001,
2407 "PMU5: CS%d <<KEY>> 0 RxPBDly <<KEY>> 1 Delay Unit ~= 7ps\n"
2409 {0x01880000,
2410 "PMU5: all CS <<KEY>> 0 DFIMRL <<KEY>> Units = DFI clocks\n"
2412 {0x01890000,
2413 "PMU5: all CS <<KEY>> VrefDACs <<KEY>> DAC(6:0)\n"
2415 {0x018a0000,
2418 {0x018b0000,
2421 {0x018c0003,
2422 "PMU2: getMaxRxen(): maxDly %d maxTg %d maxNib %d\n"
2424 {0x018d0003,
2425 "PMU2: getRankMaxRxen(): maxDly %d Tg %d maxNib %d\n"
2427 {0x018e0000,
2428 "PMU1: skipping CDD calculation in 2D image\n"
2430 {0x018f0001,
2431 "PMU3: Calculating CDDs for pstate %d\n"
2433 {0x01900003,
2434 "PMU3: rxFromDly[%d][%d] = %d\n"
2436 {0x01910003,
2437 "PMU3: rxToDly [%d][%d] = %d\n"
2439 {0x01920003,
2440 "PMU3: rxDly [%d][%d] = %d\n"
2442 {0x01930003,
2443 "PMU3: txDly [%d][%d] = %d\n"
2445 {0x01940003,
2446 "PMU3: allFine CDD_RR_%d_%d = %d\n"
2448 {0x01950003,
2449 "PMU3: allFine CDD_WW_%d_%d = %d\n"
2451 {0x01960003,
2452 "PMU3: CDD_RR_%d_%d = %d\n"
2454 {0x01970003,
2455 "PMU3: CDD_WW_%d_%d = %d\n"
2457 {0x01980003,
2458 "PMU3: allFine CDD_RW_%d_%d = %d\n"
2460 {0x01990003,
2461 "PMU3: allFine CDD_WR_%d_%d = %d\n"
2463 {0x019a0003,
2464 "PMU3: CDD_RW_%d_%d = %d\n"
2466 {0x019b0003,
2467 "PMU3: CDD_WR_%d_%d = %d\n"
2469 {0x019c0004,
2470 "PMU3: F%dBC2x_B%d_D%d = 0x%02x\n"
2472 {0x019d0004,
2473 "PMU3: F%dBC3x_B%d_D%d = 0x%02x\n"
2475 {0x019e0004,
2476 "PMU3: F%dBC4x_B%d_D%d = 0x%02x\n"
2478 {0x019f0004,
2479 "PMU3: F%dBC5x_B%d_D%d = 0x%02x\n"
2481 {0x01a00004,
2482 "PMU3: F%dBC8x_B%d_D%d = 0x%02x\n"
2484 {0x01a10004,
2485 "PMU3: F%dBC9x_B%d_D%d = 0x%02x\n"
2487 {0x01a20004,
2488 "PMU3: F%dBCAx_B%d_D%d = 0x%02x\n"
2490 {0x01a30004,
2491 "PMU3: F%dBCBx_B%d_D%d = 0x%02x\n"
2493 {0x01a40000,
2496 {0x01a50003,
2497 "PMU10: context_switch_postamble is enabled for DIMM %d, RC0A=0x%x, RC3x=0x%x\n"
2499 {0x01a60000,
2500 "PMU10: Setting bcw fspace 0\n"
2502 {0x01a70001,
2503 "PMU10: Sending BC0A = 0x%x\n"
2505 {0x01a80001,
2506 "PMU10: Sending BC6x = 0x%x\n"
2508 {0x01a90001,
2509 "PMU10: Sending RC0A = 0x%x\n"
2511 {0x01aa0001,
2512 "PMU10: Sending RC3x = 0x%x\n"
2514 {0x01ab0001,
2515 "PMU10: Sending RC0A = 0x%x\n"
2517 {0x01ac0001,
2518 "PMU1: enter_lp3: DEBUG: pstate = %d\n"
2520 {0x01ad0001,
2521 "PMU1: enter_lp3: DEBUG: dfifreqxlat_pstate = %d\n"
2523 {0x01ae0001,
2524 "PMU1: enter_lp3: DEBUG: pllbypass = %d\n"
2526 {0x01af0001,
2527 "PMU1: enter_lp3: DEBUG: forcecal = %d\n"
2529 {0x01b00001,
2530 "PMU1: enter_lp3: DEBUG: pllmaxrange = 0x%x\n"
2532 {0x01b10001,
2533 "PMU1: enter_lp3: DEBUG: dacval_out = 0x%x\n"
2535 {0x01b20001,
2536 "PMU1: enter_lp3: DEBUG: pllctrl3 = 0x%x\n"
2538 {0x01b30000,
2541 {0x01b40002,
2542 "PMU3: Setting DataBuffer function space of dimmcs 0x%02x to %d\n"
2544 {0x01b50002,
2545 "PMU4: Setting RCW FxRC%Xx = 0x%02x\n"
2547 {0x01b60002,
2548 "PMU4: Setting RCW FxRC%02x = 0x%02x\n"
2550 {0x01b70001,
2551 "PMU1: DDR4 update Rd Pre Setting disable %d\n"
2553 {0x01b80002,
2554 "PMU2: Setting BCW FxBC%Xx = 0x%02x\n"
2556 {0x01b90002,
2557 "PMU2: Setting BCW BC%02x = 0x%02x\n"
2559 {0x01ba0002,
2560 "PMU2: Setting BCW PBA mode FxBC%Xx = 0x%02x\n"
2562 {0x01bb0002,
2563 "PMU2: Setting BCW PBA mode BC%02x = 0x%02x\n"
2565 {0x01bc0003,
2566 "PMU4: BCW value for dimm %d, fspace %d, addr 0x%04x\n"
2568 {0x01bd0002,
2569 "PMU4: DB %d, value 0x%02x\n"
2571 {0x01be0000,
2572 "PMU6: WARNING MREP underflow, set to min value -2 coarse, 0 fine\n"
2574 {0x01bf0004,
2575 … Writing final data buffer fine delay value nib %2d, trainDly %3d, fineDly code %2d, new MREP fine…
2577 {0x01c00003,
2578 …"PMU6: LRDIMM Writing final data buffer fine delay value nib %2d, trainDly %3d, fineDly code %2d\n"
2580 {0x01c10003,
2581 "PMU6: LRDIMM Writing data buffer fine delay type %d nib %2d, code %2d\n"
2583 {0x01c20002,
2584 "PMU6: Writing final data buffer coarse delay value dbyte %2d, coarse = 0x%02x\n"
2586 {0x01c30003,
2587 "PMU4: data 0x%04x at MB addr 0x%08x saved at CSR addr 0x%08x\n"
2589 {0x01c40003,
2590 "PMU4: data 0x%04x at MB addr 0x%08x restored from CSR addr 0x%08x\n"
2592 {0x01c50003,
2593 "PMU4: data 0x%04x at MB addr 0x%08x saved at CSR addr 0x%08x\n"
2595 {0x01c60003,
2596 "PMU4: data 0x%04x at MB addr 0x%08x restored from CSR addr 0x%08x\n"
2598 {0x01c70001,
2599 "PMU3: Update BC00, BC01, BC02 for rank-dimm 0x%02x\n"
2601 {0x01c80000,
2604 {0x01c90000,
2607 {0x01ca0000,
2610 {0x01cb0000,
2613 {0x01cc0000,
2616 {0x01cd0002,
2617 "PMU1: setAltCL Sending MR0 0x%x cl=%d\n"
2619 {0x01ce0002,
2620 "PMU1: restoreFromAltCL Sending MR0 0x%x cl=%d\n"
2622 {0x01cf0002,
2623 "PMU1: restoreAcsmFromAltCL Sending MR0 0x%x cl=%d\n"
2625 {0x01d00002,
2626 "PMU2: Setting D3R RC%d = 0x%01x\n"
2628 {0x01d10000,
2631 {0x01d20002,
2632 "PMU0: VrefDAC0/1 vddqStart %d dacToVddq %d\n"
2634 {0x01d30001,
2635 …"PMU: Error: Messageblock phyVref=0x%x is above the limit for TSMC28's attenuated LPDDR4 receivers…
2637 {0x01d40001,
2638 …"PMU: Error: Messageblock phyVref=0x%x is above the limit for TSMC28's attenuated DDR4 receivers. …
2640 {0x01d50001,
2641 "PMU0: PHY VREF @ (%d/1000) VDDQ\n"
2643 {0x01d60002,
2644 "PMU0: initalizing phy vrefDacs to %d ExtVrefRange %x\n"
2646 {0x01d70002,
2647 "PMU0: initalizing global vref to %d range %d\n"
2649 {0x01d80002,
2650 "PMU4: Setting initial device vrefDQ for CS%d to MR6 = 0x%04x\n"
2652 {0x01d90003,
2653 "PMU1: In write_level_fine() csn=%d dimm=%d pstate=%d\n"
2655 {0x01da0000,
2658 {0x01db0000,
2661 {0x01dc0007,
2662 "PMU4: WL margin for nib %2d: %08x%08x%08x%08x%08x%08x\n"
2664 {0x01dd0000,
2667 {0x01de0000,
2670 {0x01df0001,
2671 "PMU3: got %d for cl in load_wrlvl_acsm\n"
2673 {0x01e00003,
2674 "PMU1: In write_level_coarse() csn=%d dimm=%d pstate=%d\n"
2676 {0x01e10003,
2677 "PMU3: left eye edge search db:%d ln:%d dly:0x%x\n"
2679 {0x01e20003,
2680 "PMU3: right eye edge search db:%d ln:%d dly:0x%x\n"
2682 {0x01e30004,
2683 "PMU3: eye center db:%d ln:%d dly:0x%x (maxdq:%x)\n"
2685 {0x01e40003,
2686 "PMU3: Wrote to TxDqDly db:%d ln:%d dly:0x%x\n"
2688 {0x01e50003,
2689 "PMU3: Wrote to TxDqDly db:%d ln:%d dly:0x%x\n"
2691 {0x01e60002,
2692 "PMU3: Coarse write leveling dbyte%2d is still failing for TxDqsDly=0x%04x\n"
2694 {0x01e70002,
2695 "PMU4: Coarse write leveling iteration %d saw %d data miscompares across the entire phy\n"
2697 {0x01e80000,
2700 {0x01e90001,
2701 "PMU3: got %d for cl in load_wrlvl_acsm\n"
2703 {0x01ea0003,
2704 "PMU3: In write_level_coarse() csn=%d dimm=%d pstate=%d\n"
2706 {0x01eb0003,
2707 "PMU3: left eye edge search db:%d ln:%d dly:0x%x\n"
2709 {0x01ec0003,
2710 "PMU3: right eye edge search db: %d ln: %d dly: 0x%x\n"
2712 {0x01ed0004,
2713 "PMU3: eye center db: %d ln: %d dly: 0x%x (maxdq: 0x%x)\n"
2715 {0x01ee0003,
2716 "PMU3: Wrote to TxDqDly db: %d ln: %d dly: 0x%x\n"
2718 {0x01ef0003,
2719 "PMU3: Wrote to TxDqDly db: %d ln: %d dly: 0x%x\n"
2721 {0x01f00002,
2722 "PMU3: Coarse write leveling nibble%2d is still failing for TxDqsDly=0x%04x\n"
2724 {0x01f10002,
2725 "PMU4: Coarse write leveling iteration %d saw %d data miscompares across the entire phy\n"
2727 {0x01f20000,
2730 {0x01f30000,
2733 {0x01f40009,
2734 "PMU4: WL margin for nib %2d: %08x%08x%08x%08x%08x%08x%08x%08x\n"
2736 {0x01f50000,
2739 {0x01f60001,
2740 "PMU8: Adjust margin after WL coarse to be larger than %d\n"
2742 {0x01f70001,
2743 "PMU: Error: All margin after write leveling coarse are smaller than minMargin %d\n"
2745 {0x01f80002,
2746 "PMU8: Decrement nib %d TxDqsDly by %d fine step\n"
2748 {0x01f90003,
2749 "PMU3: In write_level_coarse() csn=%d dimm=%d pstate=%d\n"
2751 {0x01fa0005,
2752 "PMU2: Write level: dbyte %d nib%d dq/dmbi %2d dqsfine 0x%04x dqDly 0x%04x\n"
2754 {0x01fb0002,
2755 "PMU3: Coarse write leveling nibble%2d is still failing for TxDqsDly=0x%04x\n"
2757 {0x01fc0002,
2758 "PMU4: Coarse write leveling iteration %d saw %d data miscompares across the entire phy\n"
2760 {0x01fd0000,
2763 {0x01fe0001,
2764 "PMU3: DWL delay = %d\n"
2766 {0x01ff0003,
2767 "PMU3: Errcnt for DWL nib %2d delay = %2d is %d\n"
2769 {0x02000002,
2770 "PMU3: DWL nibble %d sampled a 1 at delay %d\n"
2772 {0x02010003,
2773 "PMU3: DWL nibble %d passed at delay %d. Rising edge was at %d\n"
2775 {0x02020000,
2778 {0x02030002,
2779 "PMU2: Rising edge found in alias window, setting wrlvlDly for nibble %d = %d\n"
2781 {0x02040002,
2782 "PMU: Error: Failed DWL for nib %d with %d one\n"
2784 {0x02050003,
2785 "PMU2: Rising edge not found in alias window with %d one, leaving wrlvlDly for nibble %d = %d\n"
2787 {0x04000000,
2790 {0x04010000,
2793 {0x04020000,
2796 {0x04030002,
2797 "PMU1: swapByte db %d by %d\n"
2799 {0x04040003,
2800 "PMU3: get_cmd_dly max(%d ps, %d memclk) = %d\n"
2802 {0x04050002,
2803 "PMU0: Write CSR 0x%06x 0x%04x\n"
2805 {0x04060002,
2806 "PMU0: hwt_init_ppgc_prbs(): Polynomial: %x, Deg: %d\n"
2808 {0x04070001,
2809 "PMU: Error: acsm_set_cmd to non existent instruction address %d\n"
2811 {0x04080001,
2812 "PMU: Error: acsm_set_cmd with unknown ddr cmd 0x%x\n"
2814 {0x0409000c,
2817 {0x040a0000,
2820 {0x040b0000,
2823 {0x040c0000,
2826 {0x040d0002,
2829 {0x040e0002,
2830 "PMU: Error: setAcsmCLCWL: cl and cwl must be each >= 2 and 5, resp. CL=%d CWL=%d\n"
2832 {0x040f0002,
2833 "PMU: Error: setAcsmCLCWL: cl and cwl must be each >= 5. CL=%d CWL=%d\n"
2835 {0x04100002,
2836 "PMU1: setAcsmCLCWL: CASL %04d WCASL %04d\n"
2838 {0x04110001,
2839 "PMU: Error: Reserved value of register F0RC0F found in message block: 0x%04x\n"
2841 {0x04120001,
2842 "PMU3: Written MRS to CS=0x%02x\n"
2844 {0x04130001,
2845 "PMU3: Written MRS to CS=0x%02x\n"
2847 {0x04140000,
2850 {0x04150001,
2851 "PMU: Error: Boot clock divider setting of %d is too small\n"
2853 {0x04160000,
2856 {0x04170002,
2857 "PMU3: Writing MR%d OP=%x\n"
2859 {0x04180000,
2862 {0x04190001,
2863 "PMU3: Written MRS to CS=0x%02x\n"
2865 {0x041a0000,
2868 {0x041b0000,
2871 {0x041c0000,
2874 {0x041d0002,
2875 "PMU2: Use PDA mode to set MR%d with value 0x%02x\n"
2877 {0x041e0001,
2878 "PMU3: Written Vref with PDA to CS=0x%02x\n"
2880 {0x041f0000,
2883 {0x04200000,
2884 "PMU1: start_cal: DEBUG: setting CalRun to 0\n"
2886 {0x04210001,
2887 "PMU1: lock_pll_dll: DEBUG: pstate = %d\n"
2889 {0x04220001,
2890 "PMU1: lock_pll_dll: DEBUG: dfifreqxlat_pstate = %d\n"
2892 {0x04230001,
2893 "PMU1: lock_pll_dll: DEBUG: pllbypass = %d\n"
2895 {0x04240001,
2896 "PMU3: SaveLcdlSeed: Saving seed %d\n"
2898 {0x04250000,
2901 {0x04260003,
2902 "PMU3: ACXConf:%d MaxNumDbytes:%d NumDfi:%d\n"
2904 {0x04270005,
2905 "PMU1: setAltAcsmCLCWL setting cl=%d cwl=%d\n"