Lines Matching refs:interrupts

13 - MSI: message signaled interrupts. In this document, synonymous with MSI-X.
14 - MSI-X: message signaled interrupts - extended
24 MSI is used to refer to the concept of message signaled interrupts, but it always refers to
25 interrupts sent via MSI-X because that is what CrosVM uses.
27 ### Legacy interrupts (INTx)
29 These interrupts are traditionally delivered via dedicated signal lines to PICs and/or the IOAPIC.
31 interrupts. These typically are the first 24 GSIs, and are serviced either by the PIC (during very
72 ## The fundamental deception on x86_64: there are no legacy interrupts (usually)
74 After very early boot, the PIC is switched off and legacy interrupts somewhat cease to be legacy.
75 Instead of being handled by the PIC, legacy interrupts are handled by the IOAPIC, and all the IOAPIC
81 Each `IrqChip` can handle interrupts differently. Often these differences are because the underlying
92 Below, we describe the rough flow for interrupts in virtio devices for each of the chip types. We
102 1. The LAPIC interrupts the VCPU, which jumps to the kernel's ISR (interrupt service routine).
105 #### Legacy interrupts
123 1. The LAPIC interrupts the VCPU, which jumps to the kernel’s ISR (interrupt service routine).
128 #### Legacy interrupts
131 `Event`, and the MSI is also an `Event`. These interrupts are processed twice by the IRQ handler: