Lines Matching +full:thread +full:- +full:1 +full:- +full:4
32 ret = drm_intel_bo_subdata(batch->bo, 0, 4096, batch->buffer); in gen7_render_flush()
34 ret = drm_intel_bo_mrb_exec(batch->bo, batch_end, in gen7_render_flush()
44 ret = drm_intel_bo_subdata(batch->bo, 0, 4096, batch->buffer); in gen7_render_context_flush()
46 ret = drm_intel_gem_bo_context_exec(batch->bo, batch->ctx, in gen7_render_context_flush()
78 *curbe_buffer = 1; in gen11_fill_curbe_buffer_data()
103 ss->ss0.surface_type = SURFACE_2D; in gen7_fill_surface_state()
104 ss->ss0.surface_format = format; in gen7_fill_surface_state()
105 ss->ss0.render_cache_read_write = 1; in gen7_fill_surface_state()
107 if (buf->tiling == I915_TILING_X) in gen7_fill_surface_state()
108 ss->ss0.tiled_mode = 2; in gen7_fill_surface_state()
109 else if (buf->tiling == I915_TILING_Y) in gen7_fill_surface_state()
110 ss->ss0.tiled_mode = 3; in gen7_fill_surface_state()
112 ss->ss1.base_addr = buf->bo->offset; in gen7_fill_surface_state()
113 ret = drm_intel_bo_emit_reloc(batch->bo, in gen7_fill_surface_state()
114 intel_batchbuffer_subdata_offset(batch, ss) + 4, in gen7_fill_surface_state()
115 buf->bo, 0, in gen7_fill_surface_state()
119 ss->ss2.height = igt_buf_height(buf) - 1; in gen7_fill_surface_state()
120 ss->ss2.width = igt_buf_width(buf) - 1; in gen7_fill_surface_state()
122 ss->ss3.pitch = buf->stride - 1; in gen7_fill_surface_state()
124 ss->ss7.shader_chanel_select_r = 4; in gen7_fill_surface_state()
125 ss->ss7.shader_chanel_select_g = 5; in gen7_fill_surface_state()
126 ss->ss7.shader_chanel_select_b = 6; in gen7_fill_surface_state()
127 ss->ss7.shader_chanel_select_a = 7; in gen7_fill_surface_state()
140 if (IS_GEN7(batch->devid)) in gen7_fill_binding_table()
142 SURFACEFORMAT_R8_UNORM, 1); in gen7_fill_binding_table()
145 SURFACEFORMAT_R8_UNORM, 1); in gen7_fill_binding_table()
162 binding_table[1] = gen11_fill_surface_state(batch, dst, in gen11_fill_binding_table()
164 1,1, in gen11_fill_binding_table()
165 1); in gen11_fill_binding_table()
172 const uint32_t kernel[][4], in gen7_fill_kernel() argument
185 const uint32_t kernel[][4], in gen7_fill_interface_descriptor() argument
198 idd->desc0.kernel_start_pointer = (kernel_offset >> 6); in gen7_fill_interface_descriptor()
200 idd->desc1.single_program_flow = 1; in gen7_fill_interface_descriptor()
201 idd->desc1.floating_point_mode = GEN7_FLOATING_POINT_IEEE_754; in gen7_fill_interface_descriptor()
203 idd->desc2.sampler_count = 0; /* 0 samplers used */ in gen7_fill_interface_descriptor()
204 idd->desc2.sampler_state_pointer = 0; in gen7_fill_interface_descriptor()
206 idd->desc3.binding_table_entry_count = 0; in gen7_fill_interface_descriptor()
207 idd->desc3.binding_table_pointer = (binding_table_offset >> 5); in gen7_fill_interface_descriptor()
209 idd->desc4.constant_urb_entry_read_offset = 0; in gen7_fill_interface_descriptor()
210 idd->desc4.constant_urb_entry_read_length = 1; /* grf 1 */ in gen7_fill_interface_descriptor()
218 OUT_BATCH(GEN7_STATE_BASE_ADDRESS | (10 - 2)); in gen7_emit_state_base_address()
224 OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, in gen7_emit_state_base_address()
228 OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, in gen7_emit_state_base_address()
235 OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, in gen7_emit_state_base_address()
250 OUT_BATCH(GEN7_MEDIA_VFE_STATE | (8 - 2)); in gen7_emit_vfe_state()
275 OUT_BATCH(GEN7_MEDIA_CURBE_LOAD | (4 - 2)); in gen7_emit_curbe_load()
287 OUT_BATCH(GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD | (4 - 2)); in gen7_emit_interface_descriptor_load()
290 if (IS_GEN7(batch->devid)) in gen7_emit_interface_descriptor_load()
322 * Simply do SIMD16 based dispatch, so every thread uses in gen7_emit_gpgpu_walk()
325 * Define our own thread group size, e.g 16x1 for every group, then in gen7_emit_gpgpu_walk()
326 * will have 1 thread each group in SIMD16 dispatch. So thread in gen7_emit_gpgpu_walk()
327 * width/height/depth are all 1. in gen7_emit_gpgpu_walk()
329 * Then thread group X = width / 16 (aligned to 16) in gen7_emit_gpgpu_walk()
330 * thread group Y = height; in gen7_emit_gpgpu_walk()
337 right_mask = (1 << 16) - 1; in gen7_emit_gpgpu_walk()
339 right_mask = (1 << tmp) - 1; in gen7_emit_gpgpu_walk()
346 /* SIMD size, thread w/h/d */ in gen7_emit_gpgpu_walk()
347 OUT_BATCH(1 << 30 | /* SIMD16 */ in gen7_emit_gpgpu_walk()
348 0 << 16 | /* depth:1 */ in gen7_emit_gpgpu_walk()
349 0 << 8 | /* height:1 */ in gen7_emit_gpgpu_walk()
350 0); /* width:1 */ in gen7_emit_gpgpu_walk()
352 /* thread group X */ in gen7_emit_gpgpu_walk()
356 /* thread group Y */ in gen7_emit_gpgpu_walk()
360 /* thread group Z */ in gen7_emit_gpgpu_walk()
362 OUT_BATCH(1); in gen7_emit_gpgpu_walk()
367 /* bottom mask, height 1, always 0xffffffff */ in gen7_emit_gpgpu_walk()
405 ss->ss0.surface_type = SURFACE_2D; in gen8_fill_surface_state()
406 ss->ss0.surface_format = format; in gen8_fill_surface_state()
407 ss->ss0.render_cache_read_write = 1; in gen8_fill_surface_state()
408 ss->ss0.vertical_alignment = 1; /* align 4 */ in gen8_fill_surface_state()
409 ss->ss0.horizontal_alignment = 1; /* align 4 */ in gen8_fill_surface_state()
411 if (buf->tiling == I915_TILING_X) in gen8_fill_surface_state()
412 ss->ss0.tiled_mode = 2; in gen8_fill_surface_state()
413 else if (buf->tiling == I915_TILING_Y) in gen8_fill_surface_state()
414 ss->ss0.tiled_mode = 3; in gen8_fill_surface_state()
416 ss->ss8.base_addr = buf->bo->offset; in gen8_fill_surface_state()
418 ret = drm_intel_bo_emit_reloc(batch->bo, in gen8_fill_surface_state()
419 intel_batchbuffer_subdata_offset(batch, ss) + 8 * 4, in gen8_fill_surface_state()
420 buf->bo, 0, read_domain, write_domain); in gen8_fill_surface_state()
423 ss->ss2.height = igt_buf_height(buf) - 1; in gen8_fill_surface_state()
424 ss->ss2.width = igt_buf_width(buf) - 1; in gen8_fill_surface_state()
425 ss->ss3.pitch = buf->stride - 1; in gen8_fill_surface_state()
427 ss->ss7.shader_chanel_select_r = 4; in gen8_fill_surface_state()
428 ss->ss7.shader_chanel_select_g = 5; in gen8_fill_surface_state()
429 ss->ss7.shader_chanel_select_b = 6; in gen8_fill_surface_state()
430 ss->ss7.shader_chanel_select_a = 7; in gen8_fill_surface_state()
458 ss->ss0.surface_type = surface_type; in gen11_fill_surface_state()
459 ss->ss0.surface_format = format; in gen11_fill_surface_state()
460 ss->ss0.render_cache_read_write = 1; in gen11_fill_surface_state()
461 ss->ss0.vertical_alignment = vertical_alignment; /* align 4 */ in gen11_fill_surface_state()
462 ss->ss0.horizontal_alignment = horizontal_alignment; /* align 4 */ in gen11_fill_surface_state()
464 if (buf->tiling == I915_TILING_X) in gen11_fill_surface_state()
465 ss->ss0.tiled_mode = 2; in gen11_fill_surface_state()
466 else if (buf->tiling == I915_TILING_Y) in gen11_fill_surface_state()
467 ss->ss0.tiled_mode = 3; in gen11_fill_surface_state()
469 ss->ss0.tiled_mode = 0; in gen11_fill_surface_state()
471 ss->ss8.base_addr = buf->bo->offset; in gen11_fill_surface_state()
473 ret = drm_intel_bo_emit_reloc(batch->bo, in gen11_fill_surface_state()
474 intel_batchbuffer_subdata_offset(batch, ss) + 8 * 4, in gen11_fill_surface_state()
475 buf->bo, 0, read_domain, write_domain); in gen11_fill_surface_state()
479 ss->ss1.memory_object_control = 2; in gen11_fill_surface_state()
480 ss->ss2.height = 1; in gen11_fill_surface_state()
481 ss->ss2.width = 95; in gen11_fill_surface_state()
482 ss->ss3.pitch = 0; in gen11_fill_surface_state()
483 ss->ss7.shader_chanel_select_r = 4; in gen11_fill_surface_state()
484 ss->ss7.shader_chanel_select_g = 5; in gen11_fill_surface_state()
485 ss->ss7.shader_chanel_select_b = 6; in gen11_fill_surface_state()
486 ss->ss7.shader_chanel_select_a = 7; in gen11_fill_surface_state()
489 ss->ss1.qpitch = 4040; in gen11_fill_surface_state()
490 ss->ss1.base_mip_level = 31; in gen11_fill_surface_state()
491 ss->ss2.height = 9216; in gen11_fill_surface_state()
492 ss->ss2.width = 1019; in gen11_fill_surface_state()
493 ss->ss3.pitch = 64; in gen11_fill_surface_state()
494 ss->ss5.mip_count = 2; in gen11_fill_surface_state()
503 const uint32_t kernel[][4], in gen8_fill_interface_descriptor() argument
516 idd->desc0.kernel_start_pointer = (kernel_offset >> 6); in gen8_fill_interface_descriptor()
518 idd->desc2.single_program_flow = 1; in gen8_fill_interface_descriptor()
519 idd->desc2.floating_point_mode = GEN8_FLOATING_POINT_IEEE_754; in gen8_fill_interface_descriptor()
521 idd->desc3.sampler_count = 0; /* 0 samplers used */ in gen8_fill_interface_descriptor()
522 idd->desc3.sampler_state_pointer = 0; in gen8_fill_interface_descriptor()
524 idd->desc4.binding_table_entry_count = 0; in gen8_fill_interface_descriptor()
525 idd->desc4.binding_table_pointer = (binding_table_offset >> 5); in gen8_fill_interface_descriptor()
527 idd->desc5.constant_urb_entry_read_offset = 0; in gen8_fill_interface_descriptor()
528 idd->desc5.constant_urb_entry_read_length = 1; /* grf 1 */ in gen8_fill_interface_descriptor()
530 idd->desc6.num_threads_in_tg = 1; in gen8_fill_interface_descriptor()
538 const uint32_t kernel[][4], in gen11_fill_interface_descriptor() argument
551 idd->desc0.kernel_start_pointer = (kernel_offset >> 6); in gen11_fill_interface_descriptor()
553 idd->desc2.single_program_flow = 1; in gen11_fill_interface_descriptor()
554 idd->desc2.floating_point_mode = GEN8_FLOATING_POINT_IEEE_754; in gen11_fill_interface_descriptor()
556 idd->desc3.sampler_count = 0; /* 0 samplers used */ in gen11_fill_interface_descriptor()
557 idd->desc3.sampler_state_pointer = 0; in gen11_fill_interface_descriptor()
559 idd->desc4.binding_table_entry_count = 0; in gen11_fill_interface_descriptor()
560 idd->desc4.binding_table_pointer = (binding_table_offset >> 5); in gen11_fill_interface_descriptor()
562 idd->desc5.constant_urb_entry_read_offset = 0; in gen11_fill_interface_descriptor()
563 idd->desc5.constant_urb_entry_read_length = 1; /* grf 1 */ in gen11_fill_interface_descriptor()
565 idd->desc6.num_threads_in_tg = 1; in gen11_fill_interface_descriptor()
573 OUT_BATCH(GEN8_STATE_BASE_ADDRESS | (16 - 2)); in gen8_emit_state_base_address()
583 OUT_RELOC(batch->bo, I915_GEM_DOMAIN_SAMPLER, 0, BASE_ADDRESS_MODIFY); in gen8_emit_state_base_address()
586 OUT_RELOC(batch->bo, in gen8_emit_state_base_address()
595 OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, in gen8_emit_state_base_address()
599 OUT_BATCH(0xfffff000 | 1); in gen8_emit_state_base_address()
601 OUT_BATCH(1 << 12 | 1); in gen8_emit_state_base_address()
603 OUT_BATCH(0xfffff000 | 1); in gen8_emit_state_base_address()
607 OUT_BATCH(1 << 12 | 1); in gen8_emit_state_base_address()
613 OUT_BATCH(GEN8_MEDIA_STATE_FLUSH | (2 - 2)); in gen8_emit_media_state_flush()
622 OUT_BATCH(GEN7_MEDIA_VFE_STATE | (9 - 2)); in gen8_emit_vfe_state()
652 * Simply do SIMD16 based dispatch, so every thread uses in gen8_emit_gpgpu_walk()
655 * Define our own thread group size, e.g 16x1 for every group, then in gen8_emit_gpgpu_walk()
656 * will have 1 thread each group in SIMD16 dispatch. So thread in gen8_emit_gpgpu_walk()
657 * width/height/depth are all 1. in gen8_emit_gpgpu_walk()
659 * Then thread group X = width / 16 (aligned to 16) in gen8_emit_gpgpu_walk()
660 * thread group Y = height; in gen8_emit_gpgpu_walk()
667 right_mask = (1 << 16) - 1; in gen8_emit_gpgpu_walk()
669 right_mask = (1 << tmp) - 1; in gen8_emit_gpgpu_walk()
677 /* SIMD size, thread w/h/d */ in gen8_emit_gpgpu_walk()
678 OUT_BATCH(1 << 30 | /* SIMD16 */ in gen8_emit_gpgpu_walk()
679 0 << 16 | /* depth:1 */ in gen8_emit_gpgpu_walk()
680 0 << 8 | /* height:1 */ in gen8_emit_gpgpu_walk()
681 0); /* width:1 */ in gen8_emit_gpgpu_walk()
683 /* thread group X */ in gen8_emit_gpgpu_walk()
688 /* thread group Y */ in gen8_emit_gpgpu_walk()
693 /* thread group Z */ in gen8_emit_gpgpu_walk()
695 OUT_BATCH(1); in gen8_emit_gpgpu_walk()
700 /* bottom mask, height 1, always 0xffffffff */ in gen8_emit_gpgpu_walk()
708 OUT_BATCH(GEN7_MEDIA_OBJECT | (8 - 2)); in gen_emit_media_object()
724 if (AT_LEAST_GEN(batch->devid, 8) && !IS_CHERRYVIEW(batch->devid)) in gen_emit_media_object()
731 OUT_BATCH(GEN8_STATE_BASE_ADDRESS | (19 - 2)); in gen9_emit_state_base_address()
741 OUT_RELOC(batch->bo, I915_GEM_DOMAIN_SAMPLER, 0, BASE_ADDRESS_MODIFY); in gen9_emit_state_base_address()
744 OUT_RELOC(batch->bo, in gen9_emit_state_base_address()
753 OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, in gen9_emit_state_base_address()
757 OUT_BATCH(0xfffff000 | 1); in gen9_emit_state_base_address()
759 OUT_BATCH(1 << 12 | 1); in gen9_emit_state_base_address()
761 OUT_BATCH(0xfffff000 | 1); in gen9_emit_state_base_address()
765 OUT_BATCH(1 << 12 | 1); in gen9_emit_state_base_address()