Lines Matching +full:1 +full:- +full:9
1 ; RUN: llc -fast-isel -fast-isel-abort=1 -mtriple=aarch64-apple-darwin -verify-machineinstrs < %s |…
3 ; CHECK-LABEL: asr_zext_i1_i16
4 ; CHECK: uxth {{w[0-9]*}}, wzr
6 %1 = zext i1 %b to i16
7 %2 = ashr i16 %1, 1
11 ; CHECK-LABEL: asr_sext_i1_i16
12 ; CHECK: sbfx [[REG1:w[0-9]+]], {{w[0-9]*}}, #0, #1
13 ; CHECK-NEXT: sxth {{w[0-9]*}}, [[REG1]]
15 %1 = sext i1 %b to i16
16 %2 = ashr i16 %1, 1
20 ; CHECK-LABEL: asr_zext_i1_i32
21 ; CHECK: mov {{w[0-9]*}}, wzr
23 %1 = zext i1 %b to i32
24 %2 = ashr i32 %1, 1
28 ; CHECK-LABEL: asr_sext_i1_i32
29 ; CHECK: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #0, #1
31 %1 = sext i1 %b to i32
32 %2 = ashr i32 %1, 1
36 ; CHECK-LABEL: asr_zext_i1_i64
37 ; CHECK: mov {{x[0-9]*}}, xzr
39 %1 = zext i1 %b to i64
40 %2 = ashr i64 %1, 1
44 ; CHECK-LABEL: asr_sext_i1_i64
45 ; CHECK: sbfx {{x[0-9]*}}, {{x[0-9]*}}, #0, #1
47 %1 = sext i1 %b to i64
48 %2 = ashr i64 %1, 1
52 ; CHECK-LABEL: lsr_zext_i1_i16
53 ; CHECK: uxth {{w[0-9]*}}, wzr
55 %1 = zext i1 %b to i16
56 %2 = lshr i16 %1, 1
60 ; CHECK-LABEL: lsr_sext_i1_i16
61 ; CHECK: sbfx [[REG1:w[0-9]+]], {{w[0-9]*}}, #0, #1
62 ; CHECK-NEXT: ubfx [[REG2:w[0-9]+]], [[REG1]], #1, #15
63 ; CHECK-NEXT: sxth {{w[0-9]*}}, [[REG2]]
65 %1 = sext i1 %b to i16
66 %2 = lshr i16 %1, 1
70 ; CHECK-LABEL: lsr_zext_i1_i32
71 ; CHECK: mov {{w[0-9]*}}, wzr
73 %1 = zext i1 %b to i32
74 %2 = lshr i32 %1, 1
78 ; CHECK-LABEL: lsr_sext_i1_i32
79 ; CHECK: sbfx [[REG1:w[0-9]+]], {{w[0-9]*}}, #0, #1
80 ; CHECK-NEXT: lsr {{w[0-9]*}}, [[REG1:w[0-9]+]], #1
82 %1 = sext i1 %b to i32
83 %2 = lshr i32 %1, 1
87 ; CHECK-LABEL: lsr_zext_i1_i64
88 ; CHECK: mov {{x[0-9]*}}, xzr
90 %1 = zext i1 %b to i64
91 %2 = lshr i64 %1, 1
95 ; CHECK-LABEL: lsl_zext_i1_i16
96 ; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #1
98 %1 = zext i1 %b to i16
99 %2 = shl i16 %1, 4
103 ; CHECK-LABEL: lsl_sext_i1_i16
104 ; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #1
106 %1 = sext i1 %b to i16
107 %2 = shl i16 %1, 4
111 ; CHECK-LABEL: lsl_zext_i1_i32
112 ; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #1
114 %1 = zext i1 %b to i32
115 %2 = shl i32 %1, 4
119 ; CHECK-LABEL: lsl_sext_i1_i32
120 ; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #1
122 %1 = sext i1 %b to i32
123 %2 = shl i32 %1, 4
127 ; CHECK-LABEL: lsl_zext_i1_i64
128 ; CHECK: ubfiz {{x[0-9]*}}, {{x[0-9]*}}, #4, #1
130 %1 = zext i1 %b to i64
131 %2 = shl i64 %1, 4
135 ; CHECK-LABEL: lsl_sext_i1_i64
136 ; CHECK: sbfiz {{x[0-9]*}}, {{x[0-9]*}}, #4, #1
138 %1 = sext i1 %b to i64
139 %2 = shl i64 %1, 4
143 ; CHECK-LABEL: lslv_i8
144 ; CHECK: and [[REG1:w[0-9]+]], w1, #0xff
145 ; CHECK-NEXT: lsl [[REG2:w[0-9]+]], w0, [[REG1]]
146 ; CHECK-NEXT: and {{w[0-9]+}}, [[REG2]], #0xff
148 %1 = shl i8 %a, %b
149 ret i8 %1
152 ; CHECK-LABEL: lsl_i8
153 ; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
155 %1 = shl i8 %a, 4
156 ret i8 %1
159 ; CHECK-LABEL: lsl_zext_i8_i16
160 ; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #8
162 %1 = zext i8 %b to i16
163 %2 = shl i16 %1, 4
167 ; CHECK-LABEL: lsl_sext_i8_i16
168 ; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #8
170 %1 = sext i8 %b to i16
171 %2 = shl i16 %1, 4
175 ; CHECK-LABEL: lsl_zext_i8_i32
176 ; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #8
178 %1 = zext i8 %b to i32
179 %2 = shl i32 %1, 4
183 ; CHECK-LABEL: lsl_sext_i8_i32
184 ; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #8
186 %1 = sext i8 %b to i32
187 %2 = shl i32 %1, 4
191 ; CHECK-LABEL: lsl_zext_i8_i64
192 ; CHECK: ubfiz {{x[0-9]*}}, {{x[0-9]*}}, #4, #8
194 %1 = zext i8 %b to i64
195 %2 = shl i64 %1, 4
199 ; CHECK-LABEL: lsl_sext_i8_i64
200 ; CHECK: sbfiz {{x[0-9]*}}, {{x[0-9]*}}, #4, #8
202 %1 = sext i8 %b to i64
203 %2 = shl i64 %1, 4
207 ; CHECK-LABEL: lslv_i16
208 ; CHECK: and [[REG1:w[0-9]+]], w1, #0xffff
209 ; CHECK-NEXT: lsl [[REG2:w[0-9]+]], w0, [[REG1]]
210 ; CHECK-NEXT: and {{w[0-9]+}}, [[REG2]], #0xffff
212 %1 = shl i16 %a, %b
213 ret i16 %1
216 ; CHECK-LABEL: lsl_i16
217 ; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #8, #8
219 %1 = shl i16 %a, 8
220 ret i16 %1
223 ; CHECK-LABEL: lsl_zext_i16_i32
224 ; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #8, #16
226 %1 = zext i16 %b to i32
227 %2 = shl i32 %1, 8
231 ; CHECK-LABEL: lsl_sext_i16_i32
232 ; CHECK: sbfiz {{w[0-9]*}}, {{w[0-9]*}}, #8, #16
234 %1 = sext i16 %b to i32
235 %2 = shl i32 %1, 8
239 ; CHECK-LABEL: lsl_zext_i16_i64
240 ; CHECK: ubfiz {{x[0-9]*}}, {{x[0-9]*}}, #8, #16
242 %1 = zext i16 %b to i64
243 %2 = shl i64 %1, 8
247 ; CHECK-LABEL: lsl_sext_i16_i64
248 ; CHECK: sbfiz {{x[0-9]*}}, {{x[0-9]*}}, #8, #16
250 %1 = sext i16 %b to i64
251 %2 = shl i64 %1, 8
255 ; CHECK-LABEL: lslv_i32
256 ; CHECK: lsl {{w[0-9]*}}, w0, w1
258 %1 = shl i32 %a, %b
259 ret i32 %1
262 ; CHECK-LABEL: lsl_i32
263 ; CHECK: lsl {{w[0-9]*}}, {{w[0-9]*}}, #16
265 %1 = shl i32 %a, 16
266 ret i32 %1
269 ; CHECK-LABEL: lsl_zext_i32_i64
270 ; CHECK: ubfiz {{x[0-9]+}}, {{x[0-9]+}}, #16, #32
272 %1 = zext i32 %b to i64
273 %2 = shl i64 %1, 16
277 ; CHECK-LABEL: lsl_sext_i32_i64
278 ; CHECK: sbfiz {{x[0-9]+}}, {{x[0-9]+}}, #16, #32
280 %1 = sext i32 %b to i64
281 %2 = shl i64 %1, 16
285 ; CHECK-LABEL: lslv_i64
286 ; CHECK: lsl {{x[0-9]*}}, x0, x1
288 %1 = shl i64 %a, %b
289 ret i64 %1
292 ; CHECK-LABEL: lsl_i64
293 ; CHECK: lsl {{x[0-9]*}}, {{x[0-9]*}}, #32
295 %1 = shl i64 %a, 32
296 ret i64 %1
299 ; CHECK-LABEL: lsrv_i8
300 ; CHECK: and [[REG1:w[0-9]+]], w0, #0xff
301 ; CHECK-NEXT: and [[REG2:w[0-9]+]], w1, #0xff
302 ; CHECK-NEXT: lsr [[REG3:w[0-9]+]], [[REG1]], [[REG2]]
303 ; CHECK-NEXT: and {{w[0-9]+}}, [[REG3]], #0xff
305 %1 = lshr i8 %a, %b
306 ret i8 %1
309 ; CHECK-LABEL: lsr_i8
310 ; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
312 %1 = lshr i8 %a, 4
313 ret i8 %1
316 ; CHECK-LABEL: lsr_zext_i8_i16
317 ; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
319 %1 = zext i8 %b to i16
320 %2 = lshr i16 %1, 4
324 ; CHECK-LABEL: lsr_sext_i8_i16
325 ; CHECK: sxtb [[REG:w[0-9]+]], w0
326 ; CHECK-NEXT: ubfx {{w[0-9]*}}, [[REG]], #4, #12
328 %1 = sext i8 %b to i16
329 %2 = lshr i16 %1, 4
333 ; CHECK-LABEL: lsr_zext_i8_i32
334 ; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
336 %1 = zext i8 %b to i32
337 %2 = lshr i32 %1, 4
341 ; CHECK-LABEL: lsr_sext_i8_i32
342 ; CHECK: sxtb [[REG:w[0-9]+]], w0
343 ; CHECK-NEXT: lsr {{w[0-9]*}}, [[REG]], #4
345 %1 = sext i8 %b to i32
346 %2 = lshr i32 %1, 4
350 ; CHECK-LABEL: lsrv_i16
351 ; CHECK: and [[REG1:w[0-9]+]], w0, #0xffff
352 ; CHECK-NEXT: and [[REG2:w[0-9]+]], w1, #0xffff
353 ; CHECK-NEXT: lsr [[REG3:w[0-9]+]], [[REG1]], [[REG2]]
354 ; CHECK-NEXT: and {{w[0-9]+}}, [[REG3]], #0xffff
356 %1 = lshr i16 %a, %b
357 ret i16 %1
360 ; CHECK-LABEL: lsr_i16
361 ; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #8, #8
363 %1 = lshr i16 %a, 8
364 ret i16 %1
367 ; CHECK-LABEL: lsrv_i32
368 ; CHECK: lsr {{w[0-9]*}}, w0, w1
370 %1 = lshr i32 %a, %b
371 ret i32 %1
374 ; CHECK-LABEL: lsr_i32
375 ; CHECK: lsr {{w[0-9]*}}, {{w[0-9]*}}, #16
377 %1 = lshr i32 %a, 16
378 ret i32 %1
381 ; CHECK-LABEL: lsrv_i64
382 ; CHECK: lsr {{x[0-9]*}}, x0, x1
384 %1 = lshr i64 %a, %b
385 ret i64 %1
388 ; CHECK-LABEL: lsr_i64
389 ; CHECK: lsr {{x[0-9]*}}, {{x[0-9]*}}, #32
391 %1 = lshr i64 %a, 32
392 ret i64 %1
395 ; CHECK-LABEL: asrv_i8
396 ; CHECK: sxtb [[REG1:w[0-9]+]], w0
397 ; CHECK-NEXT: and [[REG2:w[0-9]+]], w1, #0xff
398 ; CHECK-NEXT: asr [[REG3:w[0-9]+]], [[REG1]], [[REG2]]
399 ; CHECK-NEXT: and {{w[0-9]+}}, [[REG3]], #0xff
401 %1 = ashr i8 %a, %b
402 ret i8 %1
405 ; CHECK-LABEL: asr_i8
406 ; CHECK: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
408 %1 = ashr i8 %a, 4
409 ret i8 %1
412 ; CHECK-LABEL: asr_zext_i8_i16
413 ; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
415 %1 = zext i8 %b to i16
416 %2 = ashr i16 %1, 4
420 ; CHECK-LABEL: asr_sext_i8_i16
421 ; CHECK: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
423 %1 = sext i8 %b to i16
424 %2 = ashr i16 %1, 4
428 ; CHECK-LABEL: asr_zext_i8_i32
429 ; CHECK: ubfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
431 %1 = zext i8 %b to i32
432 %2 = ashr i32 %1, 4
436 ; CHECK-LABEL: asr_sext_i8_i32
437 ; CHECK: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
439 %1 = sext i8 %b to i32
440 %2 = ashr i32 %1, 4
444 ; CHECK-LABEL: asrv_i16
445 ; CHECK: sxth [[REG1:w[0-9]+]], w0
446 ; CHECK-NEXT: and [[REG2:w[0-9]+]], w1, #0xffff
447 ; CHECK-NEXT: asr [[REG3:w[0-9]+]], [[REG1]], [[REG2]]
448 ; CHECK-NEXT: and {{w[0-9]+}}, [[REG3]], #0xffff
450 %1 = ashr i16 %a, %b
451 ret i16 %1
454 ; CHECK-LABEL: asr_i16
455 ; CHECK: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #8, #8
457 %1 = ashr i16 %a, 8
458 ret i16 %1
461 ; CHECK-LABEL: asrv_i32
462 ; CHECK: asr {{w[0-9]*}}, w0, w1
464 %1 = ashr i32 %a, %b
465 ret i32 %1
468 ; CHECK-LABEL: asr_i32
469 ; CHECK: asr {{w[0-9]*}}, {{w[0-9]*}}, #16
471 %1 = ashr i32 %a, 16
472 ret i32 %1
475 ; CHECK-LABEL: asrv_i64
476 ; CHECK: asr {{x[0-9]*}}, x0, x1
478 %1 = ashr i64 %a, %b
479 ret i64 %1
482 ; CHECK-LABEL: asr_i64
483 ; CHECK: asr {{x[0-9]*}}, {{x[0-9]*}}, #32
485 %1 = ashr i64 %a, 32
486 ret i64 %1
489 ; CHECK-LABEL: shift_test1
490 ; CHECK: ubfiz {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
491 ; CHECK-NEXT: sbfx {{w[0-9]*}}, {{w[0-9]*}}, #4, #4
493 %1 = shl i8 %a, 4
494 %2 = ashr i8 %1, 4
501 ; CHECK-LABEL: shl_zero
502 ; CHECK-NOT: lsl
504 %1 = shl i32 %a, 0
505 ret i32 %1
508 ; CHECK-LABEL: lshr_zero
509 ; CHECK-NOT: lsr
511 %1 = lshr i32 %a, 0
512 ret i32 %1
515 ; CHECK-LABEL: ashr_zero
516 ; CHECK-NOT: asr
518 %1 = ashr i32 %a, 0
519 ret i32 %1
522 ; CHECK-LABEL: shl_zext_zero
525 %1 = zext i32 %a to i64
526 %2 = shl i64 %1, 0
530 ; CHECK-LABEL: lshr_zext_zero
533 %1 = zext i32 %a to i64
534 %2 = lshr i64 %1, 0
538 ; CHECK-LABEL: ashr_zext_zero
541 %1 = zext i32 %a to i64
542 %2 = ashr i64 %1, 0