Lines Matching +full:0 +full:- +full:9

1 …RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -fp-contract=fast < %s | FileCheck -chec…
2 … RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs -fp-contract=fast < %s | FileCheck -chec…
4 declare i32 @llvm.amdgcn.workitem.id.x() #0
5 declare double @llvm.fabs.f64(double) #0
6 declare double @llvm.fma.f64(double, double, double) #0
7 declare float @llvm.fma.f32(float, float, float) #0
9 ; (fadd (fmul x, y), z) -> (fma x, y, z)
10 ; FUNC-LABEL: {{^}}combine_to_fma_f64_0:
11 ; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
12 ; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
13 ; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
14 ; SI: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[C]]
17   %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
18   %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
19   %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
20   %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
23   %a = load volatile double, double addrspace(1)* %gep.0
33 ; (fadd (fmul x, y), z) -> (fma x, y, z)
34 ; FUNC-LABEL: {{^}}combine_to_fma_f64_0_2use:
35 ; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
36 ; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
37 ; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
38 ; SI-DAG: buffer_load_dwordx2 [[D:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
39 ; SI-DAG: v_fma_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[C]]
40 ; SI-DAG: v_fma_f64 [[RESULT1:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[D]]
41 ; SI-DAG: buffer_store_dwordx2 [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr6…
42 ; SI-DAG: buffer_store_dwordx2 [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr6…
45   %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
46   %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
47   %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
48   %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
49   %gep.3 = getelementptr double, double addrspace(1)* %gep.0, i32 3
50   %gep.out.0 = getelementptr double, double addrspace(1)* %out, i32 %tid
51   %gep.out.1 = getelementptr double, double addrspace(1)* %gep.out.0, i32 1
53   %a = load volatile double, double addrspace(1)* %gep.0
61   store volatile double %fma0, double addrspace(1)* %gep.out.0
66 ; (fadd x, (fmul y, z)) -> (fma y, z, x)
67 ; FUNC-LABEL: {{^}}combine_to_fma_f64_1:
68 ; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
69 ; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
70 ; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
71 ; SI: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[C]]
74   %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
75   %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
76   %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
77   %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
80   %a = load volatile double, double addrspace(1)* %gep.0
90 ; (fsub (fmul x, y), z) -> (fma x, y, (fneg z))
91 ; FUNC-LABEL: {{^}}combine_to_fma_fsub_0_f64:
92 ; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
93 ; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
94 ; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
95 ; SI: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], -[[C]]
98   %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
99   %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
100   %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
101   %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
104   %a = load volatile double, double addrspace(1)* %gep.0
114 ; (fsub (fmul x, y), z) -> (fma x, y, (fneg z))
115 ; FUNC-LABEL: {{^}}combine_to_fma_fsub_f64_0_2use:
116 ; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
117 ; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
118 ; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
119 ; SI-DAG: buffer_load_dwordx2 [[D:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
120 ; SI-DAG: v_fma_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], -[[C]]
121 ; SI-DAG: v_fma_f64 [[RESULT1:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], -[[D]]
122 ; SI-DAG: buffer_store_dwordx2 [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr6…
123 ; SI-DAG: buffer_store_dwordx2 [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr6…
126   %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
127   %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
128   %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
129   %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
130   %gep.3 = getelementptr double, double addrspace(1)* %gep.0, i32 3
131   %gep.out.0 = getelementptr double, double addrspace(1)* %out, i32 %tid
132   %gep.out.1 = getelementptr double, double addrspace(1)* %gep.out.0, i32 1
134   %a = load volatile double, double addrspace(1)* %gep.0
142   store volatile double %fma0, double addrspace(1)* %gep.out.0
147 ; (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)
148 ; FUNC-LABEL: {{^}}combine_to_fma_fsub_1_f64:
149 ; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
150 ; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
151 ; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
152 ; SI: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], -[[A]], [[B]], [[C]]
155   %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
156   %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
157   %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
158   %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
161   %a = load volatile double, double addrspace(1)* %gep.0
171 ; (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)
172 ; FUNC-LABEL: {{^}}combine_to_fma_fsub_1_f64_2use:
173 ; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
174 ; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
175 ; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
176 ; SI-DAG: buffer_load_dwordx2 [[D:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
177 ; SI-DAG: v_fma_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], -[[A]], [[B]], [[C]]
178 ; SI-DAG: v_fma_f64 [[RESULT1:v\[[0-9]+:[0-9]+\]]], -[[A]], [[B]], [[D]]
179 ; SI-DAG: buffer_store_dwordx2 [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr6…
180 ; SI-DAG: buffer_store_dwordx2 [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr6…
183   %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
184   %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
185   %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
186   %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
187   %gep.3 = getelementptr double, double addrspace(1)* %gep.0, i32 3
188   %gep.out.0 = getelementptr double, double addrspace(1)* %out, i32 %tid
189   %gep.out.1 = getelementptr double, double addrspace(1)* %gep.out.0, i32 1
191   %a = load volatile double, double addrspace(1)* %gep.0
199   store volatile double %fma0, double addrspace(1)* %gep.out.0
204 ; (fsub (fneg (fmul x, y)), z) -> (fma (fneg x), y, (fneg z))
205 ; FUNC-LABEL: {{^}}combine_to_fma_fsub_2_f64:
206 ; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
207 ; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
208 ; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
209 ; SI: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], -[[A]], [[B]], -[[C]]
212   %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
213   %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
214   %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
215   %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
218   %a = load volatile double, double addrspace(1)* %gep.0
223   %mul.neg = fsub double -0.0, %mul
230 ; (fsub (fneg (fmul x, y)), z) -> (fma (fneg x), y, (fneg z))
231 ; FUNC-LABEL: {{^}}combine_to_fma_fsub_2_f64_2uses_neg:
232 ; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
233 ; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
234 ; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
235 ; SI-DAG: v_fma_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], -[[A]], [[B]], -[[C]]
236 ; SI-DAG: v_fma_f64 [[RESULT1:v\[[0-9]+:[0-9]+\]]], -[[A]], [[B]], -[[D]]
237 ; SI-DAG: buffer_store_dwordx2 [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr6…
238 ; SI-DAG: buffer_store_dwordx2 [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr6…
241   %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
242   %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
243   %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
244   %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
245   %gep.3 = getelementptr double, double addrspace(1)* %gep.0, i32 3
246   %gep.out.0 = getelementptr double, double addrspace(1)* %out, i32 %tid
247   %gep.out.1 = getelementptr double, double addrspace(1)* %gep.out.0, i32 1
249   %a = load volatile double, double addrspace(1)* %gep.0
255   %mul.neg = fsub double -0.0, %mul
259   store volatile double %fma0, double addrspace(1)* %gep.out.0
264 ; (fsub (fneg (fmul x, y)), z) -> (fma (fneg x), y, (fneg z))
265 ; FUNC-LABEL: {{^}}combine_to_fma_fsub_2_f64_2uses_mul:
266 ; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
267 ; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
268 ; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
269 ; SI-DAG: v_fma_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], -[[A]], [[B]], -[[C]]
270 ; SI-DAG: v_fma_f64 [[RESULT1:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], -[[D]]
271 ; SI-DAG: buffer_store_dwordx2 [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr6…
272 ; SI-DAG: buffer_store_dwordx2 [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr6…
275   %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
276   %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
277   %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
278   %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
279   %gep.3 = getelementptr double, double addrspace(1)* %gep.0, i32 3
280   %gep.out.0 = getelementptr double, double addrspace(1)* %out, i32 %tid
281   %gep.out.1 = getelementptr double, double addrspace(1)* %gep.out.0, i32 1
283   %a = load volatile double, double addrspace(1)* %gep.0
289   %mul.neg = fsub double -0.0, %mul
293   store volatile double %fma0, double addrspace(1)* %gep.out.0
298 ; fold (fsub (fma x, y, (fmul u, v)), z) -> (fma x, y (fma u, v, (fneg z)))
300 ; FUNC-LABEL: {{^}}aggressive_combine_to_fma_fsub_0_f64:
301 ; SI-DAG: buffer_load_dwordx2 [[X:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
302 ; SI-DAG: buffer_load_dwordx2 [[Y:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
303 ; SI-DAG: buffer_load_dwordx2 [[Z:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
304 ; SI-DAG: buffer_load_dwordx2 [[U:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
305 ; SI-DAG: buffer_load_dwordx2 [[V:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
306 ; SI: v_fma_f64 [[FMA0:v\[[0-9]+:[0-9]+\]]], [[U]], [[V]], -[[Z]]
307 ; SI: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[X]], [[Y]], [[FMA0]]
310   %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
311   %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
312   %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
313   %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
314   %gep.3 = getelementptr double, double addrspace(1)* %gep.0, i32 3
315   %gep.4 = getelementptr double, double addrspace(1)* %gep.0, i32 4
318   %x = load volatile double, double addrspace(1)* %gep.0
325   %tmp1 = call double @llvm.fma.f64(double %x, double %y, double %tmp0) #0
333 ;   -> (fma (fneg y), z, (fma (fneg u), v, x))
335 ; FUNC-LABEL: {{^}}aggressive_combine_to_fma_fsub_1_f64:
336 ; SI-DAG: buffer_load_dwordx2 [[X:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
337 ; SI-DAG: buffer_load_dwordx2 [[Y:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
338 ; SI-DAG: buffer_load_dwordx2 [[Z:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
339 ; SI-DAG: buffer_load_dwordx2 [[U:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
340 ; SI-DAG: buffer_load_dwordx2 [[V:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\…
341 ; SI: v_fma_f64 [[FMA0:v\[[0-9]+:[0-9]+\]]], -[[U]], [[V]], [[X]]
342 ; SI: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], -[[Y]], [[Z]], [[FMA0]]
345   %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
346   %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
347   %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
348   %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
349   %gep.3 = getelementptr double, double addrspace(1)* %gep.0, i32 3
350   %gep.4 = getelementptr double, double addrspace(1)* %gep.0, i32 4
353   %x = load volatile double, double addrspace(1)* %gep.0
360   %tmp1 = call double @llvm.fma.f64(double %y, double %z, double %tmp0) #0
371 ; FUNC-LABEL: {{^}}test_f32_mul_add_x_one_y:
372 ; SI: v_mac_f32_e32 [[VY:v[0-9]]], [[VY:v[0-9]]], [[VX:v[0-9]]]
384 ; FUNC-LABEL: {{^}}test_f32_mul_y_add_x_one:
385 ; SI: v_mac_f32_e32 [[VY:v[0-9]]], [[VY:v[0-9]]], [[VX:v[0-9]]]
397 ; FUNC-LABEL: {{^}}test_f32_mul_add_x_negone_y:
398 ; SI: v_mad_f32 [[VX:v[0-9]]], [[VX]], [[VY:v[0-9]]], -[[VY]]
404   %a = fadd float %x, -1.0
410 ; FUNC-LABEL: {{^}}test_f32_mul_y_add_x_negone:
411 ; SI: v_mad_f32 [[VX:v[0-9]]], [[VX]], [[VY:v[0-9]]], -[[VY]]
417   %a = fadd float %x, -1.0
423 ; FUNC-LABEL: {{^}}test_f32_mul_sub_one_x_y:
424 ; SI: v_mad_f32 [[VX:v[0-9]]], -[[VX]], [[VY:v[0-9]]], [[VY]]
436 ; FUNC-LABEL: {{^}}test_f32_mul_y_sub_one_x:
437 ; SI: v_mad_f32 [[VX:v[0-9]]], -[[VX]], [[VY:v[0-9]]], [[VY]]
449 ; FUNC-LABEL: {{^}}test_f32_mul_sub_negone_x_y:
450 ; SI: v_mad_f32 [[VX:v[0-9]]], -[[VX]], [[VY:v[0-9]]], -[[VY]]
456   %s = fsub float -1.0, %x
462 ; FUNC-LABEL: {{^}}test_f32_mul_y_sub_negone_x:
463 ; SI: v_mad_f32 [[VX:v[0-9]]], -[[VX]], [[VY:v[0-9]]], -[[VY]]
469   %s = fsub float -1.0, %x
475 ; FUNC-LABEL: {{^}}test_f32_mul_sub_x_one_y:
476 ; SI: v_mad_f32 [[VX:v[0-9]]], [[VX]], [[VY:v[0-9]]], -[[VY]]
488 ; FUNC-LABEL: {{^}}test_f32_mul_y_sub_x_one:
489 ; SI: v_mad_f32 [[VX:v[0-9]]], [[VX]], [[VY:v[0-9]]], -[[VY]]
501 ; FUNC-LABEL: {{^}}test_f32_mul_sub_x_negone_y:
502 ; SI: v_mac_f32_e32 [[VY:v[0-9]]], [[VY]], [[VX:v[0-9]]]
508   %s = fsub float %x, -1.0
514 ; FUNC-LABEL: {{^}}test_f32_mul_y_sub_x_negone:
515 ; SI: v_mac_f32_e32 [[VY:v[0-9]]], [[VY]], [[VX:v[0-9]]]
521   %s = fsub float %x, -1.0
531 ; FUNC-LABEL: {{^}}test_f32_interp:
532 ; SI: v_mad_f32 [[VR:v[0-9]]], -[[VT:v[0-9]]], [[VY:v[0-9]]], [[VY]]
533 ; SI: v_mac_f32_e32 [[VR]], [[VT]], [[VX:v[0-9]]]
549 ; FUNC-LABEL: {{^}}test_f64_interp:
550 ; SI: v_fma_f64 [[VR:v\[[0-9]+:[0-9]+\]]], -[[VT:v\[[0-9]+:[0-9]+\]]], [[VY:v\[[0-9]+:[0-9]+\]]], […
551 ; SI: v_fma_f64 [[VR:v\[[0-9]+:[0-9]+\]]], [[VX:v\[[0-9]+:[0-9]+\]]], [[VT]], [[VR]]
567 attributes #0 = { nounwind readnone }