Lines Matching +full:1 +full:- +full:9

1 ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check…
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check…
4 ; Use a 64-bit value with lo bits that can be represented as an inline constant
5 ; CHECK-LABEL: {{^}}i64_imm_inline_lo:
6 ; CHECK: v_mov_b32_e32 v[[LO_VGPR:[0-9]+]], 5
8 define void @i64_imm_inline_lo(i64 addrspace(1) *%out) {
10   store i64 1311768464867721221, i64 addrspace(1) *%out ; 0x1234567800000005
14 ; Use a 64-bit value with hi bits that can be represented as an inline constant
15 ; CHECK-LABEL: {{^}}i64_imm_inline_hi:
16 ; CHECK: v_mov_b32_e32 v[[HI_VGPR:[0-9]+]], 5
17 ; CHECK: buffer_store_dwordx2 v{{\[[0-9]+:}}[[HI_VGPR]]
18 define void @i64_imm_inline_hi(i64 addrspace(1) *%out) {
20   store i64 21780256376, i64 addrspace(1) *%out ; 0x0000000512345678
24 ; CHECK-LABEL: {{^}}store_imm_neg_0.0_i64:
25 ; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}}
26 ; CHECK-DAG: v_bfrev_b32_e32 v[[HI_VREG:[0-9]+]], 1{{$}}
28 define void @store_imm_neg_0.0_i64(i64 addrspace(1) *%out) {
29   store i64 -9223372036854775808, i64 addrspace(1) *%out
33 ; CHECK-LABEL: {{^}}store_inline_imm_neg_0.0_i32:
34 ; CHECK: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}}
36 define void @store_inline_imm_neg_0.0_i32(i32 addrspace(1)* %out) {
37   store i32 -2147483648, i32 addrspace(1)* %out
41 ; CHECK-LABEL: {{^}}store_inline_imm_0.0_f32:
42 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}}
44 define void @store_inline_imm_0.0_f32(float addrspace(1)* %out) {
45   store float 0.0, float addrspace(1)* %out
49 ; CHECK-LABEL: {{^}}store_imm_neg_0.0_f32:
50 ; CHECK: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}}
52 define void @store_imm_neg_0.0_f32(float addrspace(1)* %out) {
53   store float -0.0, float addrspace(1)* %out
57 ; CHECK-LABEL: {{^}}store_inline_imm_0.5_f32:
58 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0.5{{$}}
60 define void @store_inline_imm_0.5_f32(float addrspace(1)* %out) {
61   store float 0.5, float addrspace(1)* %out
65 ; CHECK-LABEL: {{^}}store_inline_imm_m_0.5_f32:
66 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -0.5{{$}}
68 define void @store_inline_imm_m_0.5_f32(float addrspace(1)* %out) {
69   store float -0.5, float addrspace(1)* %out
73 ; CHECK-LABEL: {{^}}store_inline_imm_1.0_f32:
74 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0{{$}}
76 define void @store_inline_imm_1.0_f32(float addrspace(1)* %out) {
77   store float 1.0, float addrspace(1)* %out
81 ; CHECK-LABEL: {{^}}store_inline_imm_m_1.0_f32:
82 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -1.0{{$}}
84 define void @store_inline_imm_m_1.0_f32(float addrspace(1)* %out) {
85   store float -1.0, float addrspace(1)* %out
89 ; CHECK-LABEL: {{^}}store_inline_imm_2.0_f32:
90 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 2.0{{$}}
92 define void @store_inline_imm_2.0_f32(float addrspace(1)* %out) {
93   store float 2.0, float addrspace(1)* %out
97 ; CHECK-LABEL: {{^}}store_inline_imm_m_2.0_f32:
98 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -2.0{{$}}
100 define void @store_inline_imm_m_2.0_f32(float addrspace(1)* %out) {
101   store float -2.0, float addrspace(1)* %out
105 ; CHECK-LABEL: {{^}}store_inline_imm_4.0_f32:
106 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 4.0{{$}}
108 define void @store_inline_imm_4.0_f32(float addrspace(1)* %out) {
109   store float 4.0, float addrspace(1)* %out
113 ; CHECK-LABEL: {{^}}store_inline_imm_m_4.0_f32:
114 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], -4.0{{$}}
116 define void @store_inline_imm_m_4.0_f32(float addrspace(1)* %out) {
117   store float -4.0, float addrspace(1)* %out
121 ; CHECK-LABEL: {{^}}store_literal_imm_f32:
122 ; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0x45800000
124 define void @store_literal_imm_f32(float addrspace(1)* %out) {
125   store float 4096.0, float addrspace(1)* %out
129 ; CHECK-LABEL: {{^}}add_inline_imm_0.0_f32:
130 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
131 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 0, [[VAL]]{{$}}
133 define void @add_inline_imm_0.0_f32(float addrspace(1)* %out, float %x) {
135   store float %y, float addrspace(1)* %out
139 ; CHECK-LABEL: {{^}}add_inline_imm_0.5_f32:
140 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
141 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 0.5, [[VAL]]{{$}}
143 define void @add_inline_imm_0.5_f32(float addrspace(1)* %out, float %x) {
145   store float %y, float addrspace(1)* %out
149 ; CHECK-LABEL: {{^}}add_inline_imm_neg_0.5_f32:
150 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
151 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -0.5, [[VAL]]{{$}}
153 define void @add_inline_imm_neg_0.5_f32(float addrspace(1)* %out, float %x) {
154   %y = fadd float %x, -0.5
155   store float %y, float addrspace(1)* %out
159 ; CHECK-LABEL: {{^}}add_inline_imm_1.0_f32:
160 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
161 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 1.0, [[VAL]]{{$}}
163 define void @add_inline_imm_1.0_f32(float addrspace(1)* %out, float %x) {
165   store float %y, float addrspace(1)* %out
169 ; CHECK-LABEL: {{^}}add_inline_imm_neg_1.0_f32:
170 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
171 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -1.0, [[VAL]]{{$}}
173 define void @add_inline_imm_neg_1.0_f32(float addrspace(1)* %out, float %x) {
174   %y = fadd float %x, -1.0
175   store float %y, float addrspace(1)* %out
179 ; CHECK-LABEL: {{^}}add_inline_imm_2.0_f32:
180 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
181 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 2.0, [[VAL]]{{$}}
183 define void @add_inline_imm_2.0_f32(float addrspace(1)* %out, float %x) {
185   store float %y, float addrspace(1)* %out
189 ; CHECK-LABEL: {{^}}add_inline_imm_neg_2.0_f32:
190 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
191 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -2.0, [[VAL]]{{$}}
193 define void @add_inline_imm_neg_2.0_f32(float addrspace(1)* %out, float %x) {
194   %y = fadd float %x, -2.0
195   store float %y, float addrspace(1)* %out
199 ; CHECK-LABEL: {{^}}add_inline_imm_4.0_f32:
200 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
201 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 4.0, [[VAL]]{{$}}
203 define void @add_inline_imm_4.0_f32(float addrspace(1)* %out, float %x) {
205   store float %y, float addrspace(1)* %out
209 ; CHECK-LABEL: {{^}}add_inline_imm_neg_4.0_f32:
210 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
211 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -4.0, [[VAL]]{{$}}
213 define void @add_inline_imm_neg_4.0_f32(float addrspace(1)* %out, float %x) {
214   %y = fadd float %x, -4.0
215   store float %y, float addrspace(1)* %out
219 ; CHECK-LABEL: {{^}}commute_add_inline_imm_0.5_f32:
220 ; CHECK: buffer_load_dword [[VAL:v[0-9]+]]
221 ; CHECK: v_add_f32_e32 [[REG:v[0-9]+]], 0.5, [[VAL]]
223 define void @commute_add_inline_imm_0.5_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
224   %x = load float, float addrspace(1)* %in
226   store float %y, float addrspace(1)* %out
230 ; CHECK-LABEL: {{^}}commute_add_literal_f32:
231 ; CHECK: buffer_load_dword [[VAL:v[0-9]+]]
232 ; CHECK: v_add_f32_e32 [[REG:v[0-9]+]], 0x44800000, [[VAL]]
234 define void @commute_add_literal_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
235   %x = load float, float addrspace(1)* %in
237   store float %y, float addrspace(1)* %out
241 ; CHECK-LABEL: {{^}}add_inline_imm_1_f32:
242 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
243 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 1, [[VAL]]{{$}}
245 define void @add_inline_imm_1_f32(float addrspace(1)* %out, float %x) {
247   store float %y, float addrspace(1)* %out
251 ; CHECK-LABEL: {{^}}add_inline_imm_2_f32:
252 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
253 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 2, [[VAL]]{{$}}
255 define void @add_inline_imm_2_f32(float addrspace(1)* %out, float %x) {
257   store float %y, float addrspace(1)* %out
261 ; CHECK-LABEL: {{^}}add_inline_imm_16_f32:
262 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
263 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 16, [[VAL]]
265 define void @add_inline_imm_16_f32(float addrspace(1)* %out, float %x) {
267   store float %y, float addrspace(1)* %out
271 ; CHECK-LABEL: {{^}}add_inline_imm_neg_1_f32:
272 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
273 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -1, [[VAL]]
275 define void @add_inline_imm_neg_1_f32(float addrspace(1)* %out, float %x) {
277   store float %y, float addrspace(1)* %out
281 ; CHECK-LABEL: {{^}}add_inline_imm_neg_2_f32:
282 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
283 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -2, [[VAL]]
285 define void @add_inline_imm_neg_2_f32(float addrspace(1)* %out, float %x) {
287   store float %y, float addrspace(1)* %out
291 ; CHECK-LABEL: {{^}}add_inline_imm_neg_16_f32:
292 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
293 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], -16, [[VAL]]
295 define void @add_inline_imm_neg_16_f32(float addrspace(1)* %out, float %x) {
297   store float %y, float addrspace(1)* %out
301 ; CHECK-LABEL: {{^}}add_inline_imm_63_f32:
302 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
303 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 63, [[VAL]]
305 define void @add_inline_imm_63_f32(float addrspace(1)* %out, float %x) {
307   store float %y, float addrspace(1)* %out
311 ; CHECK-LABEL: {{^}}add_inline_imm_64_f32:
312 ; CHECK: s_load_dword [[VAL:s[0-9]+]]
313 ; CHECK: v_add_f32_e64 [[REG:v[0-9]+]], 64, [[VAL]]
315 define void @add_inline_imm_64_f32(float addrspace(1)* %out, float %x) {
317   store float %y, float addrspace(1)* %out
322 ; CHECK-LABEL: {{^}}add_inline_imm_0.0_f64:
323 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
324 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
325 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 0{{$}}
327 define void @add_inline_imm_0.0_f64(double addrspace(1)* %out, double %x) {
329   store double %y, double addrspace(1)* %out
333 ; CHECK-LABEL: {{^}}add_inline_imm_0.5_f64:
334 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
335 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
336 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 0.5
338 define void @add_inline_imm_0.5_f64(double addrspace(1)* %out, double %x) {
340   store double %y, double addrspace(1)* %out
344 ; CHECK-LABEL: {{^}}add_inline_imm_neg_0.5_f64:
345 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
346 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
347 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], -0.5
349 define void @add_inline_imm_neg_0.5_f64(double addrspace(1)* %out, double %x) {
350   %y = fadd double %x, -0.5
351   store double %y, double addrspace(1)* %out
355 ; CHECK-LABEL: {{^}}add_inline_imm_1.0_f64:
356 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
357 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
358 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 1.0
360 define void @add_inline_imm_1.0_f64(double addrspace(1)* %out, double %x) {
362   store double %y, double addrspace(1)* %out
366 ; CHECK-LABEL: {{^}}add_inline_imm_neg_1.0_f64:
367 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
368 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
369 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], -1.0
371 define void @add_inline_imm_neg_1.0_f64(double addrspace(1)* %out, double %x) {
372   %y = fadd double %x, -1.0
373   store double %y, double addrspace(1)* %out
377 ; CHECK-LABEL: {{^}}add_inline_imm_2.0_f64:
378 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
379 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
380 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 2.0
382 define void @add_inline_imm_2.0_f64(double addrspace(1)* %out, double %x) {
384   store double %y, double addrspace(1)* %out
388 ; CHECK-LABEL: {{^}}add_inline_imm_neg_2.0_f64:
389 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
390 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
391 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], -2.0
393 define void @add_inline_imm_neg_2.0_f64(double addrspace(1)* %out, double %x) {
394   %y = fadd double %x, -2.0
395   store double %y, double addrspace(1)* %out
399 ; CHECK-LABEL: {{^}}add_inline_imm_4.0_f64:
400 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
401 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
402 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 4.0
404 define void @add_inline_imm_4.0_f64(double addrspace(1)* %out, double %x) {
406   store double %y, double addrspace(1)* %out
410 ; CHECK-LABEL: {{^}}add_inline_imm_neg_4.0_f64:
411 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
412 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
413 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], -4.0
415 define void @add_inline_imm_neg_4.0_f64(double addrspace(1)* %out, double %x) {
416   %y = fadd double %x, -4.0
417   store double %y, double addrspace(1)* %out
422 ; CHECK-LABEL: {{^}}add_inline_imm_1_f64:
423 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
424 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
425 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 1{{$}}
427 define void @add_inline_imm_1_f64(double addrspace(1)* %out, double %x) {
429   store double %y, double addrspace(1)* %out
433 ; CHECK-LABEL: {{^}}add_inline_imm_2_f64:
434 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
435 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
436 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 2{{$}}
438 define void @add_inline_imm_2_f64(double addrspace(1)* %out, double %x) {
440   store double %y, double addrspace(1)* %out
444 ; CHECK-LABEL: {{^}}add_inline_imm_16_f64:
445 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
446 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
447 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 16
449 define void @add_inline_imm_16_f64(double addrspace(1)* %out, double %x) {
451   store double %y, double addrspace(1)* %out
455 ; CHECK-LABEL: {{^}}add_inline_imm_neg_1_f64:
456 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
457 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
458 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], -1
460 define void @add_inline_imm_neg_1_f64(double addrspace(1)* %out, double %x) {
462   store double %y, double addrspace(1)* %out
466 ; CHECK-LABEL: {{^}}add_inline_imm_neg_2_f64:
467 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
468 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
469 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], -2
471 define void @add_inline_imm_neg_2_f64(double addrspace(1)* %out, double %x) {
473   store double %y, double addrspace(1)* %out
477 ; CHECK-LABEL: {{^}}add_inline_imm_neg_16_f64:
478 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
479 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
480 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], -16
482 define void @add_inline_imm_neg_16_f64(double addrspace(1)* %out, double %x) {
484   store double %y, double addrspace(1)* %out
488 ; CHECK-LABEL: {{^}}add_inline_imm_63_f64:
489 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
490 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
491 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 63
493 define void @add_inline_imm_63_f64(double addrspace(1)* %out, double %x) {
495   store double %y, double addrspace(1)* %out
499 ; CHECK-LABEL: {{^}}add_inline_imm_64_f64:
500 ; SI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
501 ; VI: s_load_dwordx2 [[VAL:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x2c
502 ; CHECK: v_add_f64 [[REG:v\[[0-9]+:[0-9]+\]]], [[VAL]], 64
504 define void @add_inline_imm_64_f64(double addrspace(1)* %out, double %x) {
506   store double %y, double addrspace(1)* %out
511 ; CHECK-LABEL: {{^}}store_inline_imm_0.0_f64:
512 ; CHECK: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0
513 ; CHECK: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], v[[LO_VREG]]{{$}}
515 define void @store_inline_imm_0.0_f64(double addrspace(1)* %out) {
516   store double 0.0, double addrspace(1)* %out
521 ; CHECK-LABEL: {{^}}store_literal_imm_neg_0.0_f64:
522 ; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}}
523 ; CHECK-DAG: v_bfrev_b32_e32 v[[HI_VREG:[0-9]+]], 1{{$}}
525 define void @store_literal_imm_neg_0.0_f64(double addrspace(1)* %out) {
526   store double -0.0, double addrspace(1)* %out
530 ; CHECK-LABEL: {{^}}store_inline_imm_0.5_f64:
531 ; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}}
532 ; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0x3fe00000
534 define void @store_inline_imm_0.5_f64(double addrspace(1)* %out) {
535   store double 0.5, double addrspace(1)* %out
539 ; CHECK-LABEL: {{^}}store_inline_imm_m_0.5_f64:
540 ; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}}
541 ; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0xbfe00000
543 define void @store_inline_imm_m_0.5_f64(double addrspace(1)* %out) {
544   store double -0.5, double addrspace(1)* %out
548 ; CHECK-LABEL: {{^}}store_inline_imm_1.0_f64:
549 ; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}}
550 ; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0x3ff00000
552 define void @store_inline_imm_1.0_f64(double addrspace(1)* %out) {
553   store double 1.0, double addrspace(1)* %out
557 ; CHECK-LABEL: {{^}}store_inline_imm_m_1.0_f64:
558 ; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}}
559 ; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0xbff00000
561 define void @store_inline_imm_m_1.0_f64(double addrspace(1)* %out) {
562   store double -1.0, double addrspace(1)* %out
566 ; CHECK-LABEL: {{^}}store_inline_imm_2.0_f64:
567 ; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}}
568 ; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 2.0
570 define void @store_inline_imm_2.0_f64(double addrspace(1)* %out) {
571   store double 2.0, double addrspace(1)* %out
575 ; CHECK-LABEL: {{^}}store_inline_imm_m_2.0_f64:
576 ; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}}
577 ; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], -2.0
579 define void @store_inline_imm_m_2.0_f64(double addrspace(1)* %out) {
580   store double -2.0, double addrspace(1)* %out
584 ; CHECK-LABEL: {{^}}store_inline_imm_4.0_f64:
585 ; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}}
586 ; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0x40100000
588 define void @store_inline_imm_4.0_f64(double addrspace(1)* %out) {
589   store double 4.0, double addrspace(1)* %out
593 ; CHECK-LABEL: {{^}}store_inline_imm_m_4.0_f64:
594 ; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}}
595 ; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0xc0100000
597 define void @store_inline_imm_m_4.0_f64(double addrspace(1)* %out) {
598   store double -4.0, double addrspace(1)* %out
602 ; CHECK-LABEL: {{^}}store_literal_imm_f64:
603 ; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], 0{{$}}
604 ; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], 0x40b00000
606 define void @store_literal_imm_f64(double addrspace(1)* %out) {
607   store double 4096.0, double addrspace(1)* %out