Lines Matching +full:1 +full:- +full:9
1 ; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=GCN -chec…
2 ; XUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck -check-prefix=GCN -chec…
3 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s
9 ;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
10 ;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
13 ;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
14 ;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
17 ;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
18 ;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
20 define void @shl_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
21 %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
22 %a = load <2 x i32>, <2 x i32> addrspace(1) * %in
23 %b = load <2 x i32>, <2 x i32> addrspace(1) * %b_ptr
25 store <2 x i32> %result, <2 x i32> addrspace(1)* %out
30 ;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
31 ;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
32 ;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
33 ;EG: LSHL {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
36 ;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
37 ;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
38 ;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
39 ;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
42 ;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
43 ;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
44 ;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
45 ;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
47 define void @shl_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
48 %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
49 %a = load <4 x i32>, <4 x i32> addrspace(1) * %in
50 %b = load <4 x i32>, <4 x i32> addrspace(1) * %b_ptr
52 store <4 x i32> %result, <4 x i32> addrspace(1)* %out
56 ;EG-LABEL: {{^}}shl_i64:
57 ;EG: SUB_INT {{\*? *}}[[COMPSH:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHIFT:T[0-9]+\.[XYZW]]]
58 ;EG: LSHR {{\* *}}[[TEMP:T[0-9]+\.[XYZW]]], [[OPLO:T[0-9]+\.[XYZW]]], {{[[COMPSH]]|PV.[XYZW]}}
59 ;EG-DAG: ADD_INT {{\*? *}}[[BIGSH:T[0-9]+\.[XYZW]]], [[SHIFT]], literal
60 ;EG-DAG: LSHR {{\*? *}}[[OVERF:T[0-9]+\.[XYZW]]], {{[[TEMP]]|PV.[XYZW]}}, 1
61 ;EG-DAG: LSHL {{\*? *}}[[HISMTMP:T[0-9]+\.[XYZW]]], [[OPHI:T[0-9]+\.[XYZW]]], [[SHIFT]]
62 ;EG-DAG: OR_INT {{\*? *}}[[HISM:T[0-9]+\.[XYZW]]], {{[[HISMTMP]]|PV.[XYZW]|PS}}, {{[[OVERF]]|PV.[XY…
63 ;EG-DAG: LSHL {{\*? *}}[[LOSM:T[0-9]+\.[XYZW]]], [[OPLO]], {{PS|[[SHIFT]]|PV.[XYZW]}}
64 ;EG-DAG: SETGT_UINT {{\*? *}}[[RESC:T[0-9]+\.[XYZW]]], [[SHIFT]], literal
65 ;EG-DAG: CNDE_INT {{\*? *}}[[RESLO:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}}
66 ;EG-DAG: CNDE_INT {{\*? *}}[[RESHI:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW], .*}}, 0.0
69 ;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
72 ;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
74 define void @shl_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
75 %b_ptr = getelementptr i64, i64 addrspace(1)* %in, i64 1
76 %a = load i64, i64 addrspace(1) * %in
77 %b = load i64, i64 addrspace(1) * %b_ptr
79 store i64 %result, i64 addrspace(1)* %out
83 ;EG-LABEL: {{^}}shl_v2i64:
84 ;EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]]
85 ;EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]]
86 ;EG-DAG: LSHR {{\*? *}}[[COMPSHA]]
87 ;EG-DAG: LSHR {{\*? *}}[[COMPSHB]]
88 ;EG-DAG: LSHR {{.*}}, 1
89 ;EG-DAG: LSHR {{.*}}, 1
90 ;EG-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal
91 ;EG-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal
92 ;EG-DAG: LSHL {{.*}}, [[SHA]]
93 ;EG-DAG: LSHL {{.*}}, [[SHB]]
94 ;EG-DAG: LSHL {{.*}}, [[SHA]]
95 ;EG-DAG: LSHL {{.*}}, [[SHB]]
96 ;EG-DAG: LSHL
97 ;EG-DAG: LSHL
98 ;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal
99 ;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal
100 ;EG-DAG: CNDE_INT {{.*}}, 0.0
101 ;EG-DAG: CNDE_INT {{.*}}, 0.0
102 ;EG-DAG: CNDE_INT
103 ;EG-DAG: CNDE_INT
106 ;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
107 ;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
110 ;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
111 ;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
113 define void @shl_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) {
114 %b_ptr = getelementptr <2 x i64>, <2 x i64> addrspace(1)* %in, i64 1
115 %a = load <2 x i64>, <2 x i64> addrspace(1) * %in
116 %b = load <2 x i64>, <2 x i64> addrspace(1) * %b_ptr
118 store <2 x i64> %result, <2 x i64> addrspace(1)* %out
123 ;EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]]
124 ;EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]]
125 ;EG-DAG: SUB_INT {{\*? *}}[[COMPSHC:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHC:T[0-9]+\.[XYZW]]]
126 ;EG-DAG: SUB_INT {{\*? *}}[[COMPSHD:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHD:T[0-9]+\.[XYZW]]]
127 ;EG-DAG: LSHR {{\*? *}}[[COMPSHA]]
128 ;EG-DAG: LSHR {{\*? *}}[[COMPSHB]]
129 ;EG-DAG: LSHR {{\*? *}}[[COMPSHC]]
130 ;EG-DAG: LSHR {{\*? *}}[[COMPSHD]]
131 ;EG-DAG: LSHR {{.*}}, 1
132 ;EG-DAG: LSHR {{.*}}, 1
133 ;EG-DAG: LSHR {{.*}}, 1
134 ;EG-DAG: LSHR {{.*}}, 1
135 ;EG-DAG: ADD_INT {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal
136 ;EG-DAG: ADD_INT {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal
137 ;EG-DAG: ADD_INT {{\*? *}}[[BIGSHC:T[0-9]+\.[XYZW]]]{{.*}}, literal
138 ;EG-DAG: ADD_INT {{\*? *}}[[BIGSHD:T[0-9]+\.[XYZW]]]{{.*}}, literal
139 ;EG-DAG: LSHL {{.*}}, [[SHA]]
140 ;EG-DAG: LSHL {{.*}}, [[SHB]]
141 ;EG-DAG: LSHL {{.*}}, [[SHC]]
142 ;EG-DAG: LSHL {{.*}}, [[SHD]]
143 ;EG-DAG: LSHL {{.*}}, [[SHA]]
144 ;EG-DAG: LSHL {{.*}}, [[SHB]]
145 ;EG-DAG: LSHL {{.*}}, [[SHC]]
146 ;EG-DAG: LSHL {{.*}}, [[SHD]]
147 ;EG-DAG: LSHL
148 ;EG-DAG: LSHL
149 ;EG-DAG: LSHL
150 ;EG-DAG: LSHL
151 ;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal
152 ;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal
153 ;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHC]], literal
154 ;EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHD]], literal
155 ;EG-DAG: CNDE_INT {{.*}}, 0.0
156 ;EG-DAG: CNDE_INT {{.*}}, 0.0
157 ;EG-DAG: CNDE_INT {{.*}}, 0.0
158 ;EG-DAG: CNDE_INT {{.*}}, 0.0
159 ;EG-DAG: CNDE_INT
160 ;EG-DAG: CNDE_INT
161 ;EG-DAG: CNDE_INT
162 ;EG-DAG: CNDE_INT
165 ;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
166 ;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
167 ;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
168 ;SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
171 ;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
172 ;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
173 ;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
174 ;VI: v_lshlrev_b64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
176 define void @shl_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) {
177 %b_ptr = getelementptr <4 x i64>, <4 x i64> addrspace(1)* %in, i64 1
178 %a = load <4 x i64>, <4 x i64> addrspace(1) * %in
179 %b = load <4 x i64>, <4 x i64> addrspace(1) * %b_ptr
181 store <4 x i64> %result, <4 x i64> addrspace(1)* %out
186 ; GCN-LABEL: {{^}}s_shl_32_i64:
187 ; GCN-DAG: s_load_dword [[LO_A:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb{{$}}
188 ; GCN-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], 0{{$}}
189 ; GCN-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], [[LO_A]]
191 define void @s_shl_32_i64(i64 addrspace(1)* %out, i64 %a) {
193 store i64 %result, i64 addrspace(1)* %out
197 ; GCN-LABEL: {{^}}v_shl_32_i64:
198 ; GCN-DAG: buffer_load_dword v[[LO_A:[0-9]+]],
199 ; GCN-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], 0{{$}}
201 define void @v_shl_32_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
203 %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
204 %gep.out = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
205 %a = load i64, i64 addrspace(1)* %gep.in
207 store i64 %result, i64 addrspace(1)* %gep.out
211 ; FUNC-LABEL: {{^}}s_shl_constant_i64
212 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}
213 define void @s_shl_constant_i64(i64 addrspace(1)* %out, i64 %a) {
215 store i64 %shl, i64 addrspace(1)* %out, align 8
219 ; FUNC-LABEL: {{^}}v_shl_constant_i64:
220 ; SI-DAG: buffer_load_dword [[VAL:v[0-9]+]]
221 ; SI-DAG: s_mov_b32 s[[KLO:[0-9]+]], 0xab19b207
222 ; SI-DAG: s_movk_i32 s[[KHI:[0-9]+]], 0x11e{{$}}
223 ; SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\]}}, s{{\[}}[[KLO]]:[[KHI]]{{\]}}, [[VAL]]
225 define void @v_shl_constant_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
226 %a = load i64, i64 addrspace(1)* %aptr, align 8
228 store i64 %shl, i64 addrspace(1)* %out, align 8
232 ; FUNC-LABEL: {{^}}v_shl_i64_32_bit_constant:
233 ; SI-DAG: buffer_load_dword [[VAL:v[0-9]+]]
234 ; SI-DAG: s_mov_b32 s[[KLO:[0-9]+]], 0x12d687{{$}}
235 ; SI-DAG: s_mov_b32 s[[KHI:[0-9]+]], 0{{$}}
236 ; SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\]}}, s{{\[}}[[KLO]]:[[KHI]]{{\]}}, [[VAL]]
237 define void @v_shl_i64_32_bit_constant(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
238 %a = load i64, i64 addrspace(1)* %aptr, align 8
240 store i64 %shl, i64 addrspace(1)* %out, align 8
244 ; FUNC-LABEL: {{^}}v_shl_inline_imm_64_i64:
245 ; SI: v_lshl_b64 {{v\[[0-9]+:[0-9]+\]}}, 64, {{v[0-9]+}}
246 define void @v_shl_inline_imm_64_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
247 %a = load i64, i64 addrspace(1)* %aptr, align 8
249 store i64 %shl, i64 addrspace(1)* %out, align 8
253 ; FUNC-LABEL: {{^}}s_shl_inline_imm_64_i64:
254 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, 64, s{{[0-9]+}}
255 define void @s_shl_inline_imm_64_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
257 store i64 %shl, i64 addrspace(1)* %out, align 8
261 ; FUNC-LABEL: {{^}}s_shl_inline_imm_1_i64:
262 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, 1, s{{[0-9]+}}
263 define void @s_shl_inline_imm_1_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
264 %shl = shl i64 1, %a
265 store i64 %shl, i64 addrspace(1)* %out, align 8
269 ; FUNC-LABEL: {{^}}s_shl_inline_imm_1.0_i64:
270 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, 1.0, s{{[0-9]+}}
271 define void @s_shl_inline_imm_1.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
273 store i64 %shl, i64 addrspace(1)* %out, align 8
277 ; FUNC-LABEL: {{^}}s_shl_inline_imm_neg_1.0_i64:
278 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, -1.0, s{{[0-9]+}}
279 define void @s_shl_inline_imm_neg_1.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
281 store i64 %shl, i64 addrspace(1)* %out, align 8
285 ; FUNC-LABEL: {{^}}s_shl_inline_imm_0.5_i64:
286 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, 0.5, s{{[0-9]+}}
287 define void @s_shl_inline_imm_0.5_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
289 store i64 %shl, i64 addrspace(1)* %out, align 8
293 ; FUNC-LABEL: {{^}}s_shl_inline_imm_neg_0.5_i64:
294 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, -0.5, s{{[0-9]+}}
295 define void @s_shl_inline_imm_neg_0.5_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
297 store i64 %shl, i64 addrspace(1)* %out, align 8
301 ; FUNC-LABEL: {{^}}s_shl_inline_imm_2.0_i64:
302 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, 2.0, s{{[0-9]+}}
303 define void @s_shl_inline_imm_2.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
305 store i64 %shl, i64 addrspace(1)* %out, align 8
309 ; FUNC-LABEL: {{^}}s_shl_inline_imm_neg_2.0_i64:
310 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, -2.0, s{{[0-9]+}}
311 define void @s_shl_inline_imm_neg_2.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
313 store i64 %shl, i64 addrspace(1)* %out, align 8
317 ; FUNC-LABEL: {{^}}s_shl_inline_imm_4.0_i64:
318 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, 4.0, s{{[0-9]+}}
319 define void @s_shl_inline_imm_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
321 store i64 %shl, i64 addrspace(1)* %out, align 8
325 ; FUNC-LABEL: {{^}}s_shl_inline_imm_neg_4.0_i64:
326 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, -4.0, s{{[0-9]+}}
327 define void @s_shl_inline_imm_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
329 store i64 %shl, i64 addrspace(1)* %out, align 8
334 ; Test with the 64-bit integer bitpattern for a 32-bit float in the
335 ; low 32-bits, which is not a valid 64-bit inline immmediate.
337 ; FUNC-LABEL: {{^}}s_shl_inline_imm_f32_4.0_i64:
338 ; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 4.0
339 ; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 0{{$}}
340 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}}, s{{[0-9]+}}
341 define void @s_shl_inline_imm_f32_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
343 store i64 %shl, i64 addrspace(1)* %out, align 8
347 ; FIXME: Copy of -1 register
348 ; FUNC-LABEL: {{^}}s_shl_inline_imm_f32_neg_4.0_i64:
349 ; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], -4.0
350 ; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], -1{{$}}
351 ; SI-DAG: s_mov_b32 s[[K_HI_COPY:[0-9]+]], s[[K_HI]]
352 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI_COPY]]{{\]}}, s{{[0-9]+}}
353 define void @s_shl_inline_imm_f32_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 …
354 %shl = shl i64 -1065353216, %a
355 store i64 %shl, i64 addrspace(1)* %out, align 8
359 ; Shift into upper 32-bits
360 ; FUNC-LABEL: {{^}}s_shl_inline_high_imm_f32_4.0_i64:
361 ; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 4.0
362 ; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 0{{$}}
363 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}}, s{{[0-9]+}}
364 define void @s_shl_inline_high_imm_f32_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64…
366 store i64 %shl, i64 addrspace(1)* %out, align 8
370 ; FUNC-LABEL: {{^}}s_shl_inline_high_imm_f32_neg_4.0_i64:
371 ; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], -4.0
372 ; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 0{{$}}
373 ; SI: s_lshl_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}}, s{{[0-9]+}}
374 define void @s_shl_inline_high_imm_f32_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr,…
376 store i64 %shl, i64 addrspace(1)* %out, align 8