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1 ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -chec…
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -chec…
3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
5 declare i32 @llvm.r600.read.tidig.x() #0
7 ; FUNC-LABEL: {{^}}ashr_v2i32:
8 ; SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
9 ; SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
11 ; VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
12 ; VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
14 ; EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
15 ; EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
25 ; FUNC-LABEL: {{^}}ashr_v4i32:
26 ; SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
27 ; SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
28 ; SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
29 ; SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
31 ; VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
32 ; VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
33 ; VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
34 ; VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
36 ; EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
37 ; EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
38 ; EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
39 ; EG: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
49 ; FUNC-LABEL: {{^}}s_ashr_i64:
50 ; GCN: s_ashr_i64 s[{{[0-9]}}:{{[0-9]}}], s[{{[0-9]}}:{{[0-9]}}], 8
61 ; FUNC-LABEL: {{^}}ashr_i64_2:
62 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
64 ; VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
66 ; EG: SUB_INT {{\*? *}}[[COMPSH:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHIFT:T[0-9]+\.[XYZW]]]
67 ; EG: LSHL {{\* *}}[[TEMP:T[0-9]+\.[XYZW]]], [[OPHI:T[0-9]+\.[XYZW]]], {{[[COMPSH]]|PV.[XYZW]}}
68 ; EG-DAG: ADD_INT {{\*? *}}[[BIGSH:T[0-9]+\.[XYZW]]], [[SHIFT]], literal
69 ; EG-DAG: LSHL {{\*? *}}[[OVERF:T[0-9]+\.[XYZW]]], {{[[TEMP]]|PV.[XYZW]}}, 1
70 ; EG-DAG: LSHR {{\*? *}}[[LOSMTMP:T[0-9]+\.[XYZW]]], [[OPLO:T[0-9]+\.[XYZW]]], [[SHIFT]]
71 ; EG-DAG: OR_INT {{\*? *}}[[LOSM:T[0-9]+\.[XYZW]]], {{[[LOSMTMP]]|PV.[XYZW]|PS}}, {{[[OVERF]]|PV.[X…
72 ; EG-DAG: ASHR {{\*? *}}[[HISM:T[0-9]+\.[XYZW]]], [[OPHI]], {{PS|PV.[XYZW]|[[SHIFT]]}}
73 ; EG-DAG: ASHR {{\*? *}}[[LOBIG:T[0-9]+\.[XYZW]]], [[OPHI]], literal
74 ; EG-DAG: ASHR {{\*? *}}[[HIBIG:T[0-9]+\.[XYZW]]], [[OPHI]], literal
75 ; EG-DAG: SETGT_UINT {{\*? *}}[[RESC:T[0-9]+\.[XYZW]]], [[SHIFT]], literal
76 ; EG-DAG: CNDE_INT {{\*? *}}[[RESLO:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}}
77 ; EG-DAG: CNDE_INT {{\*? *}}[[RESHI:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW]}}
88 ; FUNC-LABEL: {{^}}ashr_v2i64:
89 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
90 ; VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
92 ; EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]]
93 ; EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]]
94 ; EG-DAG: LSHL {{\*? *}}[[COMPSHA]]
95 ; EG-DAG: LSHL {{\*? *}}[[COMPSHB]]
96 ; EG-DAG: LSHL {{.*}}, 1
97 ; EG-DAG: LSHL {{.*}}, 1
98 ; EG-DAG: ASHR {{.*}}, [[SHA]]
99 ; EG-DAG: ASHR {{.*}}, [[SHB]]
100 ; EG-DAG: LSHR {{.*}}, [[SHA]]
101 ; EG-DAG: LSHR {{.*}}, [[SHB]]
102 ; EG-DAG: OR_INT
103 ; EG-DAG: OR_INT
104 ; EG-DAG: ADD_INT  {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal
105 ; EG-DAG: ADD_INT  {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal
106 ; EG-DAG: ASHR
107 ; EG-DAG: ASHR
108 ; EG-DAG: ASHR {{.*}}, literal
109 ; EG-DAG: ASHR {{.*}}, literal
110 ; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal
111 ; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal
112 ; EG-DAG: CNDE_INT
113 ; EG-DAG: CNDE_INT
114 ; EG-DAG: CNDE_INT
115 ; EG-DAG: CNDE_INT
126 ; XFUNC-LABEL: {{^}}s_ashr_v2i64:
127 ; XGCN: s_ashr_i64 {{s\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], s[0-9]+}}
128 ; XGCN: s_ashr_i64 {{s\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], s[0-9]+}}
135 ; FUNC-LABEL: {{^}}ashr_v4i64:
136 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
137 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
138 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
139 ; SI: v_ashr_i64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v[0-9]+}}
141 ; VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
142 ; VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
143 ; VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
144 ; VI: v_ashrrev_i64 {{v\[[0-9]+:[0-9]+\], v[0-9]+, v\[[0-9]+:[0-9]+\]}}
146 ; EG-DAG: SUB_INT {{\*? *}}[[COMPSHA:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHA:T[0-9]+\.[XYZW]]]
147 ; EG-DAG: SUB_INT {{\*? *}}[[COMPSHB:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHB:T[0-9]+\.[XYZW]]]
148 ; EG-DAG: SUB_INT {{\*? *}}[[COMPSHC:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHC:T[0-9]+\.[XYZW]]]
149 ; EG-DAG: SUB_INT {{\*? *}}[[COMPSHD:T[0-9]+\.[XYZW]]], {{literal.[xy]}}, [[SHD:T[0-9]+\.[XYZW]]]
150 ; EG-DAG: LSHL {{\*? *}}[[COMPSHA]]
151 ; EG-DAG: LSHL {{\*? *}}[[COMPSHB]]
152 ; EG-DAG: LSHL {{\*? *}}[[COMPSHC]]
153 ; EG-DAG: LSHL {{\*? *}}[[COMPSHD]]
154 ; EG-DAG: LSHL {{.*}}, 1
155 ; EG-DAG: LSHL {{.*}}, 1
156 ; EG-DAG: LSHL {{.*}}, 1
157 ; EG-DAG: LSHL {{.*}}, 1
158 ; EG-DAG: ASHR {{.*}}, [[SHA]]
159 ; EG-DAG: ASHR {{.*}}, [[SHB]]
160 ; EG-DAG: ASHR {{.*}}, [[SHC]]
161 ; EG-DAG: ASHR {{.*}}, [[SHD]]
162 ; EG-DAG: LSHR {{.*}}, [[SHA]]
163 ; EG-DAG: LSHR {{.*}}, [[SHB]]
164 ; EG-DAG: LSHR {{.*}}, [[SHA]]
165 ; EG-DAG: LSHR {{.*}}, [[SHB]]
166 ; EG-DAG: OR_INT
167 ; EG-DAG: OR_INT
168 ; EG-DAG: OR_INT
169 ; EG-DAG: OR_INT
170 ; EG-DAG: ADD_INT  {{\*? *}}[[BIGSHA:T[0-9]+\.[XYZW]]]{{.*}}, literal
171 ; EG-DAG: ADD_INT  {{\*? *}}[[BIGSHB:T[0-9]+\.[XYZW]]]{{.*}}, literal
172 ; EG-DAG: ADD_INT  {{\*? *}}[[BIGSHC:T[0-9]+\.[XYZW]]]{{.*}}, literal
173 ; EG-DAG: ADD_INT  {{\*? *}}[[BIGSHD:T[0-9]+\.[XYZW]]]{{.*}}, literal
174 ; EG-DAG: ASHR
175 ; EG-DAG: ASHR
176 ; EG-DAG: ASHR
177 ; EG-DAG: ASHR
178 ; EG-DAG: ASHR {{.*}}, literal
179 ; EG-DAG: ASHR {{.*}}, literal
180 ; EG-DAG: ASHR {{.*}}, literal
181 ; EG-DAG: ASHR {{.*}}, literal
182 ; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHA]], literal
183 ; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHB]], literal
184 ; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHC]], literal
185 ; EG-DAG: SETGT_UINT {{\*? *T[0-9]\.[XYZW]}}, [[SHD]], literal
186 ; EG-DAG: CNDE_INT
187 ; EG-DAG: CNDE_INT
188 ; EG-DAG: CNDE_INT
189 ; EG-DAG: CNDE_INT
190 ; EG-DAG: CNDE_INT
191 ; EG-DAG: CNDE_INT
192 ; EG-DAG: CNDE_INT
193 ; EG-DAG: CNDE_INT
203 ; GCN-LABEL: {{^}}s_ashr_32_i64:
204 ; GCN: s_load_dword s[[HI:[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, {{0xc|0x30}}
205 ; GCN: s_ashr_i32 s[[SHIFT:[0-9]+]], s[[HI]], 31
206 ; GCN: s_add_u32 s{{[0-9]+}}, s[[HI]], s{{[0-9]+}}
207 ; GCN: s_addc_u32 s{{[0-9]+}}, s[[SHIFT]], s{{[0-9]+}}
215 ; GCN-LABEL: {{^}}v_ashr_32_i64:
216 ; SI: buffer_load_dword v[[HI:[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 of…
217 ; VI: flat_load_dword v[[HI:[0-9]+]]
218 ; GCN: v_ashrrev_i32_e32 v[[SHIFT:[0-9]+]], 31, v[[HI]]
221   %tid = call i32 @llvm.r600.read.tidig.x() #0
230 ; GCN-LABEL: {{^}}s_ashr_63_i64:
231 ; GCN: s_load_dword s[[HI:[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, {{0xc|0x30}}
232 ; GCN: s_ashr_i32 s[[SHIFT:[0-9]+]], s[[HI]], 31
233 ; GCN: s_add_u32 {{s[0-9]+}}, s[[SHIFT]], {{s[0-9]+}}
234 ; GCN: s_addc_u32 {{s[0-9]+}}, s[[SHIFT]], {{s[0-9]+}}
242 ; GCN-LABEL: {{^}}v_ashr_63_i64:
243 ; SI: buffer_load_dword v[[HI:[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 of…
244 ; VI: flat_load_dword v[[HI:[0-9]+]]
245 ; GCN: v_ashrrev_i32_e32 v[[SHIFT:[0-9]+]], 31, v[[HI]]
246 ; GCN: v_mov_b32_e32 v[[COPY:[0-9]+]], v[[SHIFT]]
249   %tid = call i32 @llvm.r600.read.tidig.x() #0
258 attributes #0 = { nounwind readnone }