peephole-align.ll - OpenGrok cross reference for /external/llvm/test/CodeGen/PowerPC/peephole-align.ll

Lines Matching full:toc
4 ; Test peephole optimization for medium code model (32-bit TOC offsets)
33 ; POWER7: addis [[REGSTRUCT:[0-9]+]], 2, b4v@toc@ha
34 ; POWER7-DAG: lbz [[REG0_0:[0-9]+]], b4v@toc@l([[REGSTRUCT]])
35 ; POWER7-DAG: lbz [[REG1_0:[0-9]+]], b4v@toc@l+1([[REGSTRUCT]])
36 ; POWER7-DAG: lbz [[REG2_0:[0-9]+]], b4v@toc@l+2([[REGSTRUCT]])
37 ; POWER7-DAG: lbz [[REG3_0:[0-9]+]], b4v@toc@l+3([[REGSTRUCT]])
42 ; POWER7-DAG: stb [[REG0_1]], b4v@toc@l([[REGSTRUCT]])
43 ; POWER7-DAG: stb [[REG1_1]], b4v@toc@l+1([[REGSTRUCT]])
44 ; POWER7-DAG: stb [[REG2_1]], b4v@toc@l+2([[REGSTRUCT]])
45 ; POWER7-DAG: stb [[REG3_1]], b4v@toc@l+3([[REGSTRUCT]])
47 ; POWER8: addis [[REGSTRUCT:[0-9]+]], 2, b4v@toc@ha
48 ; POWER8-NEXT: addi [[REGSTRUCT]], [[REGSTRUCT]], b4v@toc@l
79 ; POWER7: addis [[REGSTRUCT:[0-9]+]], 2, h2v@toc@ha
80 ; POWER7-DAG: lhz [[REG0_0:[0-9]+]], h2v@toc@l([[REGSTRUCT]])
81 ; POWER7-DAG: lhz [[REG1_0:[0-9]+]], h2v@toc@l+2([[REGSTRUCT]])
84 ; POWER7-DAG: sth [[REG0_1]], h2v@toc@l([[REGSTRUCT]])
85 ; POWER7-DAG: sth [[REG1_1]], h2v@toc@l+2([[REGSTRUCT]])
87 ; POWER8: addis [[REGSTRUCT:[0-9]+]], 2, h2v@toc@ha
88 ; POWER8-NEXT: addi [[REGSTRUCT]], [[REGSTRUCT]], h2v@toc@l
107 ; CHECK: addis [[REGSTRUCT:[0-9]+]], 2, h2v@toc@ha
108 ; CHECK-DAG: lhz [[REG0_0:[0-9]+]], h2v@toc@l([[REGSTRUCT]])
109 ; CHECK-DAG: lhz [[REG1_0:[0-9]+]], h2v@toc@l+2([[REGSTRUCT]])
112 ; CHECK-DAG: sth [[REG0_1]], h2v@toc@l([[REGSTRUCT]])
113 ; CHECK-DAG: sth [[REG1_1]], h2v@toc@l+2([[REGSTRUCT]])
126 ; POWER7: addis [[REGSTRUCT:[0-9]+]], 2, b8v@toc@ha
127 ; POWER7-DAG: lbz [[REG0_0:[0-9]+]], b8v@toc@l([[REGSTRUCT]])
128 ; POWER7-DAG: lbz [[REG1_0:[0-9]+]], b8v@toc@l+1([[REGSTRUCT]])
129 ; POWER7-DAG: lbz [[REG2_0:[0-9]+]], b8v@toc@l+2([[REGSTRUCT]])
130 ; POWER7-DAG: lbz [[REG3_0:[0-9]+]], b8v@toc@l+3([[REGSTRUCT]])
131 ; POWER7-DAG: lbz [[REG4_0:[0-9]+]], b8v@toc@l+4([[REGSTRUCT]])
132 ; POWER7-DAG: lbz [[REG5_0:[0-9]+]], b8v@toc@l+5([[REGSTRUCT]])
133 ; POWER7-DAG: lbz [[REG6_0:[0-9]+]], b8v@toc@l+6([[REGSTRUCT]])
134 ; POWER7-DAG: lbz [[REG7_0:[0-9]+]], b8v@toc@l+7([[REGSTRUCT]])
143 ; POWER7-DAG: stb [[REG0_1]], b8v@toc@l([[REGSTRUCT]])
144 ; POWER7-DAG: stb [[REG1_1]], b8v@toc@l+1([[REGSTRUCT]])
145 ; POWER7-DAG: stb [[REG2_1]], b8v@toc@l+2([[REGSTRUCT]])
146 ; POWER7-DAG: stb [[REG3_1]], b8v@toc@l+3([[REGSTRUCT]])
147 ; POWER7-DAG: stb [[REG4_1]], b8v@toc@l+4([[REGSTRUCT]])
148 ; POWER7-DAG: stb [[REG5_1]], b8v@toc@l+5([[REGSTRUCT]])
149 ; POWER7-DAG: stb [[REG6_1]], b8v@toc@l+6([[REGSTRUCT]])
150 ; POWER7-DAG: stb [[REG7_1]], b8v@toc@l+7([[REGSTRUCT]])
152 ; POWER8: addis [[REGSTRUCT:[0-9]+]], 2, b8v@toc@ha
153 ; POWER8-NEXT: addi [[REGSTRUCT]], [[REGSTRUCT]], b8v@toc@l
208 ; POWER7: addis [[REGSTRUCT:[0-9]+]], 2, h4v@toc@ha
209 ; POWER7-DAG: lhz [[REG0_0:[0-9]+]], h4v@toc@l([[REGSTRUCT]])
210 ; POWER7-DAG: lhz [[REG1_0:[0-9]+]], h4v@toc@l+2([[REGSTRUCT]])
211 ; POWER7-DAG: lhz [[REG2_0:[0-9]+]], h4v@toc@l+4([[REGSTRUCT]])
212 ; POWER7-DAG: lhz [[REG3_0:[0-9]+]], h4v@toc@l+6([[REGSTRUCT]])
217 ; POWER7-DAG: sth [[REG0_1]], h4v@toc@l([[REGSTRUCT]])
218 ; POWER7-DAG: sth [[REG1_1]], h4v@toc@l+2([[REGSTRUCT]])
219 ; POWER7-DAG: sth [[REG2_1]], h4v@toc@l+4([[REGSTRUCT]])
220 ; POWER7-DAG: sth [[REG3_1]], h4v@toc@l+6([[REGSTRUCT]])
222 ; POWER8: addis [[REGSTRUCT:[0-9]+]], 2, h4v@toc@ha
223 ; POWER8-NEXT: addi [[REGSTRUCT]], [[REGSTRUCT]], h4v@toc@l
254 ; POWER7: addis [[REGSTRUCT:[0-9]+]], 2, w2v@toc@ha
255 ; POWER7-DAG: lwz [[REG0_0:[0-9]+]], w2v@toc@l([[REGSTRUCT]])
256 ; POWER7-DAG: lwz [[REG1_0:[0-9]+]], w2v@toc@l+4([[REGSTRUCT]])
259 ; POWER7-DAG: stw [[REG0_1]], w2v@toc@l([[REGSTRUCT]])
260 ; POWER7-DAG: stw [[REG1_1]], w2v@toc@l+4([[REGSTRUCT]])
262 ; POWER8: addis [[REGSTRUCT:[0-9]+]], 2, w2v@toc@ha
263 ; POWER8-NEXT: addi [[REGSTRUCT]], [[REGSTRUCT]], w2v@toc@l
282 ; POWER7: addis [[REGSTRUCT:[0-9]+]], 2, d2v@toc@ha
283 ; POWER7-DAG: ld [[REG0_0:[0-9]+]], d2v@toc@l([[REGSTRUCT]])
284 ; POWER7-DAG: ld [[REG1_0:[0-9]+]], d2v@toc@l+8([[REGSTRUCT]])
287 ; POWER7-DAG: std [[REG0_1]], d2v@toc@l([[REGSTRUCT]])
288 ; POWER7-DAG: std [[REG1_1]], d2v@toc@l+8([[REGSTRUCT]])
290 ; POWER8: addis [[REGSTRUCT:[0-9]+]], 2, d2v@toc@ha
291 ; POWER8-NEXT: addi [[REGSTRUCT]], [[REGSTRUCT]], d2v@toc@l
313 ; CHECK: addis 3, 2, d2v@toc@ha
314 ; CHECK: ld 3, d2v@toc@l+8(3)
323 ; POWER7: addis [[REGSTRUCT_0:[0-9]+]], 2, misalign_v@toc@ha
324 ; POWER7: addi [[REGSTRUCT:[0-9]+]], [[REGSTRUCT_0]], misalign_v@toc@l