Lines Matching refs:cs
19 radv_cs_emit_write_event_eop(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, enum radv_queu… in radv_cs_emit_write_event_eop() argument
24 radeon_emit(cs, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, SDMA_FENCE_MTYPE_UC)); in radv_cs_emit_write_event_eop()
25 radeon_emit(cs, va); in radv_cs_emit_write_event_eop()
26 radeon_emit(cs, va >> 32); in radv_cs_emit_write_event_eop()
27 radeon_emit(cs, new_fence); in radv_cs_emit_write_event_eop()
48 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); in radv_cs_emit_write_event_eop()
49 radeon_emit(cs, EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1)); in radv_cs_emit_write_event_eop()
50 radeon_emit(cs, gfx9_eop_bug_va); in radv_cs_emit_write_event_eop()
51 radeon_emit(cs, gfx9_eop_bug_va >> 32); in radv_cs_emit_write_event_eop()
54 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, false)); in radv_cs_emit_write_event_eop()
55 radeon_emit(cs, op); in radv_cs_emit_write_event_eop()
56 radeon_emit(cs, sel); in radv_cs_emit_write_event_eop()
57 radeon_emit(cs, va); /* address lo */ in radv_cs_emit_write_event_eop()
58 radeon_emit(cs, va >> 32); /* address hi */ in radv_cs_emit_write_event_eop()
59 radeon_emit(cs, new_fence); /* immediate data lo */ in radv_cs_emit_write_event_eop()
60 radeon_emit(cs, 0); /* immediate data hi */ in radv_cs_emit_write_event_eop()
62 radeon_emit(cs, 0); /* unused */ in radv_cs_emit_write_event_eop()
73 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, 5, false)); in radv_cs_emit_write_event_eop()
74 radeon_emit(cs, op); in radv_cs_emit_write_event_eop()
75 radeon_emit(cs, sel); in radv_cs_emit_write_event_eop()
76 radeon_emit(cs, va); /* address lo */ in radv_cs_emit_write_event_eop()
77 radeon_emit(cs, va >> 32); /* address hi */ in radv_cs_emit_write_event_eop()
78 radeon_emit(cs, new_fence); /* immediate data lo */ in radv_cs_emit_write_event_eop()
79 radeon_emit(cs, 0); /* immediate data hi */ in radv_cs_emit_write_event_eop()
81 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOS, 3, false)); in radv_cs_emit_write_event_eop()
82 radeon_emit(cs, op); in radv_cs_emit_write_event_eop()
83 radeon_emit(cs, va); in radv_cs_emit_write_event_eop()
84 radeon_emit(cs, ((va >> 32) & 0xffff) | EOS_DATA_SEL(EOS_DATA_SEL_VALUE_32BIT)); in radv_cs_emit_write_event_eop()
85 radeon_emit(cs, new_fence); in radv_cs_emit_write_event_eop()
93 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false)); in radv_cs_emit_write_event_eop()
94 radeon_emit(cs, op); in radv_cs_emit_write_event_eop()
95 radeon_emit(cs, va); in radv_cs_emit_write_event_eop()
96 radeon_emit(cs, ((va >> 32) & 0xffff) | sel); in radv_cs_emit_write_event_eop()
97 radeon_emit(cs, 0); /* immediate data */ in radv_cs_emit_write_event_eop()
98 radeon_emit(cs, 0); /* unused */ in radv_cs_emit_write_event_eop()
101 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, false)); in radv_cs_emit_write_event_eop()
102 radeon_emit(cs, op); in radv_cs_emit_write_event_eop()
103 radeon_emit(cs, va); in radv_cs_emit_write_event_eop()
104 radeon_emit(cs, ((va >> 32) & 0xffff) | sel); in radv_cs_emit_write_event_eop()
105 radeon_emit(cs, new_fence); /* immediate data */ in radv_cs_emit_write_event_eop()
106 radeon_emit(cs, 0); /* unused */ in radv_cs_emit_write_event_eop()
112 radv_emit_acquire_mem(struct radeon_cmdbuf *cs, bool is_mec, bool is_gfx9, unsigned cp_coher_cntl) in radv_emit_acquire_mem() argument
116 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, false) | PKT3_SHADER_TYPE_S(is_mec)); in radv_emit_acquire_mem()
117 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */ in radv_emit_acquire_mem()
118 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */ in radv_emit_acquire_mem()
119 radeon_emit(cs, hi_val); /* CP_COHER_SIZE_HI */ in radv_emit_acquire_mem()
120 radeon_emit(cs, 0); /* CP_COHER_BASE */ in radv_emit_acquire_mem()
121 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */ in radv_emit_acquire_mem()
122 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */ in radv_emit_acquire_mem()
125 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, false)); in radv_emit_acquire_mem()
126 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */ in radv_emit_acquire_mem()
127 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */ in radv_emit_acquire_mem()
128 radeon_emit(cs, 0); /* CP_COHER_BASE */ in radv_emit_acquire_mem()
129 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */ in radv_emit_acquire_mem()
134 gfx10_cs_emit_cache_flush(struct radeon_cmdbuf *cs, enum amd_gfx_level gfx_level, uint32_t *flush_c… in gfx10_cs_emit_cache_flush() argument
184 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in gfx10_cs_emit_cache_flush()
185 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0)); in gfx10_cs_emit_cache_flush()
194 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in gfx10_cs_emit_cache_flush()
195 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0)); in gfx10_cs_emit_cache_flush()
220 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in gfx10_cs_emit_cache_flush()
221 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4)); in gfx10_cs_emit_cache_flush()
225 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in gfx10_cs_emit_cache_flush()
226 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4)); in gfx10_cs_emit_cache_flush()
233 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in gfx10_cs_emit_cache_flush()
234 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4))); in gfx10_cs_emit_cache_flush()
259 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, 6, 0)); in gfx10_cs_emit_cache_flush()
260 … radeon_emit(cs, S_490_EVENT_TYPE(cb_db_event) | S_490_EVENT_INDEX(5) | S_490_GLM_WB(glm_wb) | in gfx10_cs_emit_cache_flush()
264 radeon_emit(cs, 0); /* DST_SEL, INT_SEL, DATA_SEL */ in gfx10_cs_emit_cache_flush()
265 radeon_emit(cs, 0); /* ADDRESS_LO */ in gfx10_cs_emit_cache_flush()
266 radeon_emit(cs, 0); /* ADDRESS_HI */ in gfx10_cs_emit_cache_flush()
267 radeon_emit(cs, 0); /* DATA_LO */ in gfx10_cs_emit_cache_flush()
268 radeon_emit(cs, 0); /* DATA_HI */ in gfx10_cs_emit_cache_flush()
269 radeon_emit(cs, 0); /* INT_CTXID */ in gfx10_cs_emit_cache_flush()
272 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 6, 0)); in gfx10_cs_emit_cache_flush()
273 … radeon_emit(cs, S_580_PWS_STAGE_SEL(V_580_CP_PFP) | S_580_PWS_COUNTER_SEL(V_580_TS_SELECT) | in gfx10_cs_emit_cache_flush()
275 radeon_emit(cs, 0xffffffff); /* GCR_SIZE */ in gfx10_cs_emit_cache_flush()
276 radeon_emit(cs, 0x01ffffff); /* GCR_SIZE_HI */ in gfx10_cs_emit_cache_flush()
277 radeon_emit(cs, 0); /* GCR_BASE_LO */ in gfx10_cs_emit_cache_flush()
278 radeon_emit(cs, 0); /* GCR_BASE_HI */ in gfx10_cs_emit_cache_flush()
279 radeon_emit(cs, S_585_PWS_ENA(1)); in gfx10_cs_emit_cache_flush()
280 radeon_emit(cs, gcr_cntl); /* GCR_CNTL */ in gfx10_cs_emit_cache_flush()
310 radv_cs_emit_write_event_eop(cs, gfx_level, qf, cb_db_event, in gfx10_cs_emit_cache_flush()
316 radv_cp_wait_mem(cs, qf, WAIT_REG_MEM_EQUAL, flush_va, *flush_cnt, 0xffffffff); in gfx10_cs_emit_cache_flush()
322 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in gfx10_cs_emit_cache_flush()
323 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0)); in gfx10_cs_emit_cache_flush()
332 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 6, 0)); in gfx10_cs_emit_cache_flush()
333 radeon_emit(cs, 0); /* CP_COHER_CNTL */ in gfx10_cs_emit_cache_flush()
334 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */ in gfx10_cs_emit_cache_flush()
335 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */ in gfx10_cs_emit_cache_flush()
336 radeon_emit(cs, 0); /* CP_COHER_BASE */ in gfx10_cs_emit_cache_flush()
337 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */ in gfx10_cs_emit_cache_flush()
338 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */ in gfx10_cs_emit_cache_flush()
339 radeon_emit(cs, gcr_cntl); /* GCR_CNTL */ in gfx10_cs_emit_cache_flush()
344 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0)); in gfx10_cs_emit_cache_flush()
345 radeon_emit(cs, 0); in gfx10_cs_emit_cache_flush()
352 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in gfx10_cs_emit_cache_flush()
353 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) | EVENT_INDEX(0)); in gfx10_cs_emit_cache_flush()
355 … radeon_set_sh_reg(cs, R_00B828_COMPUTE_PIPELINESTAT_ENABLE, S_00B828_PIPELINESTAT_ENABLE(1)); in gfx10_cs_emit_cache_flush()
359 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in gfx10_cs_emit_cache_flush()
360 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) | EVENT_INDEX(0)); in gfx10_cs_emit_cache_flush()
362 … radeon_set_sh_reg(cs, R_00B828_COMPUTE_PIPELINESTAT_ENABLE, S_00B828_PIPELINESTAT_ENABLE(0)); in gfx10_cs_emit_cache_flush()
368 radv_cs_emit_cache_flush(struct radeon_winsys *ws, struct radeon_cmdbuf *cs, enum amd_gfx_level gfx… in radv_cs_emit_cache_flush() argument
376 radeon_check_space(ws, cs, 128); in radv_cs_emit_cache_flush()
380 …gfx10_cs_emit_cache_flush(cs, gfx_level, flush_cnt, flush_va, qf, flush_bits, sqtt_flush_bits, gfx… in radv_cs_emit_cache_flush()
404 …radv_cs_emit_write_event_eop(cs, gfx_level, is_mec, V_028A90_FLUSH_AND_INV_CB_DATA_TS, 0, EOP_DST_… in radv_cs_emit_cache_flush()
418 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in radv_cs_emit_cache_flush()
419 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0)); in radv_cs_emit_cache_flush()
425 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in radv_cs_emit_cache_flush()
426 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0)); in radv_cs_emit_cache_flush()
432 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in radv_cs_emit_cache_flush()
433 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4)); in radv_cs_emit_cache_flush()
437 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in radv_cs_emit_cache_flush()
438 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4)); in radv_cs_emit_cache_flush()
444 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in radv_cs_emit_cache_flush()
445 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4)); in radv_cs_emit_cache_flush()
486 radv_cs_emit_write_event_eop(cs, gfx_level, false, cb_db_event, tc_flags, EOP_DST_SEL_MEM, in radv_cs_emit_cache_flush()
488 radv_cp_wait_mem(cs, qf, WAIT_REG_MEM_EQUAL, flush_va, *flush_cnt, 0xffffffff); in radv_cs_emit_cache_flush()
493 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in radv_cs_emit_cache_flush()
494 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0)); in radv_cs_emit_cache_flush()
499 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in radv_cs_emit_cache_flush()
500 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0)); in radv_cs_emit_cache_flush()
509 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0)); in radv_cs_emit_cache_flush()
510 radeon_emit(cs, 0); in radv_cs_emit_cache_flush()
516 radv_emit_acquire_mem(cs, is_mec, gfx_level == GFX9, in radv_cs_emit_cache_flush()
530 radv_emit_acquire_mem(cs, is_mec, gfx_level == GFX9, in radv_cs_emit_cache_flush()
537 … radv_emit_acquire_mem(cs, is_mec, gfx_level == GFX9, cp_coher_cntl | S_0085F0_TCL1_ACTION_ENA(1)); in radv_cs_emit_cache_flush()
548 radv_emit_acquire_mem(cs, is_mec, gfx_level == GFX9, cp_coher_cntl); in radv_cs_emit_cache_flush()
552 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in radv_cs_emit_cache_flush()
553 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) | EVENT_INDEX(0)); in radv_cs_emit_cache_flush()
555 … radeon_set_sh_reg(cs, R_00B828_COMPUTE_PIPELINESTAT_ENABLE, S_00B828_PIPELINESTAT_ENABLE(1)); in radv_cs_emit_cache_flush()
559 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); in radv_cs_emit_cache_flush()
560 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) | EVENT_INDEX(0)); in radv_cs_emit_cache_flush()
562 … radeon_set_sh_reg(cs, R_00B828_COMPUTE_PIPELINESTAT_ENABLE, S_00B828_PIPELINESTAT_ENABLE(0)); in radv_cs_emit_cache_flush()
568 radv_emit_cond_exec(const struct radv_device *device, struct radeon_cmdbuf *cs, uint64_t va, uint32… in radv_emit_cond_exec() argument
574 radeon_emit(cs, PKT3(PKT3_COND_EXEC, 3, 0)); in radv_emit_cond_exec()
575 radeon_emit(cs, va); in radv_emit_cond_exec()
576 radeon_emit(cs, va >> 32); in radv_emit_cond_exec()
577 radeon_emit(cs, 0); in radv_emit_cond_exec()
578 radeon_emit(cs, count); in radv_emit_cond_exec()
580 radeon_emit(cs, PKT3(PKT3_COND_EXEC, 2, 0)); in radv_emit_cond_exec()
581 radeon_emit(cs, va); in radv_emit_cond_exec()
582 radeon_emit(cs, va >> 32); in radv_emit_cond_exec()
583 radeon_emit(cs, count); in radv_emit_cond_exec()
588 radv_cs_write_data_imm(struct radeon_cmdbuf *cs, unsigned engine_sel, uint64_t va, uint32_t imm) in radv_cs_write_data_imm() argument
590 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0)); in radv_cs_write_data_imm()
591 radeon_emit(cs, S_370_DST_SEL(V_370_MEM) | S_370_WR_CONFIRM(1) | S_370_ENGINE_SEL(engine_sel)); in radv_cs_write_data_imm()
592 radeon_emit(cs, va); in radv_cs_write_data_imm()
593 radeon_emit(cs, va >> 32); in radv_cs_write_data_imm()
594 radeon_emit(cs, imm); in radv_cs_write_data_imm()