Lines Matching full:info
18 mark_sampler_desc(const nir_variable *var, struct radv_shader_info *info) in mark_sampler_desc() argument
20 info->desc_set_used_mask |= (1u << var->data.descriptor_set); in mark_sampler_desc()
27 return gfx_state->vs.has_prolog && nir->info.inputs_read; in radv_use_vs_prolog()
39 …input_info(const nir_shader *nir, const nir_intrinsic_instr *intrin, struct radv_shader_info *info, in gather_load_vs_input_info() argument
53 info->vs.needs_instance_id = true; in gather_load_vs_input_info()
54 info->vs.needs_base_instance = true; in gather_load_vs_input_info()
58 info->vs.vb_desc_usage_mask |= BITFIELD_BIT(generic_loc); in gather_load_vs_input_info()
60 … info->vs.vb_desc_usage_mask |= BITFIELD_BIT(gfx_state->vi.vertex_attribute_bindings[generic_loc]); in gather_load_vs_input_info()
62 info->vs.input_slot_usage_mask |= BITFIELD_RANGE(generic_loc, io_sem.num_slots); in gather_load_vs_input_info()
67 …input_info(const nir_shader *nir, const nir_intrinsic_instr *intrin, struct radv_shader_info *info, in gather_load_fs_input_info() argument
78 info->ps.input_clips_culls_mask |= BITFIELD_RANGE(component, intrin->num_components); in gather_load_fs_input_info()
81 info->ps.input_clips_culls_mask |= BITFIELD_RANGE(component, intrin->num_components) << 4; in gather_load_fs_input_info()
88 const bool per_primitive = nir->info.per_primitive_inputs & BITFIELD64_BIT(location); in gather_load_fs_input_info()
93 info->ps.explicit_strict_shaded_mask |= mapped_mask; in gather_load_fs_input_info()
95 info->ps.explicit_shaded_mask |= mapped_mask; in gather_load_fs_input_info()
98 info->ps.float16_hi_shaded_mask |= mapped_mask; in gather_load_fs_input_info()
100 info->ps.float16_shaded_mask |= mapped_mask; in gather_load_fs_input_info()
102 info->ps.float32_shaded_mask |= mapped_mask; in gather_load_fs_input_info()
110 info->ps.input_per_primitive_mask |= var_mask; in gather_load_fs_input_info()
112 info->ps.input_mask |= var_mask; in gather_load_fs_input_info()
117 …_input_info(const nir_shader *nir, const nir_intrinsic_instr *instr, struct radv_shader_info *info, in gather_intrinsic_load_input_info() argument
121 switch (nir->info.stage) { in gather_intrinsic_load_input_info()
123 gather_load_vs_input_info(nir, instr, info, gfx_state, stage_key); in gather_intrinsic_load_input_info()
126 gather_load_fs_input_info(nir, instr, info, gfx_state); in gather_intrinsic_load_input_info()
135 struct radv_shader_info *info, bool consider_force_vrs) in gather_intrinsic_store_output_info() argument
144 switch (nir->info.stage) { in gather_intrinsic_store_output_info()
146 output_usage_mask = info->vs.output_usage_mask; in gather_intrinsic_store_output_info()
149 output_usage_mask = info->tes.output_usage_mask; in gather_intrinsic_store_output_info()
152 output_usage_mask = info->gs.output_usage_mask; in gather_intrinsic_store_output_info()
157 info->ps.colors_written |= 0xfu << (4 * (fs_semantic - FRAG_RESULT_DATA0)); in gather_intrinsic_store_output_info()
160 info->ps.color0_written = write_mask; in gather_intrinsic_store_output_info()
182 info->force_vrs_per_vertex = true; in gather_intrinsic_store_output_info()
186 if (nir->info.stage == MESA_SHADER_GEOMETRY) { in gather_intrinsic_store_output_info()
188 info->gs.output_streams[location] |= gs_streams << (component * 2); in gather_intrinsic_store_output_info()
193 unsigned clip_array_mask = BITFIELD_MASK(nir->info.clip_distance_array_size); in gather_intrinsic_store_output_info()
194 info->outinfo.clip_dist_mask |= (write_mask << base) & clip_array_mask; in gather_intrinsic_store_output_info()
195 info->outinfo.cull_dist_mask |= (write_mask << base) & ~clip_array_mask; in gather_intrinsic_store_output_info()
200 …nstant_info(const nir_shader *nir, const nir_intrinsic_instr *instr, struct radv_shader_info *info) in gather_push_constant_info() argument
202 info->loads_push_constants = true; in gather_push_constant_info()
209 info->inline_push_constant_mask |= u_bit_consecutive64(start, size); in gather_push_constant_info()
214 info->can_inline_all_push_constants = false; in gather_push_constant_info()
218 …rinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr, struct radv_shader_info *info, in gather_intrinsic_info() argument
235 info->ps.reads_persp_center = true; in gather_intrinsic_info()
237 info->ps.reads_persp_centroid = true; in gather_intrinsic_info()
239 info->ps.reads_persp_sample = true; in gather_intrinsic_info()
245 info->ps.reads_linear_center = true; in gather_intrinsic_info()
247 info->ps.reads_linear_centroid = true; in gather_intrinsic_info()
249 info->ps.reads_linear_sample = true; in gather_intrinsic_info()
255 info->ps.needs_sample_positions = true; in gather_intrinsic_info()
259 info->ps.load_provoking_vtx = true; in gather_intrinsic_info()
262 info->ps.needs_sample_positions = true; in gather_intrinsic_info()
265 info->ps.load_rasterization_prim = true; in gather_intrinsic_info()
274 info->cs.uses_block_id[i] = true; in gather_intrinsic_info()
276 info->cs.uses_thread_id[i] = true; in gather_intrinsic_info()
281 info->ps.reads_pixel_coord = true; in gather_intrinsic_info()
284 info->ps.reads_frag_coord_mask |= nir_def_components_read(&instr->def); in gather_intrinsic_info()
287 info->ps.reads_sample_pos_mask |= nir_def_components_read(&instr->def); in gather_intrinsic_info()
290 gather_push_constant_info(nir, instr, info); in gather_intrinsic_info()
293 info->desc_set_used_mask |= (1u << nir_intrinsic_desc_set(instr)); in gather_intrinsic_info()
303 mark_sampler_desc(var, info); in gather_intrinsic_info()
310 gather_intrinsic_load_input_info(nir, instr, info, gfx_state, stage_key); in gather_intrinsic_info()
314 gather_intrinsic_store_output_info(nir, instr, info, consider_force_vrs); in gather_intrinsic_info()
317 info->cs.uses_rt = true; in gather_intrinsic_info()
320 info->ps.needs_poly_line_smooth = true; in gather_intrinsic_info()
323 info->ps.pops = true; in gather_intrinsic_info()
331 gather_tex_info(const nir_shader *nir, const nir_tex_instr *instr, struct radv_shader_info *info) in gather_tex_info() argument
336 mark_sampler_desc(nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src)), info); in gather_tex_info()
339 mark_sampler_desc(nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src)), info); in gather_tex_info()
348 gather_info_block(const nir_shader *nir, const nir_block *block, struct radv_shader_info *info, in gather_info_block() argument
355 …gather_intrinsic_info(nir, nir_instr_as_intrinsic(instr), info, gfx_state, stage_key, consider_for… in gather_info_block()
358 gather_tex_info(nir, nir_instr_as_tex(instr), info); in gather_info_block()
367 gather_xfb_info(const nir_shader *nir, struct radv_shader_info *info) in gather_xfb_info() argument
369 struct radv_streamout_info *so = &info->so; in gather_xfb_info()
417 *per_prim_mask = nir->info.outputs_written & nir->info.per_primitive_outputs & ~special_mask; in radv_get_output_masks()
418 *per_vtx_mask = nir->info.outputs_written & ~nir->info.per_primitive_outputs & ~special_mask; in radv_get_output_masks()
421 if (nir->info.stage == MESA_SHADER_MESH && gfx_state->has_multiview_view_index) in radv_get_output_masks()
427 … const struct radv_graphics_state_key *gfx_state, struct radv_shader_info *info, in radv_set_vs_output_param() argument
431 struct radv_vs_output_info *outinfo = &info->outinfo; in radv_set_vs_output_param()
442 …export_prim_id && info->is_ngg && pdev->info.gfx_level >= GFX10_3 && nir->info.stage == MESA_SHADE… in radv_set_vs_output_param()
445 (nir->info.stage == MESA_SHADER_VERTEX || nir->info.stage == MESA_SHADER_TESS_EVAL); in radv_set_vs_output_param()
461 if (nir->info.outputs_written & VARYING_BIT_CLIP_DIST0) in radv_set_vs_output_param()
463 if (nir->info.outputs_written & VARYING_BIT_CLIP_DIST1) in radv_set_vs_output_param()
472 const unsigned extra_offset = !!(total_param_exports == 0 && pdev->info.gfx_level >= GFX11); in radv_set_vs_output_param()
489 …t_wave_size(struct radv_device *device, gl_shader_stage stage, const struct radv_shader_info *info, in radv_get_wave_size() argument
497 if (stage == MESA_SHADER_GEOMETRY && !info->is_ngg) in radv_get_wave_size()
500 return info->wave_size; in radv_get_wave_size()
510 …ot_bit_size(struct radv_device *device, gl_shader_stage stage, const struct radv_shader_info *info, in radv_get_ballot_bit_size() argument
530 if (pdev->info.gfx_level >= GFX9 && esgs_itemsize) in radv_compute_esgs_itemsize()
537 gather_shader_info_ngg_query(struct radv_device *device, struct radv_shader_info *info) in gather_shader_info_ngg_query() argument
541 …info->gs.has_pipeline_stat_query = pdev->emulate_ngg_gs_query_pipeline_stat && info->stage == MESA… in gather_shader_info_ngg_query()
542 info->has_xfb_query = info->so.num_outputs > 0; in gather_shader_info_ngg_query()
543 info->has_prim_query = device->cache_key.primitives_generated_query || info->has_xfb_query; in gather_shader_info_ngg_query()
583 struct radv_shader_info *info) in gather_shader_info_vs() argument
586 info->vs.has_prolog = true; in gather_shader_info_vs()
587 info->vs.dynamic_inputs = true; in gather_shader_info_vs()
590 info->gs_inputs_read = ~0ULL; in gather_shader_info_vs()
591 info->vs.tcs_inputs_via_lds = ~0ULL; in gather_shader_info_vs()
594 info->vs.use_per_attribute_vb_descs = radv_use_per_attribute_vb_descs(nir, gfx_state, stage_key); in gather_shader_info_vs()
599 info->vs.needs_instance_id |= info->vs.has_prolog; in gather_shader_info_vs()
600 info->vs.needs_base_instance |= info->vs.has_prolog; in gather_shader_info_vs()
601 info->vs.needs_draw_id |= info->vs.has_prolog; in gather_shader_info_vs()
603 if (info->vs.dynamic_inputs) in gather_shader_info_vs()
604 info->vs.vb_desc_usage_mask = BITFIELD_MASK(util_last_bit(info->vs.vb_desc_usage_mask)); in gather_shader_info_vs()
610 …info->vs.dynamic_num_verts_per_prim = gfx_state->ia.topology == V_008958_DI_PT_NONE && info->is_ng… in gather_shader_info_vs()
612 if (!info->outputs_linked) in gather_shader_info_vs()
613 …info->vs.num_linked_outputs = util_last_bit64(radv_gather_unlinked_io_mask(nir->info.outputs_writt… in gather_shader_info_vs()
615 if (info->next_stage == MESA_SHADER_TESS_CTRL) { in gather_shader_info_vs()
616 info->vs.as_ls = true; in gather_shader_info_vs()
617 } else if (info->next_stage == MESA_SHADER_GEOMETRY) { in gather_shader_info_vs()
618 info->vs.as_es = true; in gather_shader_info_vs()
619 info->esgs_itemsize = radv_compute_esgs_itemsize(device, info->vs.num_linked_outputs); in gather_shader_info_vs()
622 if (info->is_ngg) { in gather_shader_info_vs()
623 info->vs.num_outputs = nir->num_outputs; in gather_shader_info_vs()
625 if (info->next_stage == MESA_SHADER_FRAGMENT || info->next_stage == MESA_SHADER_NONE) { in gather_shader_info_vs()
626 gather_shader_info_ngg_query(device, info); in gather_shader_info_vs()
633 … const struct radv_graphics_state_key *gfx_state, struct radv_shader_info *info) in gather_shader_info_tcs() argument
637 … nir_gather_tcs_info(nir, &info->tcs.info, nir->info.tess._primitive_mode, nir->info.tess.spacing); in gather_shader_info_tcs()
639 info->tcs.tcs_outputs_read = nir->info.outputs_read; in gather_shader_info_tcs()
640 info->tcs.tcs_outputs_written = nir->info.outputs_written; in gather_shader_info_tcs()
641 info->tcs.tcs_patch_outputs_read = nir->info.patch_inputs_read; in gather_shader_info_tcs()
642 info->tcs.tcs_patch_outputs_written = nir->info.patch_outputs_written; in gather_shader_info_tcs()
643 info->tcs.tcs_vertices_out = nir->info.tess.tcs_vertices_out; in gather_shader_info_tcs()
644 info->tcs.tes_inputs_read = ~0ULL; in gather_shader_info_tcs()
645 info->tcs.tes_patch_inputs_read = ~0ULL; in gather_shader_info_tcs()
647 if (!info->inputs_linked) in gather_shader_info_tcs()
648 …info->tcs.num_linked_inputs = util_last_bit64(radv_gather_unlinked_io_mask(nir->info.inputs_read)); in gather_shader_info_tcs()
649 if (!info->outputs_linked) { in gather_shader_info_tcs()
650 info->tcs.num_linked_outputs = util_last_bit64(radv_gather_unlinked_io_mask( in gather_shader_info_tcs()
651 … nir->info.outputs_written & ~(VARYING_BIT_TESS_LEVEL_OUTER | VARYING_BIT_TESS_LEVEL_INNER))); in gather_shader_info_tcs()
652 info->tcs.num_linked_patch_outputs = util_last_bit64( in gather_shader_info_tcs()
653 … radv_gather_unlinked_patch_io_mask(nir->info.outputs_written, nir->info.patch_outputs_written)); in gather_shader_info_tcs()
658 radv_get_tess_wg_info(pdev, &nir->info, gfx_state->ts.patch_control_points, in gather_shader_info_tcs()
660 info->tcs.num_linked_inputs, info->tcs.num_linked_outputs, in gather_shader_info_tcs()
661 … info->tcs.num_linked_patch_outputs, info->tcs.info.all_invocations_define_tess_levels, in gather_shader_info_tcs()
662 &info->num_tess_patches, &info->tcs.num_lds_blocks); in gather_shader_info_tcs()
667 …r_shader_info_tes(struct radv_device *device, const nir_shader *nir, struct radv_shader_info *info) in gather_shader_info_tes() argument
669 info->gs_inputs_read = ~0ULL; in gather_shader_info_tes()
670 info->tes._primitive_mode = nir->info.tess._primitive_mode; in gather_shader_info_tes()
671 info->tes.spacing = nir->info.tess.spacing; in gather_shader_info_tes()
672 info->tes.ccw = nir->info.tess.ccw; in gather_shader_info_tes()
673 info->tes.point_mode = nir->info.tess.point_mode; in gather_shader_info_tes()
674 info->tes.tcs_vertices_out = nir->info.tess.tcs_vertices_out; in gather_shader_info_tes()
675 info->tes.reads_tess_factors = in gather_shader_info_tes()
676 !!(nir->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER)); in gather_shader_info_tes()
678 if (!info->inputs_linked) { in gather_shader_info_tes()
679 info->tes.num_linked_inputs = util_last_bit64(radv_gather_unlinked_io_mask( in gather_shader_info_tes()
680 nir->info.inputs_read & ~(VARYING_BIT_TESS_LEVEL_OUTER | VARYING_BIT_TESS_LEVEL_INNER))); in gather_shader_info_tes()
681 info->tes.num_linked_patch_inputs = util_last_bit64( in gather_shader_info_tes()
682 radv_gather_unlinked_patch_io_mask(nir->info.inputs_read, nir->info.patch_inputs_read)); in gather_shader_info_tes()
684 if (!info->outputs_linked) in gather_shader_info_tes()
685 …info->tes.num_linked_outputs = util_last_bit64(radv_gather_unlinked_io_mask(nir->info.outputs_writ… in gather_shader_info_tes()
687 if (info->next_stage == MESA_SHADER_GEOMETRY) { in gather_shader_info_tes()
688 info->tes.as_es = true; in gather_shader_info_tes()
689 info->esgs_itemsize = radv_compute_esgs_itemsize(device, info->tes.num_linked_outputs); in gather_shader_info_tes()
692 if (info->is_ngg) { in gather_shader_info_tes()
693 info->tes.num_outputs = nir->num_outputs; in gather_shader_info_tes()
695 if (info->next_stage == MESA_SHADER_FRAGMENT || info->next_stage == MESA_SHADER_NONE) { in gather_shader_info_tes()
696 gather_shader_info_ngg_query(device, info); in gather_shader_info_tes()
706 unsigned num_se = pdev->info.max_se; in radv_init_legacy_gs_ring_info()
712 unsigned gs_vertex_reuse = (pdev->info.gfx_level >= GFX8 ? 32 : 16) * num_se; in radv_init_legacy_gs_ring_info()
727 if (pdev->info.gfx_level <= GFX8) in radv_init_legacy_gs_ring_info()
821 const uint32_t lds_granularity = pdev->info.lds_encode_granularity; in radv_get_legacy_gs_info()
835 …er_shader_info_gs(struct radv_device *device, const nir_shader *nir, struct radv_shader_info *info) in gather_shader_info_gs() argument
837 unsigned add_clip = nir->info.clip_distance_array_size + nir->info.cull_distance_array_size > 4; in gather_shader_info_gs()
838 info->gs.gsvs_vertex_size = (util_bitcount64(nir->info.outputs_written) + add_clip) * 16; in gather_shader_info_gs()
839 info->gs.max_gsvs_emit_size = info->gs.gsvs_vertex_size * nir->info.gs.vertices_out; in gather_shader_info_gs()
841 info->gs.vertices_in = nir->info.gs.vertices_in; in gather_shader_info_gs()
842 info->gs.vertices_out = nir->info.gs.vertices_out; in gather_shader_info_gs()
843 info->gs.input_prim = nir->info.gs.input_primitive; in gather_shader_info_gs()
844 info->gs.output_prim = nir->info.gs.output_primitive; in gather_shader_info_gs()
845 info->gs.invocations = nir->info.gs.invocations; in gather_shader_info_gs()
846 …info->gs.max_stream = nir->info.gs.active_stream_mask ? util_last_bit(nir->info.gs.active_stream_m… in gather_shader_info_gs()
849 const uint8_t usage_mask = info->gs.output_usage_mask[slot]; in gather_shader_info_gs()
850 const uint8_t gs_streams = info->gs.output_streams[slot]; in gather_shader_info_gs()
857 info->gs.num_stream_output_components[stream]++; in gather_shader_info_gs()
861 if (!info->inputs_linked) in gather_shader_info_gs()
862 … info->gs.num_linked_inputs = util_last_bit64(radv_gather_unlinked_io_mask(nir->info.inputs_read)); in gather_shader_info_gs()
864 if (info->is_ngg) { in gather_shader_info_gs()
865 gather_shader_info_ngg_query(device, info); in gather_shader_info_gs()
867 radv_get_legacy_gs_info(device, info); in gather_shader_info_gs()
873 … const struct radv_shader_stage_key *stage_key, struct radv_shader_info *info) in gather_shader_info_mesh() argument
875 struct gfx10_ngg_info *ngg_info = &info->ngg_info; in gather_shader_info_mesh()
877 info->ms.output_prim = nir->info.mesh.primitive_type; in gather_shader_info_mesh()
907 ngg_info->max_out_verts = nir->info.mesh.max_vertices_out; in gather_shader_info_mesh()
910 ngg_info->prim_amp_factor = nir->info.mesh.max_primitives_out; in gather_shader_info_mesh()
913 info->ms.has_query = device->cache_key.mesh_shader_queries; in gather_shader_info_mesh()
914 info->ms.has_task = stage_key->has_task_shader; in gather_shader_info_mesh()
918 …kgroup_size(const struct radv_device *device, const nir_shader *nir, struct radv_shader_info *info) in calc_mesh_workgroup_size() argument
921 …unsigned api_workgroup_size = ac_compute_cs_workgroup_size(nir->info.workgroup_size, false, UINT32… in calc_mesh_workgroup_size()
925 info->workgroup_size = api_workgroup_size; in calc_mesh_workgroup_size()
927 struct gfx10_ngg_info *ngg_info = &info->ngg_info; in calc_mesh_workgroup_size()
931 info->workgroup_size = MAX2(min_ngg_workgroup_size, api_workgroup_size); in calc_mesh_workgroup_size()
937 … const struct radv_graphics_state_key *gfx_state, struct radv_shader_info *info) in gather_shader_info_fs() argument
941 info->ps.num_inputs = util_bitcount64(nir->info.inputs_read); in gather_shader_info_fs()
942 info->ps.can_discard = nir->info.fs.uses_discard; in gather_shader_info_fs()
943 info->ps.early_fragment_test = in gather_shader_info_fs()
944 nir->info.fs.early_fragment_tests || in gather_shader_info_fs()
945 …(nir->info.fs.early_and_late_fragment_tests && nir->info.fs.depth_layout == FRAG_DEPTH_LAYOUT_NONE… in gather_shader_info_fs()
946 nir->info.fs.stencil_front_layout == FRAG_STENCIL_LAYOUT_NONE && in gather_shader_info_fs()
947 nir->info.fs.stencil_back_layout == FRAG_STENCIL_LAYOUT_NONE); in gather_shader_info_fs()
948 info->ps.post_depth_coverage = nir->info.fs.post_depth_coverage; in gather_shader_info_fs()
949 info->ps.depth_layout = nir->info.fs.depth_layout; in gather_shader_info_fs()
950 info->ps.uses_sample_shading = nir->info.fs.uses_sample_shading; in gather_shader_info_fs()
951 info->ps.uses_fbfetch_output = nir->info.fs.uses_fbfetch_output; in gather_shader_info_fs()
952 info->ps.writes_memory = nir->info.writes_memory; in gather_shader_info_fs()
953 info->ps.has_pcoord = nir->info.inputs_read & VARYING_BIT_PNTC; in gather_shader_info_fs()
954 info->ps.prim_id_input = nir->info.inputs_read & VARYING_BIT_PRIMITIVE_ID; in gather_shader_info_fs()
955 info->ps.reads_layer = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_LAYER_ID); in gather_shader_info_fs()
956 info->ps.viewport_index_input = nir->info.inputs_read & VARYING_BIT_VIEWPORT; in gather_shader_info_fs()
957 info->ps.writes_z = nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH); in gather_shader_info_fs()
958 info->ps.writes_stencil = nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_STENCIL); in gather_shader_info_fs()
959 … info->ps.writes_sample_mask = nir->info.outputs_written & BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK); in gather_shader_info_fs()
960 …info->ps.reads_sample_mask_in = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_MASK… in gather_shader_info_fs()
961 info->ps.reads_sample_id = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_ID); in gather_shader_info_fs()
962 …info->ps.reads_frag_shading_rate = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FRAG_SHA… in gather_shader_info_fs()
963 info->ps.reads_front_face = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FRONT_FACE) | in gather_shader_info_fs()
964 … BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FRONT_FACE_FSIGN); in gather_shader_info_fs()
965 …info->ps.reads_barycentric_model = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BARYCENT… in gather_shader_info_fs()
966 …info->ps.reads_fully_covered = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FULLY_COVERE… in gather_shader_info_fs()
968 … bool uses_persp_or_linear_interp = info->ps.reads_persp_center || info->ps.reads_persp_centroid || in gather_shader_info_fs()
969 info->ps.reads_persp_sample || info->ps.reads_linear_center || in gather_shader_info_fs()
970 … info->ps.reads_linear_centroid || info->ps.reads_linear_sample; in gather_shader_info_fs()
972 info->ps.allow_flat_shading = in gather_shader_info_fs()
973 …!(uses_persp_or_linear_interp || info->ps.needs_sample_positions || info->ps.reads_frag_shading_ra… in gather_shader_info_fs()
974 info->ps.writes_memory || nir->info.fs.needs_quad_helper_invocations || in gather_shader_info_fs()
975 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_FRAG_COORD) || in gather_shader_info_fs()
976 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_PIXEL_COORD) || in gather_shader_info_fs()
977 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_POINT_COORD) || in gather_shader_info_fs()
978 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_ID) || in gather_shader_info_fs()
979 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_POS) || in gather_shader_info_fs()
980 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SAMPLE_MASK_IN) || in gather_shader_info_fs()
981 BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_HELPER_INVOCATION)); in gather_shader_info_fs()
983 info->ps.pops_is_per_sample = in gather_shader_info_fs()
984 …info->ps.pops && (nir->info.fs.sample_interlock_ordered || nir->info.fs.sample_interlock_unordered… in gather_shader_info_fs()
986 info->ps.spi_ps_input_ena = radv_compute_spi_ps_input(pdev, gfx_state, info); in gather_shader_info_fs()
987 info->ps.spi_ps_input_addr = info->ps.spi_ps_input_ena; in gather_shader_info_fs()
988 if (pdev->info.gfx_level >= GFX12) { in gather_shader_info_fs()
990 info->ps.spi_ps_input_addr &= C_02865C_COVERAGE_TO_SHADER_SELECT; in gather_shader_info_fs()
993 info->ps.has_epilog = gfx_state->ps.has_epilog && info->ps.colors_written; in gather_shader_info_fs()
995 const bool export_alpha = !!(info->ps.color0_written & 0x8); in gather_shader_info_fs()
997 if (info->ps.has_epilog) { in gather_shader_info_fs()
998 info->ps.exports_mrtz_via_epilog = gfx_state->ps.exports_mrtz_via_epilog && export_alpha; in gather_shader_info_fs()
1000 info->ps.mrt0_is_dual_src = gfx_state->ps.epilog.mrt0_is_dual_src; in gather_shader_info_fs()
1001 info->ps.spi_shader_col_format = gfx_state->ps.epilog.spi_shader_col_format; in gather_shader_info_fs()
1004 info->ps.spi_shader_col_format &= info->ps.colors_written; in gather_shader_info_fs()
1006 info->ps.cb_shader_mask = ac_get_cb_shader_mask(info->ps.spi_shader_col_format); in gather_shader_info_fs()
1009 if (!info->ps.exports_mrtz_via_epilog) { in gather_shader_info_fs()
1010 info->ps.writes_mrt0_alpha = gfx_state->ms.alpha_to_coverage_via_mrtz && export_alpha; in gather_shader_info_fs()
1020 info->ps.force_sample_iter_shading_rate = in gather_shader_info_fs()
1021 (info->ps.reads_sample_mask_in && !info->ps.needs_poly_line_smooth) || in gather_shader_info_fs()
1022 (pdev->info.gfx_level == GFX10_3 && in gather_shader_info_fs()
1023 (nir->info.fs.sample_interlock_ordered || nir->info.fs.sample_interlock_unordered || in gather_shader_info_fs()
1024 nir->info.fs.pixel_interlock_ordered || nir->info.fs.pixel_interlock_unordered)); in gather_shader_info_fs()
1028 gather_shader_info_rt(const nir_shader *nir, struct radv_shader_info *info) in gather_shader_info_rt() argument
1031 info->loads_dynamic_offsets = true; in gather_shader_info_rt()
1032 info->loads_push_constants = true; in gather_shader_info_rt()
1033 info->can_inline_all_push_constants = false; in gather_shader_info_rt()
1034 info->inline_push_constant_mask = 0; in gather_shader_info_rt()
1035 info->desc_set_used_mask = -1u; in gather_shader_info_rt()
1040 struct radv_shader_info *info) in gather_shader_info_cs() argument
1044 if (info->cs.uses_rt) in gather_shader_info_cs()
1047 …unsigned local_size = nir->info.workgroup_size[0] * nir->info.workgroup_size[1] * nir->info.workgr… in gather_shader_info_cs()
1050 …* is enabled. Furthermore, if cooperative matrices or subgroup info are used, we can't transparent… in gather_shader_info_cs()
1054 stage_key->subgroup_require_full || nir->info.cs.has_cooperative_matrix || in gather_shader_info_cs()
1055 …(default_wave_size == 32 && nir->info.uses_wide_subgroup_intrinsics && local_size % RADV_SUBGROUP_… in gather_shader_info_cs()
1060 info->wave_size = required_subgroup_size; in gather_shader_info_cs()
1062 info->wave_size = RADV_SUBGROUP_SIZE; in gather_shader_info_cs()
1063 } else if (pdev->info.gfx_level >= GFX10 && local_size <= 32) { in gather_shader_info_cs()
1065 info->wave_size = 32; in gather_shader_info_cs()
1067 info->wave_size = default_wave_size; in gather_shader_info_cs()
1070 if (pdev->info.has_cs_regalloc_hang_bug) { in gather_shader_info_cs()
1071 …info->cs.regalloc_hang_bug = info->cs.block_size[0] * info->cs.block_size[1] * info->cs.block_size… in gather_shader_info_cs()
1077 … const struct radv_shader_stage_key *stage_key, struct radv_shader_info *info) in gather_shader_info_task() argument
1079 gather_shader_info_cs(device, nir, stage_key, info); in gather_shader_info_task()
1086 info->cs.uses_block_id[0] = true; in gather_shader_info_task()
1087 info->cs.uses_block_id[1] = true; in gather_shader_info_task()
1088 info->cs.uses_block_id[2] = true; in gather_shader_info_task()
1089 info->cs.uses_grid_size = true; in gather_shader_info_task()
1092 info->cs.uses_local_invocation_idx = true; in gather_shader_info_task()
1097 info->cs.linear_taskmesh_dispatch = in gather_shader_info_task()
1098 …nir->info.mesh.ts_mesh_dispatch_dimensions[1] == 1 && nir->info.mesh.ts_mesh_dispatch_dimensions[2… in gather_shader_info_task()
1100 info->cs.has_query = device->cache_key.mesh_shader_queries; in gather_shader_info_task()
1104 radv_get_user_data_0(const struct radv_device *device, struct radv_shader_info *info) in radv_get_user_data_0() argument
1107 const enum amd_gfx_level gfx_level = pdev->info.gfx_level; in radv_get_user_data_0()
1109 switch (info->stage) { in radv_get_user_data_0()
1113 if (info->next_stage == MESA_SHADER_TESS_CTRL) { in radv_get_user_data_0()
1114 assert(info->stage == MESA_SHADER_VERTEX); in radv_get_user_data_0()
1125 if (info->next_stage == MESA_SHADER_GEOMETRY) { in radv_get_user_data_0()
1126 assert(info->stage == MESA_SHADER_VERTEX || info->stage == MESA_SHADER_TESS_EVAL); in radv_get_user_data_0()
1135 if (info->is_ngg) in radv_get_user_data_0()
1138 assert(info->stage != MESA_SHADER_MESH); in radv_get_user_data_0()
1161 …d_shader_compiled_separately(const struct radv_device *device, const struct radv_shader_info *info) in radv_is_merged_shader_compiled_separately() argument
1164 const enum amd_gfx_level gfx_level = pdev->info.gfx_level; in radv_is_merged_shader_compiled_separately()
1167 switch (info->stage) { in radv_is_merged_shader_compiled_separately()
1169 if (info->next_stage == MESA_SHADER_TESS_CTRL || info->next_stage == MESA_SHADER_GEOMETRY) in radv_is_merged_shader_compiled_separately()
1170 return !info->outputs_linked; in radv_is_merged_shader_compiled_separately()
1173 if (info->next_stage == MESA_SHADER_GEOMETRY) in radv_is_merged_shader_compiled_separately()
1174 return !info->outputs_linked; in radv_is_merged_shader_compiled_separately()
1178 return !info->inputs_linked; in radv_is_merged_shader_compiled_separately()
1188 …_shader_info_init(gl_shader_stage stage, gl_shader_stage next_stage, struct radv_shader_info *info) in radv_nir_shader_info_init() argument
1190 memset(info, 0, sizeof(*info)); in radv_nir_shader_info_init()
1193 info->can_inline_all_push_constants = true; in radv_nir_shader_info_init()
1195 info->stage = stage; in radv_nir_shader_info_init()
1196 info->next_stage = next_stage; in radv_nir_shader_info_init()
1203 bool consider_force_vrs, struct radv_shader_info *info) in radv_nir_shader_info_pass() argument
1209 info->loads_push_constants = true; in radv_nir_shader_info_pass()
1210 info->loads_dynamic_offsets = true; in radv_nir_shader_info_pass()
1214 gather_info_block(nir, block, info, gfx_state, stage_key, consider_force_vrs); in radv_nir_shader_info_pass()
1217 if (nir->info.stage == MESA_SHADER_VERTEX || nir->info.stage == MESA_SHADER_TESS_EVAL || in radv_nir_shader_info_pass()
1218 nir->info.stage == MESA_SHADER_GEOMETRY) in radv_nir_shader_info_pass()
1219 gather_xfb_info(nir, info); in radv_nir_shader_info_pass()
1221 if (nir->info.stage == MESA_SHADER_VERTEX || nir->info.stage == MESA_SHADER_TESS_EVAL || in radv_nir_shader_info_pass()
1222 nir->info.stage == MESA_SHADER_GEOMETRY || nir->info.stage == MESA_SHADER_MESH) { in radv_nir_shader_info_pass()
1223 struct radv_vs_output_info *outinfo = &info->outinfo; in radv_nir_shader_info_pass()
1229 if (nir->info.stage == MESA_SHADER_MESH && gfx_state->has_multiview_view_index) in radv_nir_shader_info_pass()
1230 info->uses_view_index = true; in radv_nir_shader_info_pass()
1237 (per_vtx_mask & VARYING_BIT_PRIMITIVE_SHADING_RATE) || info->force_vrs_per_vertex; in radv_nir_shader_info_pass()
1259 info->vs.needs_draw_id |= BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_DRAW_ID); in radv_nir_shader_info_pass()
1260 …info->vs.needs_base_instance |= BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_BASE_INSTAN… in radv_nir_shader_info_pass()
1261 … info->vs.needs_instance_id |= BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_INSTANCE_ID); in radv_nir_shader_info_pass()
1262 info->uses_view_index |= BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_VIEW_INDEX); in radv_nir_shader_info_pass()
1263 … info->uses_invocation_id |= BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_INVOCATION_ID); in radv_nir_shader_info_pass()
1264 info->uses_prim_id |= BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_PRIMITIVE_ID); in radv_nir_shader_info_pass()
1267 …info->cs.uses_grid_size = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_NUM_WORKGROUPS) || in radv_nir_shader_info_pass()
1268 (nir->info.stage == MESA_SHADER_MESH && pdev->info.gfx_level < GFX11); in radv_nir_shader_info_pass()
1269 …info->cs.uses_local_invocation_idx = BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_LOCAL_… in radv_nir_shader_info_pass()
1270 … BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_SUBGROUP_ID) | in radv_nir_shader_info_pass()
1271 … BITSET_TEST(nir->info.system_values_read, SYSTEM_VALUE_NUM_SUBGROUPS) | in radv_nir_shader_info_pass()
1274 if (nir->info.stage == MESA_SHADER_COMPUTE || nir->info.stage == MESA_SHADER_TASK || in radv_nir_shader_info_pass()
1275 nir->info.stage == MESA_SHADER_MESH) { in radv_nir_shader_info_pass()
1277 info->cs.block_size[i] = nir->info.workgroup_size[i]; in radv_nir_shader_info_pass()
1280 info->user_data_0 = radv_get_user_data_0(device, info); in radv_nir_shader_info_pass()
1281 … info->merged_shader_compiled_separately = radv_is_merged_shader_compiled_separately(device, info); in radv_nir_shader_info_pass()
1282 …info->force_indirect_desc_sets = info->merged_shader_compiled_separately || stage_key->indirect_bi… in radv_nir_shader_info_pass()
1284 switch (nir->info.stage) { in radv_nir_shader_info_pass()
1286 gather_shader_info_cs(device, nir, stage_key, info); in radv_nir_shader_info_pass()
1289 gather_shader_info_task(device, nir, stage_key, info); in radv_nir_shader_info_pass()
1292 gather_shader_info_fs(device, nir, gfx_state, info); in radv_nir_shader_info_pass()
1295 gather_shader_info_gs(device, nir, info); in radv_nir_shader_info_pass()
1298 gather_shader_info_tes(device, nir, info); in radv_nir_shader_info_pass()
1301 gather_shader_info_tcs(device, nir, gfx_state, info); in radv_nir_shader_info_pass()
1304 gather_shader_info_vs(device, nir, gfx_state, stage_key, info); in radv_nir_shader_info_pass()
1307 gather_shader_info_mesh(device, nir, stage_key, info); in radv_nir_shader_info_pass()
1310 if (gl_shader_stage_is_rt(nir->info.stage)) in radv_nir_shader_info_pass()
1311 gather_shader_info_rt(nir, info); in radv_nir_shader_info_pass()
1315 info->wave_size = radv_get_wave_size(device, nir->info.stage, info, stage_key); in radv_nir_shader_info_pass()
1316 info->ballot_bit_size = radv_get_ballot_bit_size(device, nir->info.stage, info, stage_key); in radv_nir_shader_info_pass()
1318 switch (nir->info.stage) { in radv_nir_shader_info_pass()
1321 … info->workgroup_size = ac_compute_cs_workgroup_size(nir->info.workgroup_size, false, UINT32_MAX); in radv_nir_shader_info_pass()
1328 …info->cs.uses_full_subgroups = pipeline_type != RADV_PIPELINE_RAY_TRACING && !nir->info.internal && in radv_nir_shader_info_pass()
1329 (info->workgroup_size % info->wave_size) == 0; in radv_nir_shader_info_pass()
1332 if (info->vs.as_ls || info->vs.as_es) { in radv_nir_shader_info_pass()
1336 info->workgroup_size = 256; in radv_nir_shader_info_pass()
1338 info->workgroup_size = info->wave_size; in radv_nir_shader_info_pass()
1343 info->workgroup_size = in radv_nir_shader_info_pass()
1344 …ac_compute_lshs_workgroup_size(pdev->info.gfx_level, MESA_SHADER_TESS_CTRL, info->num_tess_patches, in radv_nir_shader_info_pass()
1345 … gfx_state->ts.patch_control_points, info->tcs.tcs_vertices_out); in radv_nir_shader_info_pass()
1348 info->workgroup_size = 256; in radv_nir_shader_info_pass()
1352 if (info->tes.as_es) { in radv_nir_shader_info_pass()
1356 info->workgroup_size = 256; in radv_nir_shader_info_pass()
1358 info->workgroup_size = info->wave_size; in radv_nir_shader_info_pass()
1362 if (!info->is_ngg) { in radv_nir_shader_info_pass()
1363 unsigned es_verts_per_subgroup = info->gs_ring_info.es_verts_per_subgroup; in radv_nir_shader_info_pass()
1364 unsigned gs_inst_prims_in_subgroup = info->gs_ring_info.gs_inst_prims_in_subgroup; in radv_nir_shader_info_pass()
1366 … info->workgroup_size = ac_compute_esgs_workgroup_size(pdev->info.gfx_level, info->wave_size, in radv_nir_shader_info_pass()
1372 info->workgroup_size = 256; in radv_nir_shader_info_pass()
1376 calc_mesh_workgroup_size(device, nir, info); in radv_nir_shader_info_pass()
1382 info->workgroup_size = info->wave_size; in radv_nir_shader_info_pass()
1468 const enum amd_gfx_level gfx_level = pdev->info.gfx_level; in gfx10_get_ngg_info()
1679 const struct radv_shader_info *info = gs_info ? gs_info : es_info; in gfx10_get_ngg_info() local
1680 … unsigned scratch_lds_size = ac_ngg_get_scratch_lds_size(info->stage, info->workgroup_size, info->… in gfx10_get_ngg_info()
1681 … pdev->use_ngg_streamout, info->has_ngg_culling, false); in gfx10_get_ngg_info()
1703 ps_inputs_read = fs_stage->nir->info.inputs_read; in radv_determine_ngg_settings()
1708 ps_inputs_read = es_stage->nir->info.outputs_written; in radv_determine_ngg_settings()
1718 … num_vertices_per_prim = es_stage->nir->info.tess.point_mode ? 1 in radv_determine_ngg_settings()
1719 … : es_stage->nir->info.tess._primitive_mode == TESS_PRIMITIVE_ISOLINES ? 2 in radv_determine_ngg_settings()
1723 es_stage->info.has_ngg_culling = in radv_determine_ngg_settings()
1724 …radv_consider_culling(pdev, es_stage->nir, ps_inputs_read, num_vertices_per_prim, &es_stage->info); in radv_determine_ngg_settings()
1727 es_stage->info.has_ngg_early_prim_export = exec_list_is_singular(&impl->body); in radv_determine_ngg_settings()
1732 …es_stage->info.is_ngg_passthrough = !es_stage->info.has_ngg_culling && !(es_stage->stage == MESA_S… in radv_determine_ngg_settings()
1733 … es_stage->info.outinfo.export_prim_id); in radv_determine_ngg_settings()
1745 if (producer->info.next_stage == MESA_SHADER_FRAGMENT || in radv_link_shaders_info()
1747 const bool ps_prim_id_in = !consumer || consumer->info.ps.prim_id_input; in radv_link_shaders_info()
1748 const bool ps_clip_dists_in = !consumer || !!consumer->info.ps.input_clips_culls_mask; in radv_link_shaders_info()
1750 …radv_set_vs_output_param(device, producer->nir, gfx_state, &producer->info, ps_prim_id_in, ps_clip… in radv_link_shaders_info()
1754 /* Compute NGG info (GFX10+) or GS info. */ in radv_link_shaders_info()
1755 if (producer->info.is_ngg) { in radv_link_shaders_info()
1757 … struct gfx10_ngg_info *out = gs_stage ? &gs_stage->info.ngg_info : &producer->info.ngg_info; in radv_link_shaders_info()
1764 gfx10_get_ngg_info(device, &producer->info, gs_stage ? &gs_stage->info : NULL, out); in radv_link_shaders_info()
1766 struct radv_shader_info *gs_info = &consumer->info; in radv_link_shaders_info()
1767 struct radv_shader_info *es_info = &producer->info; in radv_link_shaders_info()
1773 producer->info.gs_inputs_read = consumer->nir->info.inputs_read; in radv_link_shaders_info()
1781 vs_stage->info.vs.tcs_inputs_via_lds = tcs_stage->nir->info.inputs_read; in radv_link_shaders_info()
1784 vs_stage->info.workgroup_size = in radv_link_shaders_info()
1785 …ac_compute_lshs_workgroup_size(pdev->info.gfx_level, MESA_SHADER_VERTEX, tcs_stage->info.num_tess_… in radv_link_shaders_info()
1786 … gfx_state->ts.patch_control_points, tcs_stage->info.tcs.tcs_vertices_out); in radv_link_shaders_info()
1798 vs_stage->info.vs.tcs_in_out_eq = in radv_link_shaders_info()
1799 pdev->info.gfx_level >= GFX9 && in radv_link_shaders_info()
1800 gfx_state->ts.patch_control_points == tcs_stage->info.tcs.tcs_vertices_out && in radv_link_shaders_info()
1801 …vs_stage->nir->info.float_controls_execution_mode == tcs_stage->nir->info.float_controls_execution… in radv_link_shaders_info()
1803 if (vs_stage->info.vs.tcs_in_out_eq) { in radv_link_shaders_info()
1804 vs_stage->info.vs.tcs_inputs_via_temp = vs_stage->nir->info.outputs_written & in radv_link_shaders_info()
1805 … ~vs_stage->nir->info.outputs_accessed_indirectly & in radv_link_shaders_info()
1806 … tcs_stage->nir->info.tess.tcs_same_invocation_inputs_read; in radv_link_shaders_info()
1807 …vs_stage->info.vs.tcs_inputs_via_lds = tcs_stage->nir->info.tess.tcs_cross_invocation_inputs_read | in radv_link_shaders_info()
1808 … (tcs_stage->nir->info.tess.tcs_same_invocation_inputs_read & in radv_link_shaders_info()
1809 … tcs_stage->nir->info.inputs_read_indirectly) | in radv_link_shaders_info()
1810 … (tcs_stage->nir->info.tess.tcs_same_invocation_inputs_read & in radv_link_shaders_info()
1811 … vs_stage->nir->info.outputs_accessed_indirectly); in radv_link_shaders_info()
1817 /* Copy shader info between TCS<->TES. */ in radv_link_shaders_info()
1822 tcs_stage->info.tcs.tes_reads_tess_factors = tes_stage->info.tes.reads_tess_factors; in radv_link_shaders_info()
1823 tcs_stage->info.tcs.tes_inputs_read = tes_stage->nir->info.inputs_read; in radv_link_shaders_info()
1824 tcs_stage->info.tcs.tes_patch_inputs_read = tes_stage->nir->info.patch_inputs_read; in radv_link_shaders_info()
1825 tcs_stage->info.tes._primitive_mode = tes_stage->nir->info.tess._primitive_mode; in radv_link_shaders_info()
1828 tes_stage->info.num_tess_patches = tcs_stage->info.num_tess_patches; in radv_link_shaders_info()
1835 const struct radv_shader_info *src_info = &src->info; in radv_nir_shader_info_merge()
1836 struct radv_shader_info *dst_info = &dst->info; in radv_nir_shader_info_merge()
1886 if (pdev->info.gfx_level >= GFX9) { in radv_nir_shader_info_link()
1887 /* Merge shader info for VS+TCS. */ in radv_nir_shader_info_link()
1892 /* Merge shader info for VS+GS or TES+GS. */ in radv_nir_shader_info_link()
1902 radv_select_hw_stage(const struct radv_shader_info *const info, const enum amd_gfx_level gfx_level) in radv_select_hw_stage() argument
1904 switch (info->stage) { in radv_select_hw_stage()
1906 if (info->is_ngg) in radv_select_hw_stage()
1908 else if (info->vs.as_es) in radv_select_hw_stage()
1910 else if (info->vs.as_ls) in radv_select_hw_stage()
1915 if (info->is_ngg) in radv_select_hw_stage()
1917 else if (info->tes.as_es) in radv_select_hw_stage()
1924 if (info->is_ngg) in radv_select_hw_stage()