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Lines Matching refs:spm

23    result = radv_bo_create(device, NULL, device->spm.buffer_size, 4096, RADEON_DOMAIN_VRAM,  in radv_spm_init_bo()
26 device->spm.bo = bo; in radv_spm_init_bo()
30 result = ws->buffer_make_resident(ws, device->spm.bo, true); in radv_spm_init_bo()
34 device->spm.ptr = radv_buffer_map(ws, device->spm.bo); in radv_spm_init_bo()
35 if (!device->spm.ptr) in radv_spm_init_bo()
46 if (device->spm.bo) { in radv_spm_finish_bo()
47 ws->buffer_make_resident(ws, device->spm.bo, false); in radv_spm_finish_bo()
48 radv_bo_destroy(device, NULL, device->spm.bo); in radv_spm_finish_bo()
59 device->spm.buffer_size *= 2; in radv_spm_resize_bo()
64 device->spm.buffer_size / 1024); in radv_spm_resize_bo()
75 struct ac_spm *spm = &device->spm; in radv_emit_spm_counters() local
78 for (uint32_t instance = 0; instance < ARRAY_SIZE(spm->sq_wgp); instance++) { in radv_emit_spm_counters()
79 uint32_t num_counters = spm->sq_wgp[instance].num_counters; in radv_emit_spm_counters()
86 radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX, spm->sq_wgp[instance].grbm_gfx_index); in radv_emit_spm_counters()
89 const struct ac_spm_counter_select *cntr_sel = &spm->sq_wgp[instance].counters[b]; in radv_emit_spm_counters()
98 for (uint32_t instance = 0; instance < ARRAY_SIZE(spm->sqg); instance++) { in radv_emit_spm_counters()
99 uint32_t num_counters = spm->sqg[instance].num_counters; in radv_emit_spm_counters()
111 const struct ac_spm_counter_select *cntr_sel = &spm->sqg[instance].counters[b]; in radv_emit_spm_counters()
119 for (uint32_t b = 0; b < spm->num_block_sel; b++) { in radv_emit_spm_counters()
120 struct ac_spm_block_select *block_sel = &spm->block_sel[b]; in radv_emit_spm_counters()
156 struct ac_spm *spm = &device->spm; in radv_emit_spm_setup() local
157 uint64_t va = radv_buffer_get_va(spm->bo); in radv_emit_spm_setup()
158 uint64_t ring_size = spm->buffer_size; in radv_emit_spm_setup()
163 assert(spm->sample_interval >= 32); in radv_emit_spm_setup()
170 S_037200_PERFMON_SAMPLE_INTERVAL(spm->sample_interval)); /* in sclk */ in radv_emit_spm_setup()
178 total_muxsel_lines += spm->num_muxsel_lines[s]; in radv_emit_spm_setup()
186 … S_03721C_GLOBAL_NUM_SEGMENT(spm->num_muxsel_lines[AC_SPM_SEGMENT_TYPE_GLOBAL]) | in radv_emit_spm_setup()
187 S_03721C_SE_NUM_SEGMENT(spm->max_se_muxsel_lines)); in radv_emit_spm_setup()
193 S_03727C_SE0_NUM_LINE(spm->num_muxsel_lines[AC_SPM_SEGMENT_TYPE_SE0]) | in radv_emit_spm_setup()
194 … S_03727C_SE1_NUM_LINE(spm->num_muxsel_lines[AC_SPM_SEGMENT_TYPE_SE1]) | in radv_emit_spm_setup()
195 … S_03727C_SE2_NUM_LINE(spm->num_muxsel_lines[AC_SPM_SEGMENT_TYPE_SE2]) | in radv_emit_spm_setup()
196 … S_03727C_SE3_NUM_LINE(spm->num_muxsel_lines[AC_SPM_SEGMENT_TYPE_SE3])); in radv_emit_spm_setup()
199 … S_037280_GLOBAL_NUM_LINE(spm->num_muxsel_lines[AC_SPM_SEGMENT_TYPE_GLOBAL])); in radv_emit_spm_setup()
207 if (!spm->num_muxsel_lines[s]) in radv_emit_spm_setup()
224 … radeon_check_space(device->ws, cs, 3 + spm->num_muxsel_lines[s] * (7 + AC_SPM_MUXSEL_LINE_SIZE)); in radv_emit_spm_setup()
228 for (unsigned l = 0; l < spm->num_muxsel_lines[s]; l++) { in radv_emit_spm_setup()
229 uint32_t *data = (uint32_t *)spm->muxsel_lines[s][l].muxsel; in radv_emit_spm_setup()
259 if (!ac_init_spm(gpu_info, pc, &device->spm)) in radv_spm_init()
262 device->spm.buffer_size = 32 * 1024 * 1024; /* Default to 32MB. */ in radv_spm_init()
263 device->spm.sample_interval = 4096; /* Default to 4096 clk. */ in radv_spm_init()
276 ac_destroy_spm(&device->spm); in radv_spm_finish()
284 if (!ac_spm_get_trace(&device->spm, spm_trace)) { in radv_get_spm_trace()