ELFx@@-*FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF   eA    o  2  * ~   force_stagedisable_bypass&smmu->stream_map_mutexarm-smmufailed to allocate %d irqs disabling translation %scoherent table walk failed to set DMA mask for table walker Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d /mnt/disks/build-disk/src/android/common-android14-5.15/out/bazel/output_user_root/c126e7d3c13484ebc27ab7dd47bee034/sandbox/linux-sandbox/33/execroot/__main__/common/drivers/iommu/arm/arm-smmu/arm-smmu.cstream-matching supported, but no SMRs present! qcom,adreno-smmu address translation ops arm-smmu-context-faultiova to phys timed out on %pad. Falling back to software table walk. mmu-mastersprobing hardware configuration... found %d interrupts but expected at least %d failed to request context IRQ %d (%u) /mnt/disks/build-disk/src/android/common-android14-5.15/out/bazel/output_user_root/c126e7d3c13484ebc27ab7dd47bee034/sandbox/linux-sandbox/33/execroot/__main__/common/drivers/iommu/arm/arm-smmu/arm-smmu.hqcom,sdm845-smmu-500smmu.%paFailed to register iommu in sysfs Stage-1: %lu-bit VA -> %lu-bit IPA nvidia,tegra194-smmuFailed to turn off SAFE logic SMR mask 0x%x out of range for SMMU (0x%x) enabling workaround for Cavium erratum 27704 Unexpected global fault, this could be serious stream ID 0x%x out of range for SMMU (0x%x) #global-interruptsSMMU stream matching with %u register groupsnon- GFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x Stage-2: %lu-bit IPA -> %lu-bit PA TLB sync timed out -- SMMU may be deadlocked arm_smmu_context_faulttranslation fault! nvidia,tegra186-smmuarm-smmu global fault no translation support! SMMU address space size (0x%x) differs from mapped region size (0x%x)! impossible number of S2 context banks! cannot attach to SMMU %s whilst already attached to domain on SMMU %s failed to allocate arm_smmu_device failed to request global IRQ %d (%u) __arm_smmu_tlb_syncmarvell,ap806-smmu-5005arm-smmu: deprecated "mmu-masters" DT property in use; %s support unavailable SMMUv%d with: &smmu_domain->init_mutexmissing #global-interrupts property not probing due to mismatched DT properties stream-match-maskqcom,msm8996-smmu-v2failed to get clocks %d stage 1 translation %u context banks (%u stage-2 only) Failed to register iommu arm_smmu_global_faultBlocked unknown Stream ID 0x%hx; boot with "arm-smmu.disable_bypass=0" to allow, but this may have security implications Supported page sizes: 0x%08lx cannot attach to SMMU, is it on the same bus? PAR = 0x%llx nested translation (IDR0.CTTW overridden by FW configuration) Limiting the stream matching groups to 128 calxeda,smmu-secure-config-accessfound only %d context irq(s) but %d required stage 2 translation arm,smmu-v1arm,smmu-v2arm,mmu-400arm,mmu-401arm,mmu-500cavium,smmu-v2nvidia,smmu-500qcom,smmu-v2qcom,msm8998-smmu-v2qcom,sc7180-smmu-500qcom,sc7280-smmu-500qcom,sc8180x-smmu-500qcom,sdm630-smmu-v2qcom,sdm845-smmu-500qcom,sm6125-smmu-500qcom,sm8150-smmu-500qcom,sm8250-smmu-500qcom,sm8350-smmu-500qcom,adrenoqcom,adreno-gmuqcom,mdp4qcom,mdssqcom,sc7180-mdssqcom,sc7180-mss-pilqcom,sc7280-mdssqcom,sc8180x-mdssqcom,sdm845-mdssqcom,sdm845-mss-pil'void (struct arm_smmu_device *, int, unsigned int)''void (struct arm_smmu_device *, int, int, unsigned long long)''int (struct arm_smmu_device *)''int (struct arm_smmu_domain *, struct io_pgtable_cfg *, struct device *)''void (struct arm_smmu_device *, int, int, int)''int (struct arm_smmu_domain *, struct arm_smmu_device *, struct device *, int)''void (struct arm_smmu_device *, int)''int (struct io_pgtable_ops *, unsigned long, unsigned long long, unsigned long, unsigned long, int, unsigned int, unsigned long *)''unsigned long (struct io_pgtable_ops *, unsigned long, unsigned long, unsigned long, struct iommu_iotlb_gather *)''void (void *)''unsigned long long (struct io_pgtable_ops *, unsigned long)''void (struct arm_smmu_device *, struct device *)''int (struct device *)' $(*,'unsigned int (struct arm_smmu_device *, int, int)''unsigned long long (struct arm_smmu_device *, int, int)''void (struct arm_smmu_device *, int, int, unsigned int)'H TҨ#- Tőȥ(|'TȑUT葐U*T>訦@*T(U!1ThH(=ȿmTHhp,T (ѽ((T( (ѽ((&TȲH&TȽҨֲ=A,T'HOEmTh(hdTh(hd#T҈(@#T|šoȆ!(THhY TH(ձHmTh(ձH@ TMhT(hǽ_U$T+((TH(T҈$ȇhV@ThZ( TH(mT(H(THڥZ<T[hATh,ȩ{TKĸh:`TӔҨȨhxTd:(*T(H T(ʯ(;>TҨ#T5H@!TH(=ȿ T(҈(aATHOET貘(HRaTHhY THTőȥ(|'THh(ZT(Hhp TҨ(e Tq,ȩ{ T(ȭt( T( ȓ# TPd:(* T((>TOBI( ȓ T45<9630-*'$! ( ȓ#T( ȓ #T?!T_?#{@9qT{#_ )+ih8J @@*?#{_WOC$@R*8X(@h@vS5@(4( @qhb@9h06(@yc@*i@H i)@ii@+Rj@i!I)(((@i@S?qIT4`Ri@h@4 h@(i@*j@"I)(S(@9c`*5hb@9h07( @9c*h@~@h@(h@*Ri@H!(("U4h@4Rj@Z(h@A #@h@h@i@( ((ARj@Z(h@A #@h@h@i@( ((h@) @ ? qTh@#@yh@h@i@( ((i@h@@! h@h@i@( ((i@h@ @! h@Xh@i@( ((u58h@@h @h@i@( ((4h@j@  @jJ @Jj@k@)!i))(Rj@Z(h@A #@h@ h@i@( ((Rj@Z(h@A #@h@ h@i@( ((q R Ri@C(5@ ) T**? h@ j@(@T h@i@"((OEWD_C{A@#_ ) T!R?55a ) TR?h* J? T!R* ?* ) ATR?֩ ) TR?ְ ) T***2 ) TR?L )? TR ?Q ) TR?55 ) TR?u5 ) TR?  ) T**?֑_T@R@@?H B@**e )@  @ @@r B@  @@ @l B@ @@@f B@ *@*c B@* ***\ B@ Y B@ *@*@S B@  @ @N B@ *@*I>Bਦ@@C B@  @@ @= B@ **8>Bਦ@;?#{_WOA8@%C!RR A!#R 7@!@A"@97 @97!@9q T)RA 96@2C*?cTW @ @ @@(K@iT*H*R* @kT@@h47~~Rf4**7f@y7TB*`7j@**5*@4**!v !!VA8%C_ AT*OFWE_D{B@#_*5@ qT2@@kH T@h%@w@h4*f@@!hR}@@ 5@( kCTc#N 5! 5V:A*@9H6*@!*!*** 4*!*!f@*!yy*!f!*vs?#{OT@`R! Ttt@Dy rTR`7h@h@hh@)R `@Dy r T rT`@aj@ @ R`@Dy rT`@aj@*OA{¨#_ֈ ߈4"Q *  * *?k* T}_ J5 5;B! ) T**#R? B@  ?#{{#_?#{  BL@ qTDy rT`@aj@`@aj@* @{¨#_?#{ OL@@j@*5B qTDy rTN@@j@*4@j@**OB @{è#_?#{L@@i@*{#_?#{OL@`@aj@*`5*OA{¨#_?#C{WOC@h@h@!@h@h@h@!hV@(4**hV@kCTh2@4?R*r*i@h@ h@h@i@( ((ah2@kTT?R Rr? ҡ@ @@h@h@ h@  h@h@t h@  h@h@ h@@j@醟ˆR @9qRK}S *I} S } *)h@T *h@5 ȓ T?ur*RRh@h@uh@ODWC{A@C#_! T* R?*h@mT* R*?hV@5naT* R?h@T* R?h@HT**?֔T***?ַőB |'dB: * B@  B@  B@ dB: * B@ ߈߈?#{OC*h2@Rkf@9")*@y)@yCA *  7~@R(!*i2@9qcvSh@4 h@(h@4OB{A#_ ) T**? B@ @_?#{ g_WO**@*@ @ h@i@"(( A6 HR*8RrZ;h@h@h@i@")((@@6? {1cTT**?7d: *@*{SkCT! 5OEWD_CgB @{ƨ#_`@!B`@***? ) T**?֧ B@ ߈?#{ @ 4@)(1@ ) T?(|@ R )+CQ@9KA)c3 d@9C3+ 6 0@R)+j2@9qc(tS0i(@@"{B#_ ) !T*?`B `d@_ @ )  @@ @_?#{O7*57* 5`6** 4*OA{¨#_?#{WO@@!h@!`@ q(Rh@h@*h@@@ q`TqATt*U7577h@rT6i@? qCT56r5NӟkTh@ qT@6h@4R2h2 S)R4!Qhy 7*`@F4R}`6  *R,@9k6@qkLa1) T`!BtVh@ qCT7h@ 2iu72hh@h@t"h@@qRRzS(Rc@KR)!u!"!hkT`@!^S`@kub)) T!>h@r2hT `@ySR`2`OBWA{è#_ *6h@!`@2h56h@!`@2hU6h@!`@2hj`@! `@!pB`@!@2`@!hrt4B`@!U`@!*a!h2@R`@ }`&* qT )(YhRShV?qTYiRhZx6i@)2i `@(!Ț(@ 5h@qThV@hRT.SqT )(YhRhRt`7h7p6h@2hh@@T ȓ T?ր5 Rh@)"rX6j^@J j^ R jT@7i^@H6(R)i^! @_) `@b^@h@77*Lh@2ho6h@2h4w7j^@ R rJ j^G6j^@){I i^i^@(O7`@!T*R?֧bJ!`@h@6bJ!`@!T*R?*őB |'dB: *dB: *߈߈?#{ WO(@h@h@!@h@h@uh@A@h@h@ h@Q@h@h@ h@a@t 4!@5h@h@ h@ R!E`@7!>!`@!****h@T* R?*h@AT* R?*h@(T* R?*h@T* R?*5*OCWB @{Ĩ#_T* R*? RdB: *dB: *dB: *dB: * B@ ߈߈߈߈?#{OC0@ T@4*RRL!+@94J? kAT"h@c@yh@Hh@4h@h@h@4@h@<S`yh@h@4h@h@Hh@4@|ShyOB{A#_ ) T**?h@h ) T**? ) !T**?h@ ) aT**? B@  @ @dB: *@ B@  @ @dB: *@߈߈xr_?#{ q`T*qTy qaT@97RR@@!B`j @{¨#_?#{WOtY4@qT@Dy rTR7&@ R[8(![8[8qT@@( f@!YhY[8*R(CI!ɚ}'&)@Dy raTROBWA{è#_ ߈4"Q *  * *?k*T}_ J5 5; }_J) } ȫ5 ?#{ o g _ W OCA8%C(AH !@ @ J? a T)@ @v@Dy rTR@7Y@q ThR@T\ q@h4*y6@[8R (d:4Q9@kT6!y)d:*@_k!T*d:JQ@9 kT`@R`@!R*`@Dy raTRY!A8%C_ 5T*ONWM_LgKoJ{I#_h@h7(Rh@6HP7 rT(R H7h@W6HRh@ rT[H4\*Q_ qTB RiJ?,1_K1qh@KjR)J qT*I* ߈4"Q *  * *?k*T}_ J5 5;)5)RqBi.Jy6@T qT?R)1Rk1l@9@B@h@9@C@!|* HR?R)1k1Rh@ -@Z_a$T*@?*@Y7B@y9h@qTiB$#(R* 8 i@[8J H 8*z{2<@6RkT)F"ٚI *1_T1*}_K+ Ȭ5;_T@y@8\)Zq("xi@hb@9k^@+ h@/ @#9+)@( ȓ BT ?*5Z@(@@ @)!ܚ@9 j(7)yi@9*R(CI!ɚ}h)@6)RYB[9[8H%@ R*![K4[@ q!T Rg@+!l8k@@lQSmaSnqSl 353 R-3l)3(!l13lI 32 3@HIk@R}S}SaSn3}Sk3@ *A 3+!=S 22{ 2 k@ 3oM[qT R mr *l2[ qTc@_ "[xk=PK"[x=PL@93@(7 K K[_ qT R(!o@ k@  R(!;@ w@ [8h@[8 if@9Yhh@h)@`@*R7 `@![8*R8 B >Bֲ=/1(}_( 5; }_J) } ȫ5F ?#{og_WOYY**@hDy rTR7[@`ҠBby**`?ֈ@* Dy? rTRS*OEWD_CgBoA{ƨ#_h ߈)4"Q *  * *?k*T}_ J5 5; ?#{ _WOYY8@Dy rTR@7@ٍҠBL?(@ Dy? rTRODWC_B @{Ũ#_ ߈4"Q *  * *?k*@T}_ J5 5; ?#{WOvYh@H@Dy rTR7Z@ ȓ T?@Dy raTROBWA{è#_֨ ߈)4"Q *  * *?k*T}_ J5 5; B a ?#{ WOYu@Dy rTR7h@ qT\4tr*RR"ѕY@[8RR `@Dy raTROCWB @{Ĩ#_֨ ߈I4"Q *  * *?k*T}_ J5 5; ?#{g_WOA8%CYVYhb@9h(6(\4@@ HB@`?~ :[8u@Dy rTR` 77#i@*[t) _qTj@jY @j@k@)!i)) ( j@jY@j@k@)!i)) (h&B)j@ !H(#(@1** 6jRlT`|R? (@1** 7(@*1) H7i@h@6 h @9 h@i@"((A@ 7nt.@`@Dy rTR ߈4"Q *  * *?k*`T}_ J5 5;A8%C_ A TOGWF_EgD{B@#_!C`@Dy raTR@@ HB@ @X!!?T* R ??T@R@ ?c?AT@R@ ?WB ʯ ;>>Bਦ B@ (߈(߈(߈ ?#{ g_WOA )@9 7!@5 @ ) T@cTN@@4@y*#*) @b=_ jAT@yb}S_(jAT) kT~@R!hA)64qTTz QR*"-k Q)x) Q-xK5k TQR(Q1IyT@Dy rTR7hA!@)@(@96V~@TOEWD_CgB @{ƨ#_v8@3@H@4* RR,R 7@): @ yM@? kbT-)x1TN)3@@}SW@4*vq?kT@+!@9!4|@="@+A@yB@y! BJqC! `@zT!@N*_!jT=*7*{7@F1 @5n.y/y,9 4 R +RRRQy1T.(7@ύxA) @1q T7@Q@9A)?qqF) 3@pA,9* ߈4"Q *  * *?k*`T}_ J5 5;!!*_M4*(6yH@k#T*@Dy raTR4FNRFv ?#{og_WOCA !@W @ J? T)@@@Dy rTR@7@c@4*R<RRy9@?kT96@x( : @)q T6@i@9( :?q%) 2@R( )9@@@Dy raTRhA)OFWE_DgCoB{A#_ ߈4"Q *  * *?k*@T}_ J5 5; ?#{ OAH)@@@9@B ?OB @{è#_?#{_WOA)@!@@@4* 7@ R) kT)y}+Uim UT#B@ ) `T@T@4* R( 7@JyJ})ti*@ kTOCWB_A{Ĩ#_?#{ OYhHR**OB @{è#_?#{WOYh**OBWA{è#_?#{WORRBRRv@6uZOBWA{è#_?#{OCA8%C(@qT4@yqT(@ * @!#R7@B*"RA8%C@ TOB{A#_?#{CAH)@@@h!@( )  ) ɓ?T?*{A#_# Bt #@?#{ _WO3Y4[8i@h@5 h@ h@i@"((a@?Rrj Ti@h@7 h@ h@i@"((@i@h@8 h @ h@i@#((@ Rh@9 h@h h@*Ri@H!((@S1T!5i@h@4 h@vh@ Ri@"((a*ODWC_B @{Ũ#_`@!****T* R?*T* R?*?T* R ? ) T!R*?*T* R*? RdB: *dB: *B ʯ ;>dB: *@ B@ ߈߈߈?#{ O@>D@yh@h@h@tr*RROB @{è#_ ) T* R? B@ **?#{{#_?#{`@`@9H6>@cD@yh@@{B#_ ) T* R? @B C@C__?#{WOƀRut@@i@9RR OBWA{è#_?#{ǀR{#_?#{og_WOCv@*z@9b@9H6>L*L J k9 @@( )((T@*@ ?qT@h @h@@( )((@@ !T**? T*? J k ҡ@ @_>ҡਦB@_OFWE_DgCoB{A#_?#{WOC>@j@9 @@cF@y! h@@ @( ((Aut@@i@9RR OCWB{A#_ ) T€R? @B ***@*?#{WOh@94Rut@@i@9RR OBWA{è#_?#{ĀR{#_?#{og_WOu@*x@9b@9H6>i(@hD@y?qT=P*1@L@@! h @h@@( )(({AT?T*?>ҡਦ @_ t:*@C@! h@h@@( )((9!TT*? ҡ@ @_OGWF_EgDoC{B#_?#{C@h@@@{A#_ ) T*R?d:B *@߈?#{ O*5*OB @{è#_?#{_WO@h@ h@@h@h@ h@A@_R rr R h@4 *h@ h@Ah2@ 4*i@h@ h@(h@i@( ((@i@xh@ h@Hh@i@( ((h2@kTGaTR?!TR?dҡ: * @_ ҡ@ @_@T*R?*h@AT*R?֏AT*R*?h2@5*OEWD_C{B#_dB: *dB: * B@ ߈߈߈?#{O @@ q`TxAqTh!h!5!4`@%RRS"RR s !4hOA{¨#_@ @( ((" )@@* _)߈߈ @h` @) I))"*H#_* @)q _5H QAqT)R(!) R)r jT_@q@TB5B@ @( (("@_߈5H QAqT)R(!) R)r jT_@q@TB5B@ @( (("_?#{0@ )(*@ !*{#_ JQI}_+ K 5;* @ E@y)ByI Ey_?#{@%RR@`{#_?#{O@!yA46`@"RR  6`@"RRh@sOA{¨#_?#{ _WOT@qT uSh@4/h@h@R)rA4 h@h@h@A4@A@q Th@9+R Qk"9H}S}hi!ʚj&91)i@j&D9h@4 h@ui@*j@"I)(i&D9h@4~h@5h@*Ri@H!(()R hV@H4*R7RR9hV@k Th@h@h@4@6h2@~@)6*)} yxSk2@hi*xh2@ 9h6@  h6@ h6@ Q9T**?6d: *@`@!RhV|TR**#r?h@~AT**?xAT***?֋!T!R*#R?hV@5*ODWC_B @{Ũ#_ }_J } ȫ5e B@ dB: * B@  B@ ߈߈?#{O@yA!4***5OA{¨#_`@!*)R* 9_?#{uS{#_?#{4@ R D9* ))|@CQ@9J @K4_ qT_qT$D9*R*R RC3*tS(!+B0 @@#3h@@"{B#_ ) T*? @ ) C @C_@_?#{ O(R9HAH!@ @)4 1@yj4+R? kT * +l1@yKL5_ kTh@!@yA 5h2@5h*@qT@{N@ ) k Jl% ) 1 %*OB @{è#_?#{WOHAH!@ @ 4 1@yj4+R? k`T * +l1@yKL5_ kT(R(0@3R4}@6RkT |F" *1_T 1*}_K+ Ȭ5;_T`OBWA{è#_?#{ A0R @)%?@ R)@#*A h@H@ @( (({B#_ ) T*? @B C@C_@_@a_?#{@ @9 %@RH%l A7L86-8@}S}SaS3}S3/@*A 3{=SR *I%l*@)@ +@yJ 87 @^Z}S}SaS{3}S3R*A 3I%=SJ2 2)@j*@yJ=P @!@9*{#_?#{OC@ @9@@! h@h @@( ((a@`@@9@! h@ @@( ((@`@@9@! h@ @@( ((@`@@9@! h @( @@( ((@` R@9@B h@h @*R@H!((@`"@@9@! h @@@( ((@`@@9@5 h@@@"((@`OC{A@#_ ) T R?֝ ) aT R?֣ ) T R?֩ ) T R?֯ ) A T!R?ֶ )  TR?ּ ) T*R?dB: *@@dB: *@@dB: *@@B ʯ ;>@@d ): * @@B ʯ ;>@@dB: *@߈߈߈߈߈ @(R @9?r+ A!ʚj( h*( _?#{@# @ @9@! h@h@ @( ((!{B#_ ) TR? @B C@C__@zR| (LD-DD  P DD-D @DD-D`X P   `XD-D (,D-DD T DD-@D-DpX P   pXD-D 0D-D H     HD-D (,D-DD D DD-(XXD-D H  x  HD-0D-D0L 0 p 0LD-(,D-DD T DD-,DD-D H  d  HD-<tD-DPT @  4 PTD-D 0TD-D0L   p 0LD-D HD-D`X `   `XD-D ,HD-D0H   0HD-D ,D-D H    HD-84D-D0L 0 X 0LD-D <pD-D@P @   @PD-D 0LD-D0L    0LD-D  ,D-D H  l  HD-8(pD-D0L 0  0LD-D Ld D-D\ `   \D-D HXD-D`X `   `XD-D @8D-DPT P   PTD-D 8DD-D0L 0 t 0LD-D 8PD-D@P @   @PD-D HHD-D\ `  t \D-D HD-D`X `   `XD-D HTD-Dp\ `  4 p\D-D 0xD-D0L 0 P 0LD-<HD-D@P @  @PD-0`D-D0L 0 x 0LD-4H`D-D0L 0 x 0LD-4xD-D0L 0 P 0LD-0D-D0L    0LD-D ,D-D H  D  HD-D @8D-DPT P  P PTD-D 4`D-D0L 0 X 0LD-D ( D-DD H DD-(D-D0H  p 0HD-D 4pD-D0L 0 H 0LD-(( (D-DD P DD-HT D-Dp\ ` l p\D-8 D-D@P 0  @PD-D 4 D-D0L 0 ` 0LD-( (D-DD P DD-H@ D-D\ `  \D-( D-D H  \  HD-D 0 LD-D0L 0 d 0LD-( $D-DD L DD- <, D-D`T @  4 `TD-D ,l D-D H    HD- , (  T T( tD-DD  x DD-D , (@ DD-DD l DD-,l D-D H    HD-@ D-DPT P   PTD-D 0 pD-D H   x  HD-D  (( 4D-DD \ DD-,T D-D0H  | 0HD-D 0 D-D0L 0  0LD-4 D-D0L 0  0LD-, D-D0H  H 0HD-D   (4(D-DD  DD-4`D-D@P 0  @PD-D ,,D-D0H  @ 0HD-D ,@Th|0DXl    4H \p?#{!{#_?#{{#_$$parmtype=force_stage:intparm=force_stage:Force SMMU mappings to be installed at a particular stage of translation. A value of '1' or '2' forces the corresponding stage. All other values are ignored (i.e. no stage is forced). Note that selecting a specific stage will disable support for nested translation.parmtype=disable_bypass:boolparm=disable_bypass:Disable bypass streams such that incoming transactions from devices that are not attached to an iommu domain will report an abort back to the device and will not be allowed to pass through the SMMU.description=IOMMU API for ARM architected SMMU implementationsauthor=Will Deacon alias=platform:arm-smmulicense=GPL v2vermagic=5.15.149-android14-11-gbff9ae650570-ab12001441 SMP preempt mod_unload modversions aarch64name=arm_smmuintree=Ydepends=qcom-scmalias=of:N*T*Carm,smmu-v1alias=of:N*T*Carm,smmu-v1C*alias=of:N*T*Carm,smmu-v2alias=of:N*T*Carm,smmu-v2C*alias=of:N*T*Carm,mmu-400alias=of:N*T*Carm,mmu-400C*alias=of:N*T*Carm,mmu-401alias=of:N*T*Carm,mmu-401C*alias=of:N*T*Carm,mmu-500alias=of:N*T*Carm,mmu-500C*alias=of:N*T*Ccavium,smmu-v2alias=of:N*T*Ccavium,smmu-v2C*alias=of:N*T*Cnvidia,smmu-500alias=of:N*T*Cnvidia,smmu-500C*alias=of:N*T*Cqcom,smmu-v2alias=of:N*T*Cqcom,smmu-v2C*scmversion=gbff9ae650570LinuxLinuxarm_smmu6Kmodule_layoutғ__stack_chk_failY of_match_deviceRΟqcom_scm_qsmmu500_wait_safe_toggleO qcom_scm_is_availableGof_match_nodedevm_kreallocȾof_device_is_compatible^ amba_bustype"&platform_bus_typeنpci_bus_typeתAcpu_hwcap_keys5arm64_const_caps_ready`kmalloc_caches Eparam_ops_boole@>k>r>r?lt?n?fH@nL@HP@H\@Dt@f@@@B@@@D@ @ @D@m@mAmAm0An4An\AdAhA|ABAAABAAABB B $B(B8B8A?A$?Ah?A? AtExF G$TH,L0O8,M<OD\MHOPMTO\W`WhlXl [tXx[Y[H\\\L\`\\\`_bh`bhhlhlliplPitlixli|lil .$X/(0.4X/8@/D8/HP/T8/X`82d`2hp<2t`2x3@83@8(4D4,4D4|5\85\89999:::: ;$;(0;4;8@8=D`=HP<=T`=X`?d?hp?t?xEEEE H4HH4H`]]d]]_a_affff   (08H '+(P'tmxm |m88` mmmm0mHmPm`mhmpmxmmmmmmmm8,nH8 H'Xh+x '  ( `(@+ ( ((8 H)X h*x  *  * p* * '(+8H+Xh+x@++ P   p8n n n( n0n8 n$n(nmmmmmmmmm0nnnmm n nn8nn@n(0n@DnPHnn n(+,  !x;<# !X6 Q b !! P t +L$  G,$z#k!XMz2,D $J#;!W fVH$| x({ C!u$0#(( !<;,(\WWL0(0(H+T`+(`Z$ +"l!+ P( +x`-{d-|h- Eh-<t- t-2.p $." .0.p/`@*/P $/t/ "t/ t8`<2{pE@2! 3#"3 ,404g155 x8X#x8" 99nS9 989 ;#t":x :;u;Z?,<  ;0 %;R0<P#0<!=x@[<=@P%@= =H=$As#d!AFA+AA`$?C#p4!?AOAxFEt<E|Fn$|F# !TH4HHiXHxXH]HHYHJ`!J xJ`S$xJ8 Jx"JPK PKGLLL8L,Ot8>OD$O"P Of ( OO!P P!PP QpQ7 RQ Q(YQ#R!SS"T$T3"UM"`U("`U U\W\WtW>4X#h" [ t[{[`[VxIx=pxfxK0\,*0\\\#"`\8d\( d\;\\ \T\gL\m \T\P]tP]#d]m"q h]Q] ]n]S(^x`.x^8^b%_#!_qb bpTbc9c`0c40cpdcdcddddHXe$Xel#]!fx?f Xf$Xf g  g6,g(,gThThz$hl<#-!llHpltlmxl5g$|l#!ll,-lllpmtm|mRmmL$m"m mmmmmmm7mm$m"m mmmmmRmmm#m"n nnn4nm8n7DnHnLn#Pn"Tn Xn (t&$Y"4 #O (( 4Q #'z" ~  !#${,?k%I{$`EP'#f"j g L1'$0#P!PjM2'p ($xe#`(V!q8((s)$05#*&!PA *pp*f*.`$#* !&0pKE$`" + P@+p+f0pwpm{tmxm|mmmmmmmmmmmmm@m<mtm"mmmmmrm mmnm .m m m Nm m m'm m\nCnn^ nFn+nnn> n$nX(n,n0n4nW8n 9J!_Ac@J!`K!hK!&K!? @0K!uJ!@q`B CCK!uJ!Z@J!E FXK!0kK!G{K!G@K!GK!LK!GK!G@H )IJ KK! u @bvM )IO PK!Fy @y R SK!0gaTxaV@7`T?`T; X@U )W )Y )[K!PK!@]L!G! L!@L!H&L! `_4L!07]EL!`@SL!baL!dpL!vzL!v@a "c "e fgL!( : @L!  L! L! L! cjT " G!L! kL! m ]L! n G!fb M! p!M! m G!p8M! sTM! î G!jM! vM! v s$M! yM! îM! gEM! M! N! N!  G!=2N! AN! sTN! s CWhN! yN! MN! M N]`:`e^^YN!  ^N]`:^^rsN! N! M N][sN! N! M \ O! #O! ѯ;O! ѯSO! vMiO! N N] O!  \+nO!  \%O! O!  7]O!  `:l^<^7]O!  [s`:<^7]P! 6P!  `:l^<^7]qOP! iP! P! P! P! P! P! kP! k G! Q!  G!lQ!  G!l 1Q! DQ! kZQ!  G!= kQ!  }Q!Q!R[\Q! Q! Q! Q! kQ! kQ! R! )R! s>R!  }Q!G!\k/\R!  G!pq R!  "7]R!  7]Q!"R!  7]pfR!  7]R!  7]S! arm_smmu_match_dataarm_smmu_arch_versionARM_SMMU_V1ARM_SMMU_V1_64KARM_SMMU_V2arm_smmu_implementationGENERIC_SMMUARM_MMU500CAVIUM_SMMUV2QCOM_SMMUV2arm_smmu_cbar_typeCBAR_TYPE_S2_TRANSCBAR_TYPE_S1_TRANS_S2_BYPASSCBAR_TYPE_S1_TRANS_S2_FAULTCBAR_TYPE_S1_TRANS_S2_TRANSarm_smmu_context_fmtARM_SMMU_CTX_FMT_NONEARM_SMMU_CTX_FMT_AARCH64ARM_SMMU_CTX_FMT_AARCH32_LARM_SMMU_CTX_FMT_AARCH32_Sarm_smmu_domain_stageARM_SMMU_DOMAIN_S1ARM_SMMU_DOMAIN_S2ARM_SMMU_DOMAIN_NESTEDARM_SMMU_DOMAIN_BYPASSarm_smmu_s2cr_typeS2CR_TYPE_TRANSS2CR_TYPE_BYPASSS2CR_TYPE_FAULTarm_smmu_s2cr_privcfgS2CR_PRIVCFG_DEFAULTS2CR_PRIVCFG_DIPANS2CR_PRIVCFG_UNPRIVS2CR_PRIVCFG_PRIVarm_smmu_domainsmmupgtbl_opspgtbl_quirksflush_opsinit_mutexarm_smmu_devicenumpagepgshiftimplnum_context_banksnum_s2_context_bankscontext_mapirptndxnum_mapping_groupsstreamid_masksmr_mask_masksmrss2crsstream_map_mutexva_sizeipa_sizepa_sizenum_global_irqsnum_context_irqsglobal_sync_lockarm_smmu_implread_reg64write_reg64cfg_probeinit_contexttlb_syncglobal_faultcontext_faultalloc_context_bankwrite_s2crwrite_sctlrarm_smmu_cbasidarm_smmu_cfgcbndxcbarflush_walk_prefer_tlbiasidarm_smmu_smrarm_smmu_s2crprivcfgarm_smmu_master_cfgsmendxcavium_smmuid_basenvidia_smmutegra_mcgartsoctegra_smmugart_devicetegra_mc_socnum_clientsemem_regsnum_emem_regsnum_address_bitsclient_id_maskreset_opsnum_resetsicc_opsswgrouptegra_mc_clienttegra_smmu_socswgroupsnum_swgroupssupports_round_robin_arbitrationsupports_request_limitnum_tlb_linesnum_asidstegra_smmu_swgrouptegra_smmu_group_soctegra_mc_reset_opshotreset_asserthotreset_deassertblock_dmadma_idlingunblock_dmareset_statustegra_mc_resettegra_mc_icc_opstegra_mc_opstegra_mc_timingemem_dataqcom_smmubypass_quirkbypass_cbndxstall_enabledadreno_smmu_privget_ttbr1_cfgset_ttbr0_cfgget_fault_infoset_stallresume_translationadreno_smmu_fault_infocontextidrfsynr0fsynr1cbfrsynraarm_smmu_device_cfg_probearm_smmu_global_faultarm_smmu_domain_alloc__arm_smmu_tlb_syncarm_smmu_context_faultarm_smmu_write_context_bankarm_smmu_device_probearm_smmu_device_resetarm_smmu_test_smr_masksarm_smmu_bus_initarm_smmu_device_removearm_smmu_device_shutdownarm_smmu_runtime_suspendarm_smmu_pm_suspendarm_smmu_runtime_resumearm_smmu_pm_resumearm_smmu_readlarm_smmu_write_smearm_smmu_write_s2crarm_smmu_capablearm_smmu_domain_freearm_smmu_attach_devarm_smmu_map_pagesarm_smmu_unmap_pagesarm_smmu_flush_iotlb_allarm_smmu_iotlb_syncarm_smmu_iova_to_physarm_smmu_probe_devicearm_smmu_release_devicearm_smmu_probe_finalizearm_smmu_device_grouparm_smmu_enable_nestingarm_smmu_set_pgtable_quirksarm_smmu_get_resv_regionsarm_smmu_of_xlatearm_smmu_def_domain_typearm_smmu_tlb_inv_context_s2arm_smmu_tlb_inv_walk_s2_v1arm_smmu_tlb_add_page_s2_v1arm_smmu_tlb_inv_walk_s2arm_smmu_tlb_inv_range_s2arm_smmu_tlb_add_page_s2arm_smmu_tlb_inv_context_s1arm_smmu_tlb_inv_walk_s1arm_smmu_tlb_inv_range_s1arm_smmu_tlb_add_page_s1cavium_cfg_probearm_mmu500_resetarm_smmu_impl_initmrvl_mmu500_readqmrvl_mmu500_writeqmrvl_mmu500_cfg_probearm_smmu_read_nsarm_smmu_write_nssmmu_domainpgtbl_cfgcavium_init_contextnvidia_smmu_impl_initqcom_smmu_impl_initqcom_smmu_cfg_probeqcom_smmu500_resetqcom_smmu_init_contextqcom_smmu_def_domain_typeqcom_smmu_write_s2crqcom_adreno_smmu_init_contextqcom_adreno_smmu_alloc_context_bankqcom_adreno_smmu_write_sctlrqcom_adreno_smmu_get_ttbr1_cfgqcom_adreno_smmu_set_ttbr0_cfgqcom_adreno_smmu_get_fault_infoqcom_adreno_smmu_set_stallqcom_adreno_smmu_resume_translationk@P` a 20 +D @`nX`Sab@]@H(b)5,0@pCx)f@Cp)K@XL )%$ @UH) P@0V)p@V)@] )@a)@a)J0b@b )LoXm01@,@o0)#|]$( 0o0ox?+:pz%&