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TLBMCF stage 2 translation &smmu->stream_map_mutexnvidia,tegra234-smmu ASFFSYNR0 = %08x [S1CBNDX=%u%s%s%s%s%s%s PLVL=%u] address translation ops preserved %d boot mapping%s enabling workaround for Cavium erratum 27704 qcom,msm8998-smmu-v2not probing due to mismatched DT properties stream-match-maskqcom_tbu (IDR0.CTTW overridden by FW configuration) SMR mask 0x%x out of range for SMMU (0x%x) failed to allocate %d irqs #global-interruptsnvidia,tegra186-smmu PTWF TF GFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x 5arm-smmu: deprecated "mmu-masters" DT property in use; %s support unavailable SMMU stage 1 translation %u context banks (%u stage-2 only) failed to set DMA mask for table walker Unexpected global fault, this could be serious Limiting the stream matching groups to 128 nested translation disabling translation Unhandled context fault: fsr=0x%x, iova=0x%08lx, fsynr=0x%x, cbfrsynra=0x%x, cb=%d arm-smmu-context-faultcalxeda,smmu-secure-config-accessarm_smmu_global_faultarm_smmu_context_faultSMMUv%d with: %scoherent table walk SMMU address space size (0x%x) differs from mapped region size (0x%x)! marvell,ap806-smmu-500Missing qcom_smmu_impl_of_match entry for: %s NSATTRstream-matching supported, but no SMRs present! &smmu_domain->init_mutexfailed to request context IRQ %d (%u) Failed to turn off SAFE logic qcom_scm not ready TLBLKFarm-smmumissing #global-interrupts property translation fault! SS WNRFailed to register iommu in sysfs no translation support! Supported page sizes: 0x%08lx Blocked unknown Stream ID 0x%hx; boot with "arm-smmu.disable_bypass=0" to allow, but this may have security implications stream matching with %u register groupsnvidia,tegra194-smmu PF AFR INDnon-TLB sync timed out -- SMMU may be deadlocked iova to phys timed out on %pad. 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