ELF@@&#_zR| (,D-DD T DD-(D$D-DD L DD-@p`D-DT @   TD-D 4hD-D0L 0  0LD-D 0D-D0L 0  0LD-4 D-DpP 0  pPD-D 8XD-D@P @  @PD-( D-DD H DD-4D-D0L 0  0LD-<\D-D@P @   @PD-D <8D-D@P @  \ @PD-D 0xD-D0L 0 X 0LD-4|D-D0L 0 T 0LD-0D-D0L 0 t 0LD-(D-DD D DD-8DD-D@P @  @PD-4D-D0L 0 \ 0LD-8DD-D@P @  @PD-8pD-D0L 0  0LD-D |?#{_WO A8@ C,RR(RFX!B@RS~ț!T@R}>qKT} '@>@kijJ!? i(a!T>@vmk** 5@ )#B@T!c4*@M!RA5@!##RB*1T*7@@&&@?"T@RB*V5"B!F"B*5**5*4A8 C_ T*OIWH_G{F#_B?"T>Bc@>v!*?#{ O@*B?` "T*?`"T"R?`"TBR?`"TbR?`"TR?`"TOB @{è#_R@胀h?`.TB  F`7`j!t?#{ O@@@*B? T@yh @yh @yhh@yRRh@yh@yh@yu@h"`2RRhj5!?`.TBt@RR`:HRAR**%Rhn4*B`OB @{è#_?#{+OA8 C!5@(Rhr"`5!5@!c4*@!**A8 C_ TOF+@{D#_VK?#{ WO*4XAkT`*hAtZ4`@(h@=@n@:@@j@2@**R@>@`@D`@`*OC @WB{Ĩ#_}?#{@{#_?#{WO<@.@@.@@@`02aM`+.@@@`&taC`!.@@@`xa9`OBWA{è#_?#{_WO<@@>@@R@5n@:@`5n@:@5j@2@** 5*@4**n@:@R@>@*OCWB_A{Ĩ#_.@@2ZA@ qHR*@*!***@!*@!?#{ WO<@@@@Az T.@`5@5@"@qT@qsbThB@96h@)@2@qT@qsbThB@96h@)@"@qT@qsbThB@96h@)@2@qT"@qsbThB@96h@)@@VB@qTqb@TB@94@)ax @qsbThB@94h@)m@.@@`Gxad`B.@@@`=2aZ`8.@@ @1@06h&fLT`RRBR? ՠ$77 07*OC @WB{Ĩ#_**@!**@!.@ ?#{ O BRh@1*cR*OB @{è#_?#{WO* *cR2vcROBWA{è#_?#{ O@RR:&@AR**%RHR n4*B`OB @{è#_}?#{{#_>M?#{_WO<@*t* 5*@4>@n@:@@j@2@**S@>@A*OCWB_A{Ĩ#_>M?#{WO<@ A)Q u>@n@:@@j@2@**R@>@*OBWA{è#_Bpp<@*_ description=Qualcomm QMP USB-C PHY driverlicense=GPLname=phy_qcom_qmp_usbcintree=Yscmversion=ga9c2663f637fdepends=alias=of:N*T*Cqcom,msm8998-qmp-usb3-phyalias=of:N*T*Cqcom,msm8998-qmp-usb3-phyC*alias=of:N*T*Cqcom,qcm2290-qmp-usb3-phyalias=of:N*T*Cqcom,qcm2290-qmp-usb3-phyC*alias=of:N*T*Cqcom,sdm660-qmp-usb3-phyalias=of:N*T*Cqcom,sdm660-qmp-usb3-phyC*alias=of:N*T*Cqcom,sm6115-qmp-usb3-phyalias=of:N*T*Cqcom,sm6115-qmp-usb3-phyC*vermagic=6.12.0-mainline-ga9c2663f637f-ab12743383-4k SMP preempt mod_unload modversions aarch64QSERDES_V3_COM_LOCK_CMP_CFGQSERDES_V3_TX_LANE_MODE_1QSERDES_V3_RX_UCDR_FO_GAINUnable to register typec switch: %pe reset assert failed qcom,tcsr-regQSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2QSERDES_COM_SSC_PER1qmp_usbc_typec_unregisterrefQSERDES_V3_COM_LOCK_CMP3_MODE0QSERDES_V3_COM_SSC_PER1QSERDES_V3_TX_HIGHZ_DRVR_ENQSERDES_V3_RX_SIGDET_CNTRLQPHY_V3_PCS_TXDEEMPH_M6DB_V1QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4QSERDES_V3_COM_SYS_CLK_CTRLQSERDES_V3_COM_PLL_RCTRL_MODE0QPHY_V3_PCS_LOCK_DETECT_CONFIG1QPHY_V3_PCS_TXDEEMPH_M6DB_V3vdda-phyQSERDES_COM_SYS_CLK_CTRLQSERDES_COM_LOCK_CMP_CFGQSERDES_COM_INTEGLOOP_INITVALphy_phyQSERDES_V3_COM_DIV_FRAC_START1_MODE0QPHY_V3_PCS_LOCK_DETECT_CONFIG3QSERDES_COM_SVS_MODE_CLK_SELQSERDES_COM_DIV_FRAC_START1_MODE0QPHY_V3_PCS_TXDEEMPH_M3P5DB_LSQSERDES_COM_RESETSM_CNTRLQSERDES_COM_VCO_TUNE_MAPpipeQSERDES_V3_COM_CORECLK_DIV_MODE0QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOWQPHY_V3_PCS_TXDEEMPH_M3P5DB_V0QPHY_V3_PCS_TXDEEMPH_M6DB_LScommonQSERDES_V3_COM_SYSCLK_EN_SELQSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0QPHY_V3_PCS_RATE_SLEW_CNTRL&qmp->phy_mutexFailed to parse qcom,tcsr-reg QSERDES_V3_COM_SSC_ADJ_PER1auxcfg_ahbQSERDES_V3_COM_VCO_TUNE2_MODE0QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4QSERDES_V3_RX_UCDR_SO_GAINQPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCKQSERDES_COM_CLK_SELECTQSERDES_COM_SSC_ADJ_PER1QSERDES_COM_BIAS_EN_CTRL_BY_PSMphy initialization timed-out QSERDES_COM_DIV_FRAC_START2_MODE0QPHY_V3_PCS_TXMGN_V4QSERDES_V3_RX_VGA_CAL_CNTRL2failed to get pipe clock QSERDES_V3_COM_LOCK_CMP_ENQSERDES_COM_INTEGLOOP_GAIN1_MODE0QSERDES_V3_COM_CLK_SELECTQSERDES_V3_COM_HSCLK_SELQSERDES_V3_COM_CP_CTRL_MODE0QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLEQSERDES_COM_CORECLK_DIVQSERDES_V3_TX_RES_CODE_LANE_OFFSET_RXfailed to enable regulators, err=%d QSERDES_V3_COM_PLL_CCTRL_MODE0QSERDES_V3_COM_VCO_TUNE1_MODE0QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAINQSERDES_V3_RX_RX_MODE_00QPHY_V3_PCS_FLL_CNT_VAL_LQPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_HQPHY_V3_PCS_RCVR_DTCT_DLY_U3_LQSERDES_COM_PLL_RCTRL_MODE0QSERDES_V3_COM_CMN_CONFIGQSERDES_V3_COM_SSC_STEP_SIZE2QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1QPHY_V3_PCS_TXDEEMPH_M6DB_V2QSERDES_COM_LOCK_CMP_ENQSERDES_COM_CORE_CLK_ENQSERDES_COM_BG_TIMERfailed to get resets QSERDES_V3_COM_CORE_CLK_ENQSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3QPHY_V3_PCS_LOCK_DETECT_CONFIG2QSERDES_COM_RESETSM_CNTRL2QSERDES_COM_LOCK_CMP1_MODE0QSERDES_COM_SSC_PER2QSERDES_V3_TX_RCV_DETECT_LVL_2clock-output-namesQSERDES_V3_COM_RESETSM_CNTRL2QSERDES_V3_COM_SSC_PER2QPHY_V3_PCS_RXEQTRAINING_WAIT_TIMEQSERDES_V3_COM_LOCK_CMP2_MODE0QSERDES_V3_COM_SSC_STEP_SIZE1QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TXQPHY_V3_PCS_FLL_CNTRL2QPHY_V3_PCS_TXMGN_V1QPHY_V3_PCS_TXMGN_V2QPHY_V3_PCS_TXMGN_V3QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLKQPHY_V3_PCS_RX_SIGDET_LVLqcom-qmp-usbc-phyQSERDES_V3_COM_SSC_EN_CENTERQSERDES_V3_RX_SIGDET_ENABLESQPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_LQSERDES_COM_INTEGLOOP_GAIN0_MODE0com_auxQSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1QPHY_V3_PCS_TXMGN_V0QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3QSERDES_COM_PLL_CCTRL_MODE0QSERDES_V3_COM_BIAS_EN_CLKBUFLR_ENQPHY_V3_PCS_TXMGN_LSQSERDES_COM_SYSCLK_EN_SELQSERDES_V3_COM_DIV_FRAC_START2_MODE0QSERDES_V3_COM_CMN_MODEQSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGHQSERDES_COM_LOCK_CMP3_MODE0QSERDES_V3_COM_DIV_FRAC_START3_MODE0QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2vdda-pllQSERDES_COM_BIAS_EN_CLKBUFLR_ENQSERDES_COM_HSCLK_SELQSERDES_COM_DIV_FRAC_START3_MODE0QSERDES_COM_PLL_IVCOQSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0QSERDES_V3_COM_SSC_ADJ_PER2QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRLQPHY_V3_PCS_FLL_CNT_VAL_H_TOLQSERDES_COM_SSC_EN_CENTERpipe_clk enable failed err=%d QPHY_V3_PCS_FLL_CNTRL1QPHY_V3_PCS_TXDEEMPH_M6DB_V0QPHY_V3_PCS_TSYNC_RSYNC_TIME%pOFn: No clock-output-names QSERDES_V3_COM_LOCK_CMP1_MODE0QSERDES_V3_COM_VCO_TUNE_MAPQPHY_V3_PCS_TXDEEMPH_M6DB_V4QSERDES_COM_BG_TRIMQSERDES_COM_CP_CTRL_MODE0QSERDES_COM_CMN_CONFIGphyphy_clk_release_providerQSERDES_V3_COM_PLL_IVCOQPHY_V3_PCS_FLL_MAN_CODEQPHY_V3_PCS_POWER_STATE_CONFIG2QSERDES_COM_DEC_START_MODE0QSERDES_COM_LOCK_CMP2_MODE0QSERDES_COM_SSC_STEP_SIZE1reset deassert failed pipe_clk enable failed, err=%d QSERDES_V3_COM_SVS_MODE_CLK_SELQSERDES_V3_COM_DEC_START_MODE0QSERDES_V3_COM_BG_TIMERQSERDES_V3_COM_INTEGLOOP_INITVALQSERDES_V3_RX_UCDR_PI_CONTROLSQPHY_V3_PCS_RCVR_DTCT_DLY_U3_HQPHY_V3_PCS_RXEQTRAINING_RUN_TIMEQSERDES_COM_SSC_ADJ_PER2QSERDES_COM_SSC_STEP_SIZE2failed to create PHY: %d phy_qcom_qmp_usbcOv __platform_driver_registerP\platform_driver_unregister֤devm_kmallociof_device_get_match_dataS+__mutex_init@.devm_regulator_bulk_get7̋typec_switch_register'__devm_add_action)typec_switch_unregisterV_dev_err(&H__of_parse_phandle_with_args:Nisyscon_node_to_regmap"kof_node_putIXdev_err_probe9Lof_get_child_by_name"of_node_getE __pm_runtime_set_status^devm_pm_runtime_enable {pm_runtime_forbidVdevm_phy_created of_phy_simple_xlate__devm_of_phy_provider_register__stack_chk_failQdevm_platform_ioremap_resource؛=devm_of_iomapԨsdevm_get_clk_from_childvdevm_clk_bulk_get_allIdevm_clk_bulk_get_optional devm_clk_gets__devm_reset_control_bulk_get<of_property_read_stringSclk_fixed_rate_opsNdevm_clk_hw_registerqOof_clk_hw_simple_getof_clk_add_hw_provider33of_clk_del_providermtypec_switch_get_drvdata&{Hmutex_lock_nestedfreset_control_bulk_assertK}Gclk_bulk_disable)cclk_bulk_unprepare 8;regulator_bulk_disableO xtIt# ttt t tG t 8 t|P tsh t t t6 t t+ t tm td ( t@ t"X tp ty t t t t t t{  t 0 t H t` tO x t t tb t4 tS t  t t 8 t#P th t t t t t tH t t( t@ t X t p t t3 T T T T T TT td 0tP Ht`txtt* t@ttp tt t8t PtThtt ti t ttE tt (tp@tXt8pt4tt@tta t*tUt+0tnHt `tnxtQtCt+tv tt> t tI8tPtsht t6tt|t# ttt (t@tXtGpt t+ tmt tttd ty0tHt"`txtt tt t3tt t8tH Pthttt TTTTTTT tI(t@tsXt pt6tt|t# ttt t0tHtG`t xt+ tm@QHQXQT`QxQyttx{Q(t PTAndroid (12701618, +pgo, +bolt, +lto, +mlgo, based on r536225) clang version 19.0.1 (https://android.googlesource.com/toolchain/llvm-project b3a530ec6537146650e42be89f1089e9a3588460)RHStQQdQ$Q\QQxQQT <Q |Q QQQ4HQTQQQ Qmp  %(+.19