1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __BASEBOARD_VARIANTS_H__ 4 #define __BASEBOARD_VARIANTS_H__ 5 6 #include <soc/gpio.h> 7 #include <soc/meminit.h> 8 #include <stdint.h> 9 10 enum adl_boardid { 11 /* ADL-P LPDDR4 RVPs */ 12 ADL_P_LP4_1 = 0x10, 13 ADL_P_LP4_2 = 0x11, 14 /* ADL-P DDR5 RVPs */ 15 ADL_P_DDR5_1 = 0x12, 16 ADL_P_DDR5_2 = 0x16, 17 /* ADL-P LPDDR5 RVP */ 18 ADL_P_LP5_1 = 0x13, 19 ADL_P_LP5_2 = 0x17, 20 /* ADL-P DDR4 RVPs */ 21 ADL_P_DDR4_1 = 0x14, 22 ADL_P_DDR4_2 = 0x3F, 23 /* ADL-M LP4 and LP5 RVPs */ 24 ADL_M_LP4 = 0x1, 25 ADL_M_LP5 = 0x2, 26 /* ADL-N LP5 RVP */ 27 ADL_N_LP5 = 0x7, 28 }; 29 30 /* Functions to configure GPIO as per variant schematics */ 31 void variant_configure_gpio_pads(void); 32 void variant_configure_early_gpio_pads(void); 33 34 size_t variant_memory_sku(void); 35 const struct mb_cfg *variant_memory_params(void); 36 void rpl_memory_params(FSPM_UPD *memupd); 37 38 /* Modify devictree settings during ramstage */ 39 void variant_devtree_update(void); 40 struct cpu_power_limits { 41 uint16_t mchid; 42 u8 cpu_tdp; 43 unsigned int pl1_min_power; 44 unsigned int pl1_max_power; 45 unsigned int pl2_min_power; 46 unsigned int pl2_max_power; 47 unsigned int pl4_power; 48 }; 49 /* Modify Power Limit devictree settings during ramstage */ 50 void variant_update_power_limits(void); 51 52 #endif /*__BASEBOARD_VARIANTS_H__ */ 53